source: rtems/c/src/lib/libbsp/powerpc/shared/openpic/openpic.h @ e79a1947

4.104.114.84.95
Last change on this file since e79a1947 was e79a1947, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 10, 2004 at 11:51:17 PM

2004-11-10 Richard Campbell <richard.campbell@…>

  • Makefile.am, bootloader/misc.c, bootloader/pci.c, bootloader/pci.h, console/console.c, console/inch.c, console/reboot.c, console/uart.c, console/uart.h, irq/irq.c, irq/irq.h, irq/irq_init.c, motorola/motorola.c, motorola/motorola.h, openpic/openpic.c, openpic/openpic.h, pci/detect_raven_bridge.c, pci/pci.c, start/start.S, startup/bspstart.c, vectors/vectors_init.c, vme/vmeconfig.c: Add MVME2100 BSP and MPC8240 support. There was also a significant amount of spelling and whitespace cleanup.
  • tod/todcfg.c: New file.
  • Property mode set to 100644
File size: 9.2 KB
Line 
1/*
2 *  openpic.h -- OpenPIC definitions
3 *
4 *  Copyright (C) 1997 Geert Uytterhoeven
5 *
6 *  This file is based on the following documentation:
7 *
8 *      The Open Programmable Interrupt Controller (PIC)
9 *      Register Interface Specification Revision 1.2
10 *
11 *      Issue Date: October 1995
12 *
13 *      Issued jointly by Advanced Micro Devices and Cyrix Corporation
14 *
15 *      AMD is a registered trademark of Advanced Micro Devices, Inc.
16 *      Copyright (C) 1995, Advanced Micro Devices, Inc. and Cyrix, Inc.
17 *      All Rights Reserved.
18 *
19 *  To receive a copy of this documentation, send an email to openpic@amd.com.
20 *
21 *  This file is subject to the terms and conditions of the GNU General Public
22 *  License.  See the file COPYING in the main directory of this archive
23 *  for more details.
24 *
25 *  Modified to compile in RTEMS development environment
26 *  by Eric Valette
27 *
28 *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
29 *
30 *  The license and distribution terms for this file may be
31 *  found in found in the file LICENSE in this distribution or at
32 *  http://www.rtems.com/license/LICENSE.
33 *
34 * $Id$
35 */
36
37#ifndef _RTEMS_OPENPIC_H
38#define _RTEMS_OPENPIC_H
39
40    /*
41     *  OpenPIC supports up to 2048 interrupt sources and up to 32 processors
42     */
43
44#if defined(mpc8240) || defined(mpc8245)
45#define OPENPIC_MAX_SOURCES    (2048 - 16)
46#else
47#define OPENPIC_MAX_SOURCES     2048
48#endif
49#define OPENPIC_MAX_PROCESSORS  32
50
51#define OPENPIC_NUM_TIMERS      4
52#define OPENPIC_NUM_IPI         4
53#define OPENPIC_NUM_PRI         16
54#define OPENPIC_NUM_VECTORS     256
55
56    /*
57     *  Vector numbers
58     */
59
60#define OPENPIC_VEC_SOURCE      0x10    /* and up */
61#define OPENPIC_VEC_TIMER       0x40    /* and up */
62#define OPENPIC_VEC_IPI         0x50    /* and up */
63#define OPENPIC_VEC_SPURIOUS    99
64
65    /*
66     *  OpenPIC Registers are 32 bits and aligned on 128 bit boundaries
67     */
68
69typedef struct _OpenPIC_Reg {
70    unsigned int Reg;                                   /* Little endian! */
71    char Pad[0xc];
72} OpenPIC_Reg;
73
74    /*
75     *  Per Processor Registers
76     */
77
78typedef struct _OpenPIC_Processor {
79    /*
80     *  Private Shadow Registers (for SLiC backwards compatibility)
81     */
82    unsigned int IPI0_Dispatch_Shadow;                  /* Write Only */
83    char Pad1[0x4];
84    unsigned int IPI0_Vector_Priority_Shadow;           /* Read/Write */
85    char Pad2[0x34];
86    /*
87     *  Interprocessor Interrupt Command Ports
88     */
89    OpenPIC_Reg _IPI_Dispatch[OPENPIC_NUM_IPI]; /* Write Only */
90    /*
91     *  Current Task Priority Register
92     */
93    OpenPIC_Reg _Current_Task_Priority;         /* Read/Write */
94    char Pad3[0x10];
95    /*
96     *  Interrupt Acknowledge Register
97     */
98    OpenPIC_Reg _Interrupt_Acknowledge;         /* Read Only */
99    /*
100     *  End of Interrupt (EOI) Register
101     */
102    OpenPIC_Reg _EOI;                           /* Read/Write */
103    char Pad5[0xf40];
104} OpenPIC_Processor;
105
106    /*
107     *  Timer Registers
108     */
109
110typedef struct _OpenPIC_Timer {
111    OpenPIC_Reg _Current_Count;                 /* Read Only */
112    OpenPIC_Reg _Base_Count;                    /* Read/Write */
113    OpenPIC_Reg _Vector_Priority;               /* Read/Write */
114    OpenPIC_Reg _Destination;                   /* Read/Write */
115} OpenPIC_Timer;
116
117    /*
118     *  Global Registers
119     */
120
121typedef struct _OpenPIC_Global {
122    /*
123     *  Feature Reporting Registers
124     */
125    OpenPIC_Reg _Feature_Reporting0;            /* Read Only */
126    OpenPIC_Reg _Feature_Reporting1;            /* Future Expansion */
127    /*
128     *  Global Configuration Registers
129     */
130    OpenPIC_Reg _Global_Configuration0;         /* Read/Write */
131    OpenPIC_Reg _Global_Configuration1;         /* Future Expansion */
132    /*
133     *  Vendor Specific Registers
134     */
135    OpenPIC_Reg _Vendor_Specific[4];
136    /*
137     *  Vendor Identification Register
138     */
139    OpenPIC_Reg _Vendor_Identification;         /* Read Only */
140    /*
141     *  Processor Initialization Register
142     */
143    OpenPIC_Reg _Processor_Initialization;      /* Read/Write */
144    /*
145     *  IPI Vector/Priority Registers
146     */
147    OpenPIC_Reg _IPI_Vector_Priority[OPENPIC_NUM_IPI];  /* Read/Write */
148    /*
149     *  Spurious Vector Register
150     */
151    OpenPIC_Reg _Spurious_Vector;               /* Read/Write */
152    /*
153     *  Global Timer Registers
154     */
155    OpenPIC_Reg _Timer_Frequency;               /* Read/Write */
156    OpenPIC_Timer Timer[OPENPIC_NUM_TIMERS];
157    char Pad1[0xee00];
158#if defined(mpc8240) || defined(mpc8245)
159    char Pad2[0x0200];
160#endif 
161} OpenPIC_Global;
162
163    /*
164     *  Interrupt Source Registers
165     */
166
167typedef struct _OpenPIC_Source {
168    OpenPIC_Reg _Vector_Priority;               /* Read/Write */
169    OpenPIC_Reg _Destination;                   /* Read/Write */
170} OpenPIC_Source;
171
172    /*
173     *  OpenPIC Register Map
174     */
175
176struct OpenPIC {
177    char Pad1[0x1000];
178    /*
179     *  Global Registers
180     */
181    OpenPIC_Global Global;
182    /*
183     *  Interrupt Source Configuration Registers
184     */
185    OpenPIC_Source Source[OPENPIC_MAX_SOURCES];
186    /*
187     *  Per Processor Registers
188     */
189    OpenPIC_Processor Processor[OPENPIC_MAX_PROCESSORS];
190};
191
192extern volatile struct OpenPIC *OpenPIC;
193
194    /*
195     *  Current Task Priority Register
196     */
197
198#define OPENPIC_CURRENT_TASK_PRIORITY_MASK      0x0000000f
199
200    /*
201     *  Who Am I Register
202     */
203
204#define OPENPIC_WHO_AM_I_ID_MASK                0x0000001f
205
206    /*
207     *  Feature Reporting Register 0
208     */
209
210#define OPENPIC_FEATURE_LAST_SOURCE_MASK        0x07ff0000
211#define OPENPIC_FEATURE_LAST_SOURCE_SHIFT       16
212#define OPENPIC_FEATURE_LAST_PROCESSOR_MASK     0x00001f00
213#define OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT    8
214#define OPENPIC_FEATURE_VERSION_MASK            0x000000ff
215
216    /*
217     *  Global Configuration Register 0
218     */
219
220#define OPENPIC_CONFIG_RESET                    0x80000000
221#define OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE 0x20000000
222#define OPENPIC_CONFIG_BASE_MASK                0x000fffff
223
224    /*
225     *  Vendor Identification Register
226     */
227
228#define OPENPIC_VENDOR_ID_STEPPING_MASK         0x00ff0000
229#define OPENPIC_VENDOR_ID_STEPPING_SHIFT        16
230#define OPENPIC_VENDOR_ID_DEVICE_ID_MASK        0x0000ff00
231#define OPENPIC_VENDOR_ID_DEVICE_ID_SHIFT       8
232#define OPENPIC_VENDOR_ID_VENDOR_ID_MASK        0x000000ff
233
234    /*
235     *  Vector/Priority Registers
236     */
237
238#define OPENPIC_MASK                            0x80000000
239#define OPENPIC_ACTIVITY                        0x40000000      /* Read Only */
240#define OPENPIC_PRIORITY_MASK                   0x000f0000
241#define OPENPIC_PRIORITY_SHIFT                  16
242#define OPENPIC_VECTOR_MASK                     0x000000ff
243
244    /*
245     *  Interrupt Source Registers
246     */
247
248#define OPENPIC_SENSE_POLARITY                  0x00800000      /* Undoc'd */
249#define OPENPIC_SENSE_LEVEL                     0x00400000
250
251    /*
252     *  Timer Registers
253     */
254
255#define OPENPIC_COUNT_MASK                      0x7fffffff
256#define OPENPIC_TIMER_TOGGLE                    0x80000000
257#define OPENPIC_TIMER_COUNT_INHIBIT             0x80000000
258
259    /*
260     *  Aliases to make life simpler
261     */
262
263/* Per Processor Registers */
264#define IPI_Dispatch(i)                 _IPI_Dispatch[i].Reg
265#define Current_Task_Priority           _Current_Task_Priority.Reg
266#define Interrupt_Acknowledge           _Interrupt_Acknowledge.Reg
267#define EOI                             _EOI.Reg
268
269/* Global Registers */
270#define Feature_Reporting0              _Feature_Reporting0.Reg
271#define Feature_Reporting1              _Feature_Reporting1.Reg
272#define Global_Configuration0           _Global_Configuration0.Reg
273#define Global_Configuration1           _Global_Configuration1.Reg
274#define Vendor_Specific(i)              _Vendor_Specific[i].Reg
275#define Vendor_Identification           _Vendor_Identification.Reg
276#define Processor_Initialization        _Processor_Initialization.Reg
277#define IPI_Vector_Priority(i)          _IPI_Vector_Priority[i].Reg
278#define Spurious_Vector                 _Spurious_Vector.Reg
279#define Timer_Frequency                 _Timer_Frequency.Reg
280
281/* Timer Registers */
282#define Current_Count                   _Current_Count.Reg
283#define Base_Count                      _Base_Count.Reg
284#define Vector_Priority                 _Vector_Priority.Reg
285#define Destination                     _Destination.Reg
286
287/* Interrupt Source Registers */
288#define Vector_Priority                 _Vector_Priority.Reg
289#define Destination                     _Destination.Reg
290
291    /*
292     *  Vendor and Device IDs
293     */
294
295#define OPENPIC_VENDOR_ID_APPLE         0x14
296#define OPENPIC_DEVICE_ID_APPLE_HYDRA   0x46
297
298    /*
299     *  OpenPIC Operations
300     */
301
302/* Global Operations */
303extern void openpic_init(int,unsigned char *, unsigned char *);
304extern void openpic_reset(void);
305extern void openpic_enable_8259_pass_through(void);
306extern void openpic_disable_8259_pass_through(void);
307extern unsigned int openpic_irq(unsigned int cpu);
308extern void openpic_eoi(unsigned int cpu);
309extern unsigned int openpic_get_priority(unsigned int cpu);
310extern void openpic_set_priority(unsigned int cpu, unsigned int pri);
311extern unsigned int openpic_get_spurious(void);
312extern void openpic_set_spurious(unsigned int vector);
313extern void openpic_init_processor(unsigned int cpumask);
314
315/* Interprocessor Interrupts */
316extern void openpic_initipi(unsigned int ipi, unsigned int pri, unsigned int vector);
317extern void openpic_cause_IPI(unsigned int cpu, unsigned int ipi, unsigned int cpumask);
318
319/* Timer Interrupts */
320extern void openpic_inittimer(unsigned int timer, unsigned int pri, unsigned int vector);
321extern void openpic_maptimer(unsigned int timer, unsigned int cpumask);
322
323/* Interrupt Sources */
324extern void openpic_enable_irq(unsigned int irq);
325extern void openpic_disable_irq(unsigned int irq);
326extern void openpic_initirq(unsigned int irq, unsigned int pri, unsigned int vector, int polarity,
327                            int is_level);
328extern void openpic_mapirq(unsigned int irq, unsigned int cpumask);
329extern void openpic_set_sense(unsigned int irq, int sense);
330extern unsigned int openpic_get_source_priority(unsigned int irq);
331extern void openpic_set_source_priority(unsigned int irq, unsigned int pri);
332
333#endif /* RTEMS_OPENPIC_H */
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