source: rtems/c/src/lib/libbsp/powerpc/shared/openpic/openpic.h @ c499856

4.115
Last change on this file since c499856 was c499856, checked in by Chris Johns <chrisj@…>, on 03/20/14 at 21:10:47

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1/*
2 *  openpic.h -- OpenPIC definitions
3 *
4 *  Copyright (C) 1997 Geert Uytterhoeven
5 *
6 *  This file is based on the following documentation:
7 *
8 *      The Open Programmable Interrupt Controller (PIC)
9 *      Register Interface Specification Revision 1.2
10 *
11 *      Issue Date: October 1995
12 *
13 *      Issued jointly by Advanced Micro Devices and Cyrix Corporation
14 *
15 *      AMD is a registered trademark of Advanced Micro Devices, Inc.
16 *      Copyright (C) 1995, Advanced Micro Devices, Inc. and Cyrix, Inc.
17 *      All Rights Reserved.
18 *
19 *  To receive a copy of this documentation, send an email to openpic@amd.com.
20 *
21 *  This file is subject to the terms and conditions of the GNU General Public
22 *  License.  See the file COPYING in the main directory of this archive
23 *  for more details.
24 *
25 *  Modified to compile in RTEMS development environment
26 *  by Eric Valette
27 *
28 *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
29 *
30 *  The license and distribution terms for this file may be
31 *  found in the file LICENSE in this distribution or at
32 *  http://www.rtems.org/license/LICENSE.
33 */
34
35#ifndef _RTEMS_OPENPIC_H
36#define _RTEMS_OPENPIC_H
37
38    /*
39     *  OpenPIC supports up to 2048 interrupt sources and up to 32 processors
40     */
41#define OPENPIC_MAX_SOURCES     2048
42#define OPENPIC_MAX_PROCESSORS  32
43
44#define OPENPIC_NUM_TIMERS      4
45#define OPENPIC_NUM_IPI         4
46#define OPENPIC_NUM_PRI         16
47#define OPENPIC_NUM_VECTORS     256
48
49    /*
50     *  Vector numbers
51     */
52
53#define OPENPIC_VEC_SOURCE      0x10    /* and up */
54#define OPENPIC_VEC_TIMER       0x40    /* and up */
55#define OPENPIC_VEC_IPI         0x50    /* and up */
56#define OPENPIC_VEC_SPURIOUS    99
57
58    /*
59     *  OpenPIC Registers are 32 bits and aligned on 128 bit boundaries
60     */
61
62typedef struct _OpenPIC_Reg {
63    unsigned int Reg;                                   /* Little endian! */
64    char Pad[0xc];
65} OpenPIC_Reg;
66
67    /*
68     *  Per Processor Registers
69     */
70
71typedef struct _OpenPIC_Processor {
72    /*
73     *  Private Shadow Registers (for SLiC backwards compatibility)
74     */
75    unsigned int IPI0_Dispatch_Shadow;                  /* Write Only */
76    char Pad1[0x4];
77    unsigned int IPI0_Vector_Priority_Shadow;           /* Read/Write */
78    char Pad2[0x34];
79    /*
80     *  Interprocessor Interrupt Command Ports
81     */
82    OpenPIC_Reg _IPI_Dispatch[OPENPIC_NUM_IPI]; /* Write Only */
83    /*
84     *  Current Task Priority Register
85     */
86    OpenPIC_Reg _Current_Task_Priority;         /* Read/Write */
87    char Pad3[0x10];
88    /*
89     *  Interrupt Acknowledge Register
90     */
91    OpenPIC_Reg _Interrupt_Acknowledge;         /* Read Only */
92    /*
93     *  End of Interrupt (EOI) Register
94     */
95    OpenPIC_Reg _EOI;                           /* Read/Write */
96    char Pad5[0xf40];
97} OpenPIC_Processor;
98
99    /*
100     *  Timer Registers
101     */
102
103typedef struct _OpenPIC_Timer {
104    OpenPIC_Reg _Current_Count;                 /* Read Only */
105    OpenPIC_Reg _Base_Count;                    /* Read/Write */
106    OpenPIC_Reg _Vector_Priority;               /* Read/Write */
107    OpenPIC_Reg _Destination;                   /* Read/Write */
108} OpenPIC_Timer;
109
110    /*
111     *  Global Registers
112     */
113
114typedef struct _OpenPIC_Global {
115    /*
116     *  Feature Reporting Registers
117     */
118    OpenPIC_Reg _Feature_Reporting0;            /* Read Only */
119    OpenPIC_Reg _Feature_Reporting1;            /* Future Expansion */
120    /*
121     *  Global Configuration Registers
122     */
123    OpenPIC_Reg _Global_Configuration0;         /* Read/Write */
124    OpenPIC_Reg _Global_Configuration1;         /* Future Expansion */
125    /*
126     *  Vendor Specific Registers
127     */
128    OpenPIC_Reg _Vendor_Specific[4];
129    /*
130     *  Vendor Identification Register
131     */
132    OpenPIC_Reg _Vendor_Identification;         /* Read Only */
133    /*
134     *  Processor Initialization Register
135     */
136    OpenPIC_Reg _Processor_Initialization;      /* Read/Write */
137    /*
138     *  IPI Vector/Priority Registers
139     */
140    OpenPIC_Reg _IPI_Vector_Priority[OPENPIC_NUM_IPI];  /* Read/Write */
141    /*
142     *  Spurious Vector Register
143     */
144    OpenPIC_Reg _Spurious_Vector;               /* Read/Write */
145    /*
146     *  Global Timer Registers
147     */
148    OpenPIC_Reg _Timer_Frequency;               /* Read/Write */
149    OpenPIC_Timer Timer[OPENPIC_NUM_TIMERS];
150    char Pad1[0xee00];
151} OpenPIC_Global;
152
153    /*
154     *  Interrupt Source Registers
155     */
156
157typedef struct _OpenPIC_Source {
158    OpenPIC_Reg _Vector_Priority;               /* Read/Write */
159    OpenPIC_Reg _Destination;                   /* Read/Write */
160} OpenPIC_Source;
161
162    /*
163     *  OpenPIC Register Map
164     */
165
166struct OpenPIC {
167    char Pad1[0x1000];
168    /*
169     *  Global Registers
170     */
171    OpenPIC_Global Global;
172    /*
173     *  Interrupt Source Configuration Registers
174     */
175    OpenPIC_Source Source[OPENPIC_MAX_SOURCES];
176    /*
177     *  Per Processor Registers
178     */
179    OpenPIC_Processor Processor[OPENPIC_MAX_PROCESSORS];
180};
181
182extern volatile struct OpenPIC *OpenPIC;
183
184    /*
185     *  Current Task Priority Register
186     */
187
188#define OPENPIC_CURRENT_TASK_PRIORITY_MASK      0x0000000f
189
190    /*
191     *  Who Am I Register
192     */
193
194#define OPENPIC_WHO_AM_I_ID_MASK                0x0000001f
195
196    /*
197     *  Feature Reporting Register 0
198     */
199
200#define OPENPIC_FEATURE_LAST_SOURCE_MASK        0x07ff0000
201#define OPENPIC_FEATURE_LAST_SOURCE_SHIFT       16
202#define OPENPIC_FEATURE_LAST_PROCESSOR_MASK     0x00001f00
203#define OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT    8
204#define OPENPIC_FEATURE_VERSION_MASK            0x000000ff
205
206    /*
207     *  Global Configuration Register 0
208     */
209
210#define OPENPIC_CONFIG_RESET                    0x80000000
211#define OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE 0x20000000
212#define OPENPIC_CONFIG_BASE_MASK                0x000fffff
213
214    /*
215     *  Vendor Identification Register
216     */
217
218#define OPENPIC_VENDOR_ID_STEPPING_MASK         0x00ff0000
219#define OPENPIC_VENDOR_ID_STEPPING_SHIFT        16
220#define OPENPIC_VENDOR_ID_DEVICE_ID_MASK        0x0000ff00
221#define OPENPIC_VENDOR_ID_DEVICE_ID_SHIFT       8
222#define OPENPIC_VENDOR_ID_VENDOR_ID_MASK        0x000000ff
223
224    /*
225     *  Vector/Priority Registers
226     */
227
228#define OPENPIC_MASK                            0x80000000
229#define OPENPIC_ACTIVITY                        0x40000000      /* Read Only */
230#define OPENPIC_PRIORITY_MASK                   0x000f0000
231#define OPENPIC_PRIORITY_SHIFT                  16
232#define OPENPIC_VECTOR_MASK                     0x000000ff
233
234    /*
235     *  Interrupt Source Registers
236     */
237
238#define OPENPIC_SENSE_POLARITY                  0x00800000      /* Undoc'd */
239#define OPENPIC_SENSE_LEVEL                     0x00400000
240
241    /*
242     *  Timer Registers
243     */
244
245#define OPENPIC_COUNT_MASK                      0x7fffffff
246#define OPENPIC_TIMER_TOGGLE                    0x80000000
247#define OPENPIC_TIMER_COUNT_INHIBIT             0x80000000
248
249    /*
250     *  Aliases to make life simpler
251     */
252
253/* Per Processor Registers */
254#define IPI_Dispatch(i)                 _IPI_Dispatch[i].Reg
255#define Current_Task_Priority           _Current_Task_Priority.Reg
256#define Interrupt_Acknowledge           _Interrupt_Acknowledge.Reg
257#define EOI                             _EOI.Reg
258
259/* Global Registers */
260#define Feature_Reporting0              _Feature_Reporting0.Reg
261#define Feature_Reporting1              _Feature_Reporting1.Reg
262#define Global_Configuration0           _Global_Configuration0.Reg
263#define Global_Configuration1           _Global_Configuration1.Reg
264#define Vendor_Specific(i)              _Vendor_Specific[i].Reg
265#define Vendor_Identification           _Vendor_Identification.Reg
266#define Processor_Initialization        _Processor_Initialization.Reg
267#define IPI_Vector_Priority(i)          _IPI_Vector_Priority[i].Reg
268#define Spurious_Vector                 _Spurious_Vector.Reg
269#define Timer_Frequency                 _Timer_Frequency.Reg
270
271/* Timer Registers */
272#define Current_Count                   _Current_Count.Reg
273#define Base_Count                      _Base_Count.Reg
274#define Vector_Priority                 _Vector_Priority.Reg
275#define Destination                     _Destination.Reg
276
277/* Interrupt Source Registers */
278#define Vector_Priority                 _Vector_Priority.Reg
279#define Destination                     _Destination.Reg
280
281    /*
282     *  Vendor and Device IDs
283     */
284
285#define OPENPIC_VENDOR_ID_APPLE         0x14
286#define OPENPIC_DEVICE_ID_APPLE_HYDRA   0x46
287
288    /*
289     *  OpenPIC Operations
290     */
291
292/*
293 * Handle EPIC differences. Unfortunately, I don't know of an easy
294 * way to tell an EPIC from a normal PIC at run-time. Therefore,
295 * the BSP must enable a few quirks if it knows that an EPIC is being
296 * used:
297 *  - If the BSP uses the serial interrupt mode / 'multiplexer' then
298 *    EOI must be delayed by at least 16 SRAM_CLK cycles to avoid
299 *    spurious interrupts.
300 *    It is the BSP's responsibility to set up an appropriate delay
301 *    (in timebase-clock cycles) at init time using
302 *    'openpic_set_eoi_delay()'. This is ONLY necessary when using
303 *    an EPIC in serial mode.
304 *  - The EPIC sources start at an offset of 16 in the register
305 *    map, i.e., on an EPIC you'd say Sources[ x + 16 ] where
306 *    on a PIC you would say Sources[ x ].
307 *    Again, the BSP can set an offset that is used by the
308 *    calls dealing with 'Interrupt Sources'
309 *      openpic_enable_irq()
310 *      openpic_disable_irq()
311 *      openpic_initirq()
312 *      openpic_mapirq()
313 *      openpic_set_sense()
314 *      openpic_get_source_priority()
315 *      openpic_set_source_priority()
316 *    the desired source offset parameter is passed to openpic_init().
317 *
318 * The routine 'openpic_set_eoi_delay()' returns the previous/old
319 * value of the delay parameter.
320 */
321extern unsigned openpic_set_eoi_delay(unsigned tb_cycles);
322
323
324/* Global Operations */
325
326/* num_sources: number of sources to use; if zero this value
327 * is read from the device, if nonzero the value read from
328 * the device is overridden.
329 * 'polarities' and 'senses' are arrays defining the desired
330 * polarities (active hi [nonzero]/lo [zero]) and
331 * senses (level [nonzero]/edge [zero]).
332 * Either of the two array pointers may be NULL resulting
333 * in the driver choosing default values of: 'active low'
334 * and 'level sensitive', respectively.
335 * NOTE: if you do pass arrays then their size must either
336 *       match the number of sources read from the device or
337 *       that value must be overridden by specifying
338 *       a non-zero 'num_sources' parameter.
339 *
340 * Nonzero 'epic_freq' activates the EOI delay if the EPIC is
341 * configured in serial mode (driver assumes firmware performs initial
342 * EPIC setup). The BSP must pass the clock frequency of the EPIC
343 * serial interface here.
344 */
345extern void openpic_init(int main_pic, unsigned char *polarities, unsigned char *senses, int num_sources, int source_offset, unsigned long epic_freq);
346
347extern void openpic_reset(void);
348extern void openpic_enable_8259_pass_through(void);
349extern void openpic_disable_8259_pass_through(void);
350extern unsigned int openpic_irq(unsigned int cpu);
351extern void openpic_eoi(unsigned int cpu);
352extern unsigned int openpic_get_priority(unsigned int cpu);
353extern void openpic_set_priority(unsigned int cpu, unsigned int pri);
354extern unsigned int openpic_get_spurious(void);
355extern void openpic_set_spurious(unsigned int vector);
356extern void openpic_init_processor(unsigned int cpumask);
357
358/* Interprocessor Interrupts */
359extern void openpic_initipi(unsigned int ipi, unsigned int pri, unsigned int vector);
360extern void openpic_cause_IPI(unsigned int cpu, unsigned int ipi, unsigned int cpumask);
361
362/* Timer Interrupts */
363extern void openpic_inittimer(unsigned int timer, unsigned int pri, unsigned int vector);
364extern void openpic_settimer(unsigned int timer, unsigned int base_count, int irq_enable);
365extern unsigned int openpic_gettimer(unsigned int timer);
366extern void openpic_maptimer(unsigned int timer, unsigned int cpumask);
367
368/* Interrupt Sources */
369extern void openpic_enable_irq(unsigned int irq);
370extern int  openpic_disable_irq(unsigned int irq);
371extern void openpic_initirq(unsigned int irq, unsigned int pri, unsigned int vector, int polarity,
372                            int is_level);
373extern void openpic_mapirq(unsigned int irq, unsigned int cpumask);
374extern void openpic_set_sense(unsigned int irq, int sense);
375extern unsigned int openpic_get_source_priority(unsigned int irq);
376extern void openpic_set_source_priority(unsigned int irq, unsigned int pri);
377
378#endif /* RTEMS_OPENPIC_H */
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