source: rtems/c/src/lib/libbsp/powerpc/shared/openpic/openpic.h @ acc25ee

4.104.114.84.95
Last change on this file since acc25ee was acc25ee, checked in by Joel Sherrill <joel.sherrill@…>, on Dec 2, 1999 at 2:31:19 PM

Merged of mcp750 and mvme2307 BSP by Eric Valette <valette@…>.
As part of this effort, the mpc750 libcpu code is now shared with the
ppc6xx.

  • Property mode set to 100644
File size: 8.9 KB
Line 
1/*
2 *  openpic.h -- OpenPIC definitions
3 *
4 *  Copyright (C) 1997 Geert Uytterhoeven
5 *
6 *  This file is based on the following documentation:
7 *
8 *      The Open Programmable Interrupt Controller (PIC)
9 *      Register Interface Specification Revision 1.2
10 *
11 *      Issue Date: October 1995
12 *
13 *      Issued jointly by Advanced Micro Devices and Cyrix Corporation
14 *
15 *      AMD is a registered trademark of Advanced Micro Devices, Inc.
16 *      Copyright (C) 1995, Advanced Micro Devices, Inc. and Cyrix, Inc.
17 *      All Rights Reserved.
18 *
19 *  To receive a copy of this documentation, send an email to openpic@amd.com.
20 *
21 *  This file is subject to the terms and conditions of the GNU General Public
22 *  License.  See the file COPYING in the main directory of this archive
23 *  for more details.
24 *
25 *  Modified to compile in RTEMS development environment
26 *  by Eric Valette
27 *
28 *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
29 *
30 *  The license and distribution terms for this file may be
31 *  found in found in the file LICENSE in this distribution or at
32 *  http://www.OARcorp.com/rtems/license.html.
33 *
34 * $Id$
35 */
36
37#ifndef _RTEMS_OPENPIC_H
38#define _RTEMS_OPENPIC_H
39
40
41    /*
42     *  OpenPIC supports up to 2048 interrupt sources and up to 32 processors
43     */
44
45#define OPENPIC_MAX_SOURCES     2048
46#define OPENPIC_MAX_PROCESSORS  32
47
48#define OPENPIC_NUM_TIMERS      4
49#define OPENPIC_NUM_IPI         4
50#define OPENPIC_NUM_PRI         16
51#define OPENPIC_NUM_VECTORS     256
52
53
54    /*
55     *  Vector numbers
56     */
57
58#define OPENPIC_VEC_SOURCE      0x10    /* and up */
59#define OPENPIC_VEC_TIMER       0x40    /* and up */
60#define OPENPIC_VEC_IPI         0x50    /* and up */
61#define OPENPIC_VEC_SPURIOUS    99
62
63
64    /*
65     *  OpenPIC Registers are 32 bits and aligned on 128 bit boundaries
66     */
67
68typedef struct _OpenPIC_Reg {
69    unsigned int Reg;                                   /* Little endian! */
70    char Pad[0xc];
71} OpenPIC_Reg;
72
73
74    /*
75     *  Per Processor Registers
76     */
77
78typedef struct _OpenPIC_Processor {
79    /*
80     *  Private Shadow Registers (for SLiC backwards compatibility)
81     */
82    unsigned int IPI0_Dispatch_Shadow;                  /* Write Only */
83    char Pad1[0x4];
84    unsigned int IPI0_Vector_Priority_Shadow;           /* Read/Write */
85    char Pad2[0x34];
86    /*
87     *  Interprocessor Interrupt Command Ports
88     */
89    OpenPIC_Reg _IPI_Dispatch[OPENPIC_NUM_IPI]; /* Write Only */
90    /*
91     *  Current Task Priority Register
92     */
93    OpenPIC_Reg _Current_Task_Priority;         /* Read/Write */
94    char Pad3[0x10];
95    /*
96     *  Interrupt Acknowledge Register
97     */
98    OpenPIC_Reg _Interrupt_Acknowledge;         /* Read Only */
99    /*
100     *  End of Interrupt (EOI) Register
101     */
102    OpenPIC_Reg _EOI;                           /* Read/Write */
103    char Pad5[0xf40];
104} OpenPIC_Processor;
105
106
107    /*
108     *  Timer Registers
109     */
110
111typedef struct _OpenPIC_Timer {
112    OpenPIC_Reg _Current_Count;                 /* Read Only */
113    OpenPIC_Reg _Base_Count;                    /* Read/Write */
114    OpenPIC_Reg _Vector_Priority;               /* Read/Write */
115    OpenPIC_Reg _Destination;                   /* Read/Write */
116} OpenPIC_Timer;
117
118
119    /*
120     *  Global Registers
121     */
122
123typedef struct _OpenPIC_Global {
124    /*
125     *  Feature Reporting Registers
126     */
127    OpenPIC_Reg _Feature_Reporting0;            /* Read Only */
128    OpenPIC_Reg _Feature_Reporting1;            /* Future Expansion */
129    /*
130     *  Global Configuration Registers
131     */
132    OpenPIC_Reg _Global_Configuration0;         /* Read/Write */
133    OpenPIC_Reg _Global_Configuration1;         /* Future Expansion */
134    /*
135     *  Vendor Specific Registers
136     */
137    OpenPIC_Reg _Vendor_Specific[4];
138    /*
139     *  Vendor Identification Register
140     */
141    OpenPIC_Reg _Vendor_Identification;         /* Read Only */
142    /*
143     *  Processor Initialization Register
144     */
145    OpenPIC_Reg _Processor_Initialization;      /* Read/Write */
146    /*
147     *  IPI Vector/Priority Registers
148     */
149    OpenPIC_Reg _IPI_Vector_Priority[OPENPIC_NUM_IPI];  /* Read/Write */
150    /*
151     *  Spurious Vector Register
152     */
153    OpenPIC_Reg _Spurious_Vector;               /* Read/Write */
154    /*
155     *  Global Timer Registers
156     */
157    OpenPIC_Reg _Timer_Frequency;               /* Read/Write */
158    OpenPIC_Timer Timer[OPENPIC_NUM_TIMERS];
159    char Pad1[0xee00];
160} OpenPIC_Global;
161
162
163    /*
164     *  Interrupt Source Registers
165     */
166
167typedef struct _OpenPIC_Source {
168    OpenPIC_Reg _Vector_Priority;               /* Read/Write */
169    OpenPIC_Reg _Destination;                   /* Read/Write */
170} OpenPIC_Source;
171
172
173    /*
174     *  OpenPIC Register Map
175     */
176
177struct OpenPIC {
178    char Pad1[0x1000];
179    /*
180     *  Global Registers
181     */
182    OpenPIC_Global Global;
183    /*
184     *  Interrupt Source Configuration Registers
185     */
186    OpenPIC_Source Source[OPENPIC_MAX_SOURCES];
187    /*
188     *  Per Processor Registers
189     */
190    OpenPIC_Processor Processor[OPENPIC_MAX_PROCESSORS];
191};
192
193extern volatile struct OpenPIC *OpenPIC;
194extern unsigned int OpenPIC_NumInitSenses;
195extern unsigned char *OpenPIC_InitSenses;
196
197
198    /*
199     *  Current Task Priority Register
200     */
201
202#define OPENPIC_CURRENT_TASK_PRIORITY_MASK      0x0000000f
203
204    /*
205     *  Who Am I Register
206     */
207
208#define OPENPIC_WHO_AM_I_ID_MASK                0x0000001f
209
210    /*
211     *  Feature Reporting Register 0
212     */
213
214#define OPENPIC_FEATURE_LAST_SOURCE_MASK        0x07ff0000
215#define OPENPIC_FEATURE_LAST_SOURCE_SHIFT       16
216#define OPENPIC_FEATURE_LAST_PROCESSOR_MASK     0x00001f00
217#define OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT    8
218#define OPENPIC_FEATURE_VERSION_MASK            0x000000ff
219
220    /*
221     *  Global Configuration Register 0
222     */
223
224#define OPENPIC_CONFIG_RESET                    0x80000000
225#define OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE 0x20000000
226#define OPENPIC_CONFIG_BASE_MASK                0x000fffff
227
228    /*
229     *  Vendor Identification Register
230     */
231
232#define OPENPIC_VENDOR_ID_STEPPING_MASK         0x00ff0000
233#define OPENPIC_VENDOR_ID_STEPPING_SHIFT        16
234#define OPENPIC_VENDOR_ID_DEVICE_ID_MASK        0x0000ff00
235#define OPENPIC_VENDOR_ID_DEVICE_ID_SHIFT       8
236#define OPENPIC_VENDOR_ID_VENDOR_ID_MASK        0x000000ff
237
238    /*
239     *  Vector/Priority Registers
240     */
241
242#define OPENPIC_MASK                            0x80000000
243#define OPENPIC_ACTIVITY                        0x40000000      /* Read Only */
244#define OPENPIC_PRIORITY_MASK                   0x000f0000
245#define OPENPIC_PRIORITY_SHIFT                  16
246#define OPENPIC_VECTOR_MASK                     0x000000ff
247
248
249    /*
250     *  Interrupt Source Registers
251     */
252
253#define OPENPIC_SENSE_POLARITY                  0x00800000      /* Undoc'd */
254#define OPENPIC_SENSE_LEVEL                     0x00400000
255
256
257    /*
258     *  Timer Registers
259     */
260
261#define OPENPIC_COUNT_MASK                      0x7fffffff
262#define OPENPIC_TIMER_TOGGLE                    0x80000000
263#define OPENPIC_TIMER_COUNT_INHIBIT             0x80000000
264
265
266    /*
267     *  Aliases to make life simpler
268     */
269
270/* Per Processor Registers */
271#define IPI_Dispatch(i)                 _IPI_Dispatch[i].Reg
272#define Current_Task_Priority           _Current_Task_Priority.Reg
273#define Interrupt_Acknowledge           _Interrupt_Acknowledge.Reg
274#define EOI                             _EOI.Reg
275
276/* Global Registers */
277#define Feature_Reporting0              _Feature_Reporting0.Reg
278#define Feature_Reporting1              _Feature_Reporting1.Reg
279#define Global_Configuration0           _Global_Configuration0.Reg
280#define Global_Configuration1           _Global_Configuration1.Reg
281#define Vendor_Specific(i)              _Vendor_Specific[i].Reg
282#define Vendor_Identification           _Vendor_Identification.Reg
283#define Processor_Initialization        _Processor_Initialization.Reg
284#define IPI_Vector_Priority(i)          _IPI_Vector_Priority[i].Reg
285#define Spurious_Vector                 _Spurious_Vector.Reg
286#define Timer_Frequency                 _Timer_Frequency.Reg
287
288/* Timer Registers */
289#define Current_Count                   _Current_Count.Reg
290#define Base_Count                      _Base_Count.Reg
291#define Vector_Priority                 _Vector_Priority.Reg
292#define Destination                     _Destination.Reg
293
294/* Interrupt Source Registers */
295#define Vector_Priority                 _Vector_Priority.Reg
296#define Destination                     _Destination.Reg
297
298
299    /*
300     *  Vendor and Device IDs
301     */
302
303#define OPENPIC_VENDOR_ID_APPLE         0x14
304#define OPENPIC_DEVICE_ID_APPLE_HYDRA   0x46
305
306
307    /*
308     *  OpenPIC Operations
309     */
310
311/* Global Operations */
312extern void openpic_init(int);
313extern void openpic_reset(void);
314extern void openpic_enable_8259_pass_through(void);
315extern void openpic_disable_8259_pass_through(void);
316extern unsigned int openpic_irq(unsigned int cpu);
317extern void openpic_eoi(unsigned int cpu);
318extern unsigned int openpic_get_priority(unsigned int cpu);
319extern void openpic_set_priority(unsigned int cpu, unsigned int pri);
320extern unsigned int openpic_get_spurious(void);
321extern void openpic_set_spurious(unsigned int vector);
322extern void openpic_init_processor(unsigned int cpumask);
323
324/* Interprocessor Interrupts */
325extern void openpic_initipi(unsigned int ipi, unsigned int pri, unsigned int vector);
326extern void openpic_cause_IPI(unsigned int cpu, unsigned int ipi, unsigned int cpumask);
327
328/* Timer Interrupts */
329extern void openpic_inittimer(unsigned int timer, unsigned int pri, unsigned int vector);
330extern void openpic_maptimer(unsigned int timer, unsigned int cpumask);
331
332/* Interrupt Sources */
333extern void openpic_enable_irq(unsigned int irq);
334extern void openpic_disable_irq(unsigned int irq);
335extern void openpic_initirq(unsigned int irq, unsigned int pri, unsigned int vector, int polarity,
336                            int is_level);
337extern void openpic_mapirq(unsigned int irq, unsigned int cpumask);
338extern void openpic_set_sense(unsigned int irq, int sense);
339
340#endif /* RTEMS_OPENPIC_H */
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