1 | /* |
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2 | * openpic.h -- OpenPIC definitions |
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3 | * |
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4 | * Copyright (C) 1997 Geert Uytterhoeven |
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5 | * |
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6 | * This file is based on the following documentation: |
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7 | * |
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8 | * The Open Programmable Interrupt Controller (PIC) |
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9 | * Register Interface Specification Revision 1.2 |
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10 | * |
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11 | * Issue Date: October 1995 |
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12 | * |
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13 | * Issued jointly by Advanced Micro Devices and Cyrix Corporation |
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14 | * |
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15 | * AMD is a registered trademark of Advanced Micro Devices, Inc. |
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16 | * Copyright (C) 1995, Advanced Micro Devices, Inc. and Cyrix, Inc. |
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17 | * All Rights Reserved. |
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18 | * |
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19 | * To receive a copy of this documentation, send an email to openpic@amd.com. |
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20 | * |
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21 | * This file is subject to the terms and conditions of the GNU General Public |
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22 | * License. See the file COPYING in the main directory of this archive |
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23 | * for more details. |
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24 | * |
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25 | * Modified to compile in RTEMS development environment |
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26 | * by Eric Valette |
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27 | * |
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28 | * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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29 | * |
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30 | * The license and distribution terms for this file may be |
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31 | * found in found in the file LICENSE in this distribution or at |
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32 | * http://www.OARcorp.com/rtems/license.html. |
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33 | * |
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34 | * $Id$ |
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35 | */ |
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36 | |
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37 | #ifndef _RTEMS_OPENPIC_H |
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38 | #define _RTEMS_OPENPIC_H |
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39 | |
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40 | |
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41 | /* |
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42 | * OpenPIC supports up to 2048 interrupt sources and up to 32 processors |
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43 | */ |
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44 | |
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45 | #define OPENPIC_MAX_SOURCES 2048 |
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46 | #define OPENPIC_MAX_PROCESSORS 32 |
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47 | |
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48 | #define OPENPIC_NUM_TIMERS 4 |
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49 | #define OPENPIC_NUM_IPI 4 |
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50 | #define OPENPIC_NUM_PRI 16 |
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51 | #define OPENPIC_NUM_VECTORS 256 |
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52 | |
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53 | |
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54 | /* |
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55 | * Vector numbers |
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56 | */ |
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57 | |
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58 | #define OPENPIC_VEC_SOURCE 0x10 /* and up */ |
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59 | #define OPENPIC_VEC_TIMER 0x40 /* and up */ |
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60 | #define OPENPIC_VEC_IPI 0x50 /* and up */ |
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61 | #define OPENPIC_VEC_SPURIOUS 99 |
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62 | |
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63 | |
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64 | /* |
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65 | * OpenPIC Registers are 32 bits and aligned on 128 bit boundaries |
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66 | */ |
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67 | |
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68 | typedef struct _OpenPIC_Reg { |
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69 | unsigned int Reg; /* Little endian! */ |
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70 | char Pad[0xc]; |
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71 | } OpenPIC_Reg; |
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72 | |
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73 | |
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74 | /* |
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75 | * Per Processor Registers |
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76 | */ |
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77 | |
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78 | typedef struct _OpenPIC_Processor { |
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79 | /* |
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80 | * Private Shadow Registers (for SLiC backwards compatibility) |
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81 | */ |
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82 | unsigned int IPI0_Dispatch_Shadow; /* Write Only */ |
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83 | char Pad1[0x4]; |
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84 | unsigned int IPI0_Vector_Priority_Shadow; /* Read/Write */ |
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85 | char Pad2[0x34]; |
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86 | /* |
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87 | * Interprocessor Interrupt Command Ports |
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88 | */ |
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89 | OpenPIC_Reg _IPI_Dispatch[OPENPIC_NUM_IPI]; /* Write Only */ |
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90 | /* |
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91 | * Current Task Priority Register |
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92 | */ |
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93 | OpenPIC_Reg _Current_Task_Priority; /* Read/Write */ |
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94 | char Pad3[0x10]; |
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95 | /* |
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96 | * Interrupt Acknowledge Register |
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97 | */ |
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98 | OpenPIC_Reg _Interrupt_Acknowledge; /* Read Only */ |
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99 | /* |
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100 | * End of Interrupt (EOI) Register |
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101 | */ |
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102 | OpenPIC_Reg _EOI; /* Read/Write */ |
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103 | char Pad5[0xf40]; |
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104 | } OpenPIC_Processor; |
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105 | |
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106 | |
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107 | /* |
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108 | * Timer Registers |
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109 | */ |
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110 | |
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111 | typedef struct _OpenPIC_Timer { |
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112 | OpenPIC_Reg _Current_Count; /* Read Only */ |
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113 | OpenPIC_Reg _Base_Count; /* Read/Write */ |
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114 | OpenPIC_Reg _Vector_Priority; /* Read/Write */ |
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115 | OpenPIC_Reg _Destination; /* Read/Write */ |
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116 | } OpenPIC_Timer; |
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117 | |
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118 | |
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119 | /* |
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120 | * Global Registers |
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121 | */ |
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122 | |
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123 | typedef struct _OpenPIC_Global { |
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124 | /* |
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125 | * Feature Reporting Registers |
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126 | */ |
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127 | OpenPIC_Reg _Feature_Reporting0; /* Read Only */ |
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128 | OpenPIC_Reg _Feature_Reporting1; /* Future Expansion */ |
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129 | /* |
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130 | * Global Configuration Registers |
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131 | */ |
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132 | OpenPIC_Reg _Global_Configuration0; /* Read/Write */ |
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133 | OpenPIC_Reg _Global_Configuration1; /* Future Expansion */ |
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134 | /* |
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135 | * Vendor Specific Registers |
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136 | */ |
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137 | OpenPIC_Reg _Vendor_Specific[4]; |
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138 | /* |
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139 | * Vendor Identification Register |
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140 | */ |
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141 | OpenPIC_Reg _Vendor_Identification; /* Read Only */ |
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142 | /* |
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143 | * Processor Initialization Register |
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144 | */ |
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145 | OpenPIC_Reg _Processor_Initialization; /* Read/Write */ |
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146 | /* |
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147 | * IPI Vector/Priority Registers |
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148 | */ |
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149 | OpenPIC_Reg _IPI_Vector_Priority[OPENPIC_NUM_IPI]; /* Read/Write */ |
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150 | /* |
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151 | * Spurious Vector Register |
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152 | */ |
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153 | OpenPIC_Reg _Spurious_Vector; /* Read/Write */ |
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154 | /* |
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155 | * Global Timer Registers |
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156 | */ |
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157 | OpenPIC_Reg _Timer_Frequency; /* Read/Write */ |
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158 | OpenPIC_Timer Timer[OPENPIC_NUM_TIMERS]; |
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159 | char Pad1[0xee00]; |
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160 | } OpenPIC_Global; |
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161 | |
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162 | |
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163 | /* |
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164 | * Interrupt Source Registers |
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165 | */ |
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166 | |
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167 | typedef struct _OpenPIC_Source { |
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168 | OpenPIC_Reg _Vector_Priority; /* Read/Write */ |
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169 | OpenPIC_Reg _Destination; /* Read/Write */ |
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170 | } OpenPIC_Source; |
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171 | |
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172 | |
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173 | /* |
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174 | * OpenPIC Register Map |
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175 | */ |
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176 | |
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177 | struct OpenPIC { |
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178 | char Pad1[0x1000]; |
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179 | /* |
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180 | * Global Registers |
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181 | */ |
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182 | OpenPIC_Global Global; |
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183 | /* |
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184 | * Interrupt Source Configuration Registers |
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185 | */ |
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186 | OpenPIC_Source Source[OPENPIC_MAX_SOURCES]; |
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187 | /* |
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188 | * Per Processor Registers |
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189 | */ |
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190 | OpenPIC_Processor Processor[OPENPIC_MAX_PROCESSORS]; |
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191 | }; |
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192 | |
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193 | extern volatile struct OpenPIC *OpenPIC; |
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194 | |
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195 | |
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196 | /* |
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197 | * Current Task Priority Register |
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198 | */ |
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199 | |
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200 | #define OPENPIC_CURRENT_TASK_PRIORITY_MASK 0x0000000f |
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201 | |
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202 | /* |
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203 | * Who Am I Register |
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204 | */ |
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205 | |
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206 | #define OPENPIC_WHO_AM_I_ID_MASK 0x0000001f |
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207 | |
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208 | /* |
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209 | * Feature Reporting Register 0 |
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210 | */ |
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211 | |
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212 | #define OPENPIC_FEATURE_LAST_SOURCE_MASK 0x07ff0000 |
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213 | #define OPENPIC_FEATURE_LAST_SOURCE_SHIFT 16 |
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214 | #define OPENPIC_FEATURE_LAST_PROCESSOR_MASK 0x00001f00 |
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215 | #define OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT 8 |
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216 | #define OPENPIC_FEATURE_VERSION_MASK 0x000000ff |
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217 | |
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218 | /* |
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219 | * Global Configuration Register 0 |
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220 | */ |
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221 | |
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222 | #define OPENPIC_CONFIG_RESET 0x80000000 |
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223 | #define OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE 0x20000000 |
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224 | #define OPENPIC_CONFIG_BASE_MASK 0x000fffff |
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225 | |
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226 | /* |
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227 | * Vendor Identification Register |
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228 | */ |
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229 | |
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230 | #define OPENPIC_VENDOR_ID_STEPPING_MASK 0x00ff0000 |
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231 | #define OPENPIC_VENDOR_ID_STEPPING_SHIFT 16 |
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232 | #define OPENPIC_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00 |
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233 | #define OPENPIC_VENDOR_ID_DEVICE_ID_SHIFT 8 |
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234 | #define OPENPIC_VENDOR_ID_VENDOR_ID_MASK 0x000000ff |
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235 | |
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236 | /* |
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237 | * Vector/Priority Registers |
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238 | */ |
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239 | |
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240 | #define OPENPIC_MASK 0x80000000 |
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241 | #define OPENPIC_ACTIVITY 0x40000000 /* Read Only */ |
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242 | #define OPENPIC_PRIORITY_MASK 0x000f0000 |
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243 | #define OPENPIC_PRIORITY_SHIFT 16 |
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244 | #define OPENPIC_VECTOR_MASK 0x000000ff |
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245 | |
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246 | |
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247 | /* |
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248 | * Interrupt Source Registers |
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249 | */ |
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250 | |
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251 | #define OPENPIC_SENSE_POLARITY 0x00800000 /* Undoc'd */ |
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252 | #define OPENPIC_SENSE_LEVEL 0x00400000 |
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253 | |
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254 | |
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255 | /* |
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256 | * Timer Registers |
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257 | */ |
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258 | |
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259 | #define OPENPIC_COUNT_MASK 0x7fffffff |
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260 | #define OPENPIC_TIMER_TOGGLE 0x80000000 |
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261 | #define OPENPIC_TIMER_COUNT_INHIBIT 0x80000000 |
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262 | |
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263 | |
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264 | /* |
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265 | * Aliases to make life simpler |
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266 | */ |
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267 | |
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268 | /* Per Processor Registers */ |
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269 | #define IPI_Dispatch(i) _IPI_Dispatch[i].Reg |
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270 | #define Current_Task_Priority _Current_Task_Priority.Reg |
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271 | #define Interrupt_Acknowledge _Interrupt_Acknowledge.Reg |
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272 | #define EOI _EOI.Reg |
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273 | |
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274 | /* Global Registers */ |
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275 | #define Feature_Reporting0 _Feature_Reporting0.Reg |
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276 | #define Feature_Reporting1 _Feature_Reporting1.Reg |
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277 | #define Global_Configuration0 _Global_Configuration0.Reg |
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278 | #define Global_Configuration1 _Global_Configuration1.Reg |
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279 | #define Vendor_Specific(i) _Vendor_Specific[i].Reg |
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280 | #define Vendor_Identification _Vendor_Identification.Reg |
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281 | #define Processor_Initialization _Processor_Initialization.Reg |
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282 | #define IPI_Vector_Priority(i) _IPI_Vector_Priority[i].Reg |
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283 | #define Spurious_Vector _Spurious_Vector.Reg |
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284 | #define Timer_Frequency _Timer_Frequency.Reg |
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285 | |
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286 | /* Timer Registers */ |
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287 | #define Current_Count _Current_Count.Reg |
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288 | #define Base_Count _Base_Count.Reg |
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289 | #define Vector_Priority _Vector_Priority.Reg |
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290 | #define Destination _Destination.Reg |
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291 | |
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292 | /* Interrupt Source Registers */ |
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293 | #define Vector_Priority _Vector_Priority.Reg |
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294 | #define Destination _Destination.Reg |
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295 | |
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296 | |
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297 | /* |
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298 | * Vendor and Device IDs |
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299 | */ |
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300 | |
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301 | #define OPENPIC_VENDOR_ID_APPLE 0x14 |
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302 | #define OPENPIC_DEVICE_ID_APPLE_HYDRA 0x46 |
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303 | |
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304 | |
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305 | /* |
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306 | * OpenPIC Operations |
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307 | */ |
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308 | |
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309 | /* Global Operations */ |
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310 | extern void openpic_init(int,unsigned char *, unsigned char *); |
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311 | extern void openpic_reset(void); |
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312 | extern void openpic_enable_8259_pass_through(void); |
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313 | extern void openpic_disable_8259_pass_through(void); |
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314 | extern unsigned int openpic_irq(unsigned int cpu); |
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315 | extern void openpic_eoi(unsigned int cpu); |
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316 | extern unsigned int openpic_get_priority(unsigned int cpu); |
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317 | extern void openpic_set_priority(unsigned int cpu, unsigned int pri); |
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318 | extern unsigned int openpic_get_spurious(void); |
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319 | extern void openpic_set_spurious(unsigned int vector); |
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320 | extern void openpic_init_processor(unsigned int cpumask); |
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321 | |
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322 | /* Interprocessor Interrupts */ |
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323 | extern void openpic_initipi(unsigned int ipi, unsigned int pri, unsigned int vector); |
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324 | extern void openpic_cause_IPI(unsigned int cpu, unsigned int ipi, unsigned int cpumask); |
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325 | |
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326 | /* Timer Interrupts */ |
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327 | extern void openpic_inittimer(unsigned int timer, unsigned int pri, unsigned int vector); |
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328 | extern void openpic_maptimer(unsigned int timer, unsigned int cpumask); |
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329 | |
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330 | /* Interrupt Sources */ |
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331 | extern void openpic_enable_irq(unsigned int irq); |
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332 | extern void openpic_disable_irq(unsigned int irq); |
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333 | extern void openpic_initirq(unsigned int irq, unsigned int pri, unsigned int vector, int polarity, |
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334 | int is_level); |
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335 | extern void openpic_mapirq(unsigned int irq, unsigned int cpumask); |
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336 | extern void openpic_set_sense(unsigned int irq, int sense); |
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337 | extern unsigned int openpic_get_source_priority(unsigned int irq); |
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338 | extern void openpic_set_source_priority(unsigned int irq, unsigned int pri); |
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339 | |
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340 | #endif /* RTEMS_OPENPIC_H */ |
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