1 | /* |
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2 | * openpic.c -- OpenPIC Interrupt Handling |
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3 | * |
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4 | * Copyright (C) 1997 Geert Uytterhoeven |
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5 | * |
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6 | * Modified to compile in RTEMS development environment |
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7 | * by Eric Valette |
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8 | * |
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9 | * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in found in the file LICENSE in this distribution or at |
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13 | * http://www.OARcorp.com/rtems/license.html. |
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14 | * |
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15 | * $Id$ |
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16 | */ |
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17 | |
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18 | /* |
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19 | * Note: Interprocessor Interrupt (IPI) and Timer support is incomplete |
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20 | */ |
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21 | |
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22 | #include <rtems/bspIo.h> |
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23 | #include <bsp/openpic.h> |
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24 | #include <bsp/pci.h> |
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25 | #include <bsp/consoleIo.h> |
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26 | #include <libcpu/io.h> |
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27 | #include <libcpu/byteorder.h> |
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28 | #include <bsp.h> |
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29 | |
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30 | #define NULL 0 |
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31 | #define REGISTER_DEBUG |
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32 | #undef REGISTER_DEBUG |
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33 | |
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34 | |
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35 | volatile struct OpenPIC *OpenPIC = NULL; |
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36 | unsigned int OpenPIC_NumInitSenses = 0; |
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37 | unsigned char *OpenPIC_InitSenses = NULL; |
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38 | |
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39 | static unsigned int NumProcessors; |
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40 | static unsigned int NumSources; |
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41 | |
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42 | |
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43 | /* |
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44 | * Accesses to the current processor's registers |
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45 | */ |
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46 | |
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47 | #define THIS_CPU Processor[cpu] |
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48 | #define CHECK_THIS_CPU check_arg_cpu(cpu) |
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49 | |
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50 | |
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51 | /* |
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52 | * Sanity checks |
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53 | */ |
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54 | |
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55 | #if 1 |
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56 | #define check_arg_ipi(ipi) \ |
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57 | if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \ |
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58 | printk("openpic.c:%d: illegal ipi %d\n", __LINE__, ipi); |
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59 | #define check_arg_timer(timer) \ |
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60 | if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \ |
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61 | printk("openpic.c:%d: illegal timer %d\n", __LINE__, timer); |
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62 | #define check_arg_vec(vec) \ |
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63 | if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \ |
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64 | printk("openpic.c:%d: illegal vector %d\n", __LINE__, vec); |
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65 | #define check_arg_pri(pri) \ |
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66 | if (pri < 0 || pri >= OPENPIC_NUM_PRI) \ |
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67 | printk("openpic.c:%d: illegal priority %d\n", __LINE__, pri); |
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68 | #define check_arg_irq(irq) \ |
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69 | if (irq < 0 || irq >= NumSources) \ |
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70 | printk("openpic.c:%d: illegal irq %d from %p,[%p],[[%p]]\n", \ |
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71 | __LINE__, irq, __builtin_return_address(0), \ |
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72 | __builtin_return_address(1), __builtin_return_address(2) \ |
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73 | ); |
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74 | #define check_arg_cpu(cpu) \ |
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75 | if (cpu < 0 || cpu >= NumProcessors) \ |
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76 | printk("openpic.c:%d: illegal cpu %d\n", __LINE__, cpu); |
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77 | #else |
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78 | #define check_arg_ipi(ipi) do {} while (0) |
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79 | #define check_arg_timer(timer) do {} while (0) |
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80 | #define check_arg_vec(vec) do {} while (0) |
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81 | #define check_arg_pri(pri) do {} while (0) |
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82 | #define check_arg_irq(irq) do {} while (0) |
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83 | #define check_arg_cpu(cpu) do {} while (0) |
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84 | #endif |
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85 | |
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86 | |
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87 | |
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88 | /* |
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89 | * I/O functions |
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90 | */ |
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91 | |
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92 | static inline unsigned int openpic_read(volatile unsigned int *addr) |
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93 | { |
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94 | unsigned int val; |
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95 | |
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96 | val = ld_le32(addr); |
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97 | #ifdef REGISTER_DEBUG |
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98 | printk("openpic_read(0x%08x) = 0x%08x\n", (unsigned int)addr, val); |
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99 | #endif |
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100 | return val; |
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101 | } |
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102 | |
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103 | static inline void openpic_write(volatile unsigned int *addr, unsigned int val) |
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104 | { |
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105 | #ifdef REGISTER_DEBUG |
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106 | printk("openpic_write(0x%08x, 0x%08x)\n", (unsigned int)addr, val); |
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107 | #endif |
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108 | out_le32(addr, val); |
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109 | } |
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110 | |
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111 | |
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112 | static inline unsigned int openpic_readfield(volatile unsigned int *addr, unsigned int mask) |
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113 | { |
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114 | unsigned int val = openpic_read(addr); |
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115 | return val & mask; |
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116 | } |
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117 | |
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118 | inline void openpic_writefield(volatile unsigned int *addr, unsigned int mask, |
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119 | unsigned int field) |
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120 | { |
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121 | unsigned int val = openpic_read(addr); |
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122 | openpic_write(addr, (val & ~mask) | (field & mask)); |
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123 | } |
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124 | |
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125 | static inline void openpic_clearfield(volatile unsigned int *addr, unsigned int mask) |
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126 | { |
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127 | openpic_writefield(addr, mask, 0); |
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128 | } |
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129 | |
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130 | static inline void openpic_setfield(volatile unsigned int *addr, unsigned int mask) |
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131 | { |
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132 | openpic_writefield(addr, mask, mask); |
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133 | } |
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134 | |
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135 | |
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136 | /* |
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137 | * Update a Vector/Priority register in a safe manner. The interrupt will |
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138 | * be disabled. |
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139 | */ |
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140 | |
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141 | static void openpic_safe_writefield(volatile unsigned int *addr, unsigned int mask, |
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142 | unsigned int field) |
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143 | { |
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144 | openpic_setfield(addr, OPENPIC_MASK); |
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145 | /* wait until it's not in use */ |
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146 | while (openpic_read(addr) & OPENPIC_ACTIVITY); |
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147 | openpic_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK); |
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148 | } |
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149 | |
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150 | |
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151 | /* -------- Global Operations ---------------------------------------------- */ |
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152 | |
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153 | |
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154 | /* |
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155 | * Initialize the OpenPIC |
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156 | * |
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157 | * Add some kludge to use the Motorola Raven OpenPIC which does not |
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158 | * report vendor and device id, and gets the wrong number of interrupts. |
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159 | * (Motorola did a great job on that one!) |
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160 | */ |
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161 | |
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162 | void openpic_init(int main_pic) |
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163 | { |
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164 | unsigned int t, i; |
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165 | unsigned int vendorid, devid, stepping, timerfreq; |
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166 | const char *version, *vendor, *device; |
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167 | |
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168 | if (!OpenPIC) |
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169 | BSP_panic("No OpenPIC found"); |
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170 | |
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171 | t = openpic_read(&OpenPIC->Global.Feature_Reporting0); |
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172 | switch (t & OPENPIC_FEATURE_VERSION_MASK) { |
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173 | case 1: |
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174 | version = "1.0"; |
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175 | break; |
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176 | case 2: |
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177 | version = "1.2"; |
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178 | break; |
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179 | default: |
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180 | version = "?"; |
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181 | break; |
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182 | } |
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183 | NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >> |
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184 | OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1; |
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185 | NumSources = ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >> |
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186 | OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1; |
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187 | t = openpic_read(&OpenPIC->Global.Vendor_Identification); |
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188 | |
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189 | vendorid = t & OPENPIC_VENDOR_ID_VENDOR_ID_MASK; |
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190 | devid = (t & OPENPIC_VENDOR_ID_DEVICE_ID_MASK) >> |
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191 | OPENPIC_VENDOR_ID_DEVICE_ID_SHIFT; |
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192 | stepping = (t & OPENPIC_VENDOR_ID_STEPPING_MASK) >> |
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193 | OPENPIC_VENDOR_ID_STEPPING_SHIFT; |
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194 | |
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195 | /* Kludge for the Raven */ |
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196 | pci_read_config_dword(0, 0, 0, 0, &t); |
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197 | if (t == PCI_VENDOR_ID_MOTOROLA + (PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) { |
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198 | vendor = "Motorola"; |
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199 | device = "Raven"; |
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200 | NumSources += 1; |
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201 | } else { |
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202 | switch (vendorid) { |
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203 | case OPENPIC_VENDOR_ID_APPLE: |
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204 | vendor = "Apple"; |
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205 | break; |
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206 | default: |
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207 | vendor = "Unknown"; |
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208 | break; |
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209 | } |
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210 | switch (devid) { |
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211 | case OPENPIC_DEVICE_ID_APPLE_HYDRA: |
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212 | device = "Hydra"; |
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213 | break; |
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214 | default: |
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215 | device = "Unknown"; |
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216 | break; |
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217 | } |
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218 | } |
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219 | printk("OpenPIC Version %s (%d CPUs and %d IRQ sources) at %p\n", version, |
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220 | NumProcessors, NumSources, OpenPIC); |
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221 | |
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222 | printk("OpenPIC Vendor %d (%s), Device %d (%s), Stepping %d\n", vendorid, |
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223 | vendor, devid, device, stepping); |
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224 | |
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225 | timerfreq = openpic_read(&OpenPIC->Global.Timer_Frequency); |
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226 | printk("OpenPIC timer frequency is "); |
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227 | if (timerfreq) |
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228 | printk("%d Hz\n", timerfreq); |
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229 | else |
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230 | printk("not set\n"); |
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231 | |
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232 | if ( main_pic ) |
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233 | { |
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234 | /* Initialize timer interrupts */ |
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235 | for (i = 0; i < OPENPIC_NUM_TIMERS; i++) { |
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236 | /* Disabled, Priority 0 */ |
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237 | openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i); |
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238 | /* No processor */ |
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239 | openpic_maptimer(i, 0); |
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240 | } |
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241 | |
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242 | /* Initialize IPI interrupts */ |
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243 | for (i = 0; i < OPENPIC_NUM_IPI; i++) { |
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244 | /* Disabled, Priority 0 */ |
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245 | openpic_initipi(i, 0, OPENPIC_VEC_IPI+i); |
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246 | } |
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247 | |
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248 | /* Initialize external interrupts */ |
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249 | /* SIOint (8259 cascade) is special */ |
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250 | openpic_initirq(0, 8, OPENPIC_VEC_SOURCE, 1, 1); |
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251 | /* Processor 0 */ |
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252 | openpic_mapirq(0, 1<<0); |
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253 | for (i = 1; i < NumSources; i++) { |
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254 | /* Enabled, Priority 8 */ |
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255 | openpic_initirq(i, 8, OPENPIC_VEC_SOURCE+i, 0, |
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256 | i < OpenPIC_NumInitSenses ? OpenPIC_InitSenses[i] : 1); |
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257 | /* Processor 0 */ |
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258 | openpic_mapirq(i, 1<<0); |
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259 | } |
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260 | |
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261 | /* Initialize the spurious interrupt */ |
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262 | openpic_set_spurious(OPENPIC_VEC_SPURIOUS); |
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263 | #if 0 |
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264 | if (request_irq(IRQ_8259_CASCADE, no_action, SA_INTERRUPT, |
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265 | "82c59 cascade", NULL)) |
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266 | printk("Unable to get OpenPIC IRQ 0 for cascade\n"); |
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267 | #endif |
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268 | openpic_set_priority(0, 0); |
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269 | openpic_disable_8259_pass_through(); |
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270 | } |
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271 | } |
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272 | |
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273 | |
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274 | /* |
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275 | * Reset the OpenPIC |
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276 | */ |
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277 | |
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278 | void openpic_reset(void) |
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279 | { |
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280 | openpic_setfield(&OpenPIC->Global.Global_Configuration0, |
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281 | OPENPIC_CONFIG_RESET); |
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282 | } |
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283 | |
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284 | |
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285 | /* |
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286 | * Enable/disable 8259 Pass Through Mode |
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287 | */ |
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288 | |
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289 | void openpic_enable_8259_pass_through(void) |
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290 | { |
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291 | openpic_clearfield(&OpenPIC->Global.Global_Configuration0, |
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292 | OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE); |
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293 | } |
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294 | |
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295 | void openpic_disable_8259_pass_through(void) |
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296 | { |
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297 | openpic_setfield(&OpenPIC->Global.Global_Configuration0, |
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298 | OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE); |
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299 | } |
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300 | |
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301 | |
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302 | /* |
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303 | * Find out the current interrupt |
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304 | */ |
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305 | |
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306 | unsigned int openpic_irq(unsigned int cpu) |
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307 | { |
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308 | unsigned int vec; |
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309 | |
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310 | check_arg_cpu(cpu); |
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311 | vec = openpic_readfield(&OpenPIC->THIS_CPU.Interrupt_Acknowledge, |
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312 | OPENPIC_VECTOR_MASK); |
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313 | return vec; |
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314 | } |
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315 | |
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316 | |
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317 | /* |
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318 | * Signal end of interrupt (EOI) processing |
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319 | */ |
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320 | |
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321 | void openpic_eoi(unsigned int cpu) |
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322 | { |
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323 | check_arg_cpu(cpu); |
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324 | openpic_write(&OpenPIC->THIS_CPU.EOI, 0); |
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325 | } |
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326 | |
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327 | |
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328 | /* |
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329 | * Get/set the current task priority |
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330 | */ |
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331 | |
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332 | unsigned int openpic_get_priority(unsigned int cpu) |
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333 | { |
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334 | CHECK_THIS_CPU; |
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335 | return openpic_readfield(&OpenPIC->THIS_CPU.Current_Task_Priority, |
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336 | OPENPIC_CURRENT_TASK_PRIORITY_MASK); |
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337 | } |
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338 | |
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339 | void openpic_set_priority(unsigned int cpu, unsigned int pri) |
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340 | { |
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341 | CHECK_THIS_CPU; |
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342 | check_arg_pri(pri); |
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343 | openpic_writefield(&OpenPIC->THIS_CPU.Current_Task_Priority, |
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344 | OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri); |
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345 | } |
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346 | |
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347 | /* |
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348 | * Get/set the spurious vector |
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349 | */ |
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350 | |
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351 | unsigned int openpic_get_spurious(void) |
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352 | { |
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353 | return openpic_readfield(&OpenPIC->Global.Spurious_Vector, |
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354 | OPENPIC_VECTOR_MASK); |
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355 | } |
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356 | |
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357 | void openpic_set_spurious(unsigned int vec) |
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358 | { |
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359 | check_arg_vec(vec); |
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360 | openpic_writefield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK, |
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361 | vec); |
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362 | } |
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363 | |
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364 | |
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365 | /* |
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366 | * Initialize one or more CPUs |
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367 | */ |
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368 | |
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369 | void openpic_init_processor(unsigned int cpumask) |
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370 | { |
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371 | openpic_write(&OpenPIC->Global.Processor_Initialization, cpumask); |
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372 | } |
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373 | |
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374 | |
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375 | /* -------- Interprocessor Interrupts -------------------------------------- */ |
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376 | |
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377 | |
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378 | /* |
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379 | * Initialize an interprocessor interrupt (and disable it) |
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380 | * |
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381 | * ipi: OpenPIC interprocessor interrupt number |
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382 | * pri: interrupt source priority |
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383 | * vec: the vector it will produce |
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384 | */ |
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385 | |
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386 | void openpic_initipi(unsigned int ipi, unsigned int pri, unsigned int vec) |
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387 | { |
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388 | check_arg_timer(ipi); |
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389 | check_arg_pri(pri); |
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390 | check_arg_vec(vec); |
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391 | openpic_safe_writefield(&OpenPIC->Global.IPI_Vector_Priority(ipi), |
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392 | OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK, |
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393 | (pri << OPENPIC_PRIORITY_SHIFT) | vec); |
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394 | } |
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395 | |
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396 | |
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397 | /* |
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398 | * Send an IPI to one or more CPUs |
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399 | */ |
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400 | |
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401 | void openpic_cause_IPI(unsigned int cpu, unsigned int ipi, unsigned int cpumask) |
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402 | { |
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403 | CHECK_THIS_CPU; |
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404 | check_arg_ipi(ipi); |
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405 | openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi), cpumask); |
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406 | } |
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407 | |
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408 | |
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409 | /* -------- Timer Interrupts ----------------------------------------------- */ |
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410 | |
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411 | |
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412 | /* |
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413 | * Initialize a timer interrupt (and disable it) |
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414 | * |
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415 | * timer: OpenPIC timer number |
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416 | * pri: interrupt source priority |
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417 | * vec: the vector it will produce |
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418 | */ |
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419 | |
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420 | void openpic_inittimer(unsigned int timer, unsigned int pri, unsigned int vec) |
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421 | { |
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422 | check_arg_timer(timer); |
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423 | check_arg_pri(pri); |
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424 | check_arg_vec(vec); |
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425 | openpic_safe_writefield(&OpenPIC->Global.Timer[timer].Vector_Priority, |
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426 | OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK, |
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427 | (pri << OPENPIC_PRIORITY_SHIFT) | vec); |
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428 | } |
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429 | |
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430 | |
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431 | /* |
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432 | * Map a timer interrupt to one or more CPUs |
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433 | */ |
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434 | |
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435 | void openpic_maptimer(unsigned int timer, unsigned int cpumask) |
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436 | { |
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437 | check_arg_timer(timer); |
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438 | openpic_write(&OpenPIC->Global.Timer[timer].Destination, cpumask); |
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439 | } |
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440 | |
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441 | |
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442 | /* -------- Interrupt Sources ---------------------------------------------- */ |
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443 | |
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444 | |
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445 | /* |
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446 | * Enable/disable an interrupt source |
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447 | */ |
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448 | |
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449 | void openpic_enable_irq(unsigned int irq) |
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450 | { |
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451 | check_arg_irq(irq); |
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452 | openpic_clearfield(&OpenPIC->Source[irq].Vector_Priority, OPENPIC_MASK); |
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453 | } |
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454 | |
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455 | void openpic_disable_irq(unsigned int irq) |
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456 | { |
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457 | check_arg_irq(irq); |
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458 | openpic_setfield(&OpenPIC->Source[irq].Vector_Priority, OPENPIC_MASK); |
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459 | } |
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460 | |
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461 | |
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462 | /* |
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463 | * Initialize an interrupt source (and disable it!) |
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464 | * |
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465 | * irq: OpenPIC interrupt number |
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466 | * pri: interrupt source priority |
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467 | * vec: the vector it will produce |
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468 | * pol: polarity (1 for positive, 0 for negative) |
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469 | * sense: 1 for level, 0 for edge |
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470 | */ |
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471 | |
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472 | void openpic_initirq(unsigned int irq, unsigned int pri, unsigned int vec, int pol, int sense) |
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473 | { |
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474 | check_arg_irq(irq); |
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475 | check_arg_pri(pri); |
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476 | check_arg_vec(vec); |
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477 | openpic_safe_writefield(&OpenPIC->Source[irq].Vector_Priority, |
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478 | OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK | |
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479 | OPENPIC_SENSE_POLARITY | OPENPIC_SENSE_LEVEL, |
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480 | (pri << OPENPIC_PRIORITY_SHIFT) | vec | |
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481 | (pol ? OPENPIC_SENSE_POLARITY : 0) | |
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482 | (sense ? OPENPIC_SENSE_LEVEL : 0)); |
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483 | } |
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484 | |
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485 | |
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486 | /* |
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487 | * Map an interrupt source to one or more CPUs |
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488 | */ |
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489 | |
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490 | void openpic_mapirq(unsigned int irq, unsigned int cpumask) |
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491 | { |
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492 | check_arg_irq(irq); |
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493 | openpic_write(&OpenPIC->Source[irq].Destination, cpumask); |
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494 | } |
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495 | |
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496 | |
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497 | /* |
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498 | * Set the sense for an interrupt source (and disable it!) |
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499 | * |
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500 | * sense: 1 for level, 0 for edge |
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501 | */ |
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502 | |
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503 | void openpic_set_sense(unsigned int irq, int sense) |
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504 | { |
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505 | check_arg_irq(irq); |
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506 | openpic_safe_writefield(&OpenPIC->Source[irq].Vector_Priority, |
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507 | OPENPIC_SENSE_LEVEL, |
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508 | (sense ? OPENPIC_SENSE_LEVEL : 0)); |
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509 | } |
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