1 | /* |
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2 | * openpic.c -- OpenPIC Interrupt Handling |
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3 | * |
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4 | * Copyright (C) 1997 Geert Uytterhoeven |
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5 | * |
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6 | * Modified to compile in RTEMS development environment |
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7 | * by Eric Valette |
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8 | * |
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9 | * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in the file LICENSE in this distribution or at |
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13 | * http://www.rtems.org/license/LICENSE. |
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14 | */ |
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15 | |
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16 | /* |
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17 | * Note: Interprocessor Interrupt (IPI) and Timer support is incomplete |
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18 | */ |
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19 | |
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20 | #include <rtems.h> |
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21 | #include <bsp.h> |
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22 | #include <rtems/bspIo.h> |
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23 | #include <bsp/openpic.h> |
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24 | #include <rtems/pci.h> |
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25 | #include <libcpu/io.h> |
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26 | #include <libcpu/byteorder.h> |
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27 | #include <rtems/bspIo.h> |
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28 | #include <inttypes.h> |
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29 | |
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30 | #ifndef NULL |
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31 | #define NULL 0 |
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32 | #endif |
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33 | #define REGISTER_DEBUG |
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34 | #undef REGISTER_DEBUG |
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35 | |
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36 | volatile struct OpenPIC *OpenPIC = NULL; |
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37 | |
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38 | static unsigned int NumProcessors; |
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39 | static unsigned int NumSources; |
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40 | |
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41 | static unsigned int openpic_eoi_delay = 0; |
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42 | static int openpic_src_offst = 0; |
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43 | #define SOURCE(irq) Source[ (irq) + openpic_src_offst ] |
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44 | |
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45 | /* |
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46 | * Accesses to the current processor's registers |
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47 | */ |
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48 | |
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49 | #define THIS_CPU Processor[cpu] |
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50 | #define CHECK_THIS_CPU check_arg_cpu(cpu) |
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51 | |
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52 | /* |
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53 | * Sanity checks |
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54 | */ |
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55 | |
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56 | #if 1 |
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57 | /* This software deliberately uses non-zero values to the method |
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58 | * __builtin_return_address() and we want to avoid the GCC warning. |
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59 | */ |
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60 | #pragma GCC diagnostic push |
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61 | #pragma GCC diagnostic ignored "-Wframe-address" |
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62 | #define check_arg_ipi(ipi) \ |
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63 | if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \ |
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64 | printk("openpic.c:%d: illegal ipi %d\n", __LINE__, ipi); |
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65 | #define check_arg_timer(timer) \ |
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66 | if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \ |
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67 | printk("openpic.c:%d: illegal timer %d\n", __LINE__, timer); |
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68 | #define check_arg_vec(vec) \ |
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69 | if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \ |
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70 | printk("openpic.c:%d: illegal vector %d\n", __LINE__, vec); |
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71 | #define check_arg_pri(pri) \ |
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72 | if (pri < 0 || pri >= OPENPIC_NUM_PRI) \ |
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73 | printk("openpic.c:%d: illegal priority %d\n", __LINE__, pri); |
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74 | #define check_arg_irq(irq) \ |
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75 | if (irq < 0 || irq >= NumSources) \ |
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76 | printk("openpic.c:%d: illegal irq %d from 0x%08" PRIxPTR ",[0x%08" PRIxPTR "],[[0x%08" PRIxPTR "]]\n", \ |
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77 | __LINE__, irq, (uintptr_t) __builtin_return_address(0), \ |
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78 | (uintptr_t) __builtin_return_address(1), (uintptr_t) __builtin_return_address(2) \ |
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79 | ); |
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80 | #define check_arg_cpu(cpu) \ |
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81 | if (cpu < 0 || cpu >= NumProcessors) \ |
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82 | printk("openpic.c:%d: illegal cpu %d\n", __LINE__, cpu); |
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83 | #else |
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84 | #define check_arg_ipi(ipi) do {} while (0) |
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85 | #define check_arg_timer(timer) do {} while (0) |
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86 | #define check_arg_vec(vec) do {} while (0) |
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87 | #define check_arg_pri(pri) do {} while (0) |
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88 | #define check_arg_irq(irq) do {} while (0) |
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89 | #define check_arg_cpu(cpu) do {} while (0) |
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90 | #endif |
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91 | |
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92 | /* |
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93 | * I/O functions |
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94 | */ |
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95 | |
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96 | static inline unsigned int openpic_read(volatile unsigned int *addr) |
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97 | { |
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98 | unsigned int val; |
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99 | |
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100 | #ifdef BSP_OPEN_PIC_BIG_ENDIAN |
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101 | val = in_be32((volatile uint32_t *)addr); |
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102 | #else |
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103 | val = in_le32((volatile uint32_t *)addr); |
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104 | #endif |
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105 | #ifdef REGISTER_DEBUG |
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106 | printk("openpic_read(0x%08x) = 0x%08x\n", (unsigned int)addr, val); |
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107 | #endif |
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108 | return val; |
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109 | } |
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110 | |
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111 | static inline void openpic_write(volatile unsigned int *addr, unsigned int val) |
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112 | { |
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113 | #ifdef REGISTER_DEBUG |
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114 | printk("openpic_write(0x%08x, 0x%08x)\n", (unsigned int)addr, val); |
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115 | #endif |
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116 | #ifdef BSP_OPEN_PIC_BIG_ENDIAN |
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117 | out_be32((volatile uint32_t *)addr, val); |
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118 | #else |
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119 | out_le32((volatile uint32_t *)addr, val); |
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120 | #endif |
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121 | } |
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122 | |
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123 | static inline unsigned int openpic_readfield(volatile unsigned int *addr, unsigned int mask) |
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124 | { |
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125 | unsigned int val = openpic_read(addr); |
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126 | return val & mask; |
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127 | } |
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128 | |
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129 | static inline void openpic_writefield(volatile unsigned int *addr, unsigned int mask, |
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130 | unsigned int field) |
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131 | { |
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132 | unsigned int val = openpic_read(addr); |
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133 | openpic_write(addr, (val & ~mask) | (field & mask)); |
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134 | } |
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135 | |
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136 | static inline void openpic_clearfield(volatile unsigned int *addr, unsigned int mask) |
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137 | { |
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138 | openpic_writefield(addr, mask, 0); |
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139 | } |
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140 | |
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141 | static inline void openpic_setfield(volatile unsigned int *addr, unsigned int mask) |
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142 | { |
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143 | openpic_writefield(addr, mask, mask); |
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144 | } |
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145 | |
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146 | /* |
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147 | * Update a Vector/Priority register in a safe manner. The interrupt will |
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148 | * be disabled. |
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149 | */ |
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150 | |
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151 | static void openpic_safe_writefield(volatile unsigned int *addr, unsigned int mask, |
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152 | unsigned int field) |
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153 | { |
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154 | openpic_setfield(addr, OPENPIC_MASK); |
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155 | /* wait until it's not in use */ |
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156 | while (openpic_read(addr) & OPENPIC_ACTIVITY); |
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157 | openpic_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK); |
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158 | } |
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159 | |
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160 | /* -------- Global Operations ---------------------------------------------- */ |
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161 | |
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162 | /* |
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163 | * Initialize the OpenPIC |
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164 | * |
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165 | * Add some kludge to use the Motorola Raven OpenPIC which does not |
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166 | * report vendor and device id, and gets the wrong number of interrupts. |
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167 | * (Motorola did a great job on that one!) |
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168 | * |
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169 | * T. Straumann, 12/20/2001: polarities and senses are now passed as |
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170 | * parameters, eliminated global vars. |
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171 | * IRQ0 is no longer treated specially. |
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172 | */ |
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173 | |
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174 | void openpic_init(int main_pic, unsigned char *polarities, unsigned char *senses, int num_sources, int source_offset, unsigned long epic_freq) |
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175 | { |
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176 | unsigned int t, i; |
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177 | unsigned int vendorid, devid, stepping, timerfreq; |
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178 | const char *version, *vendor, *device; |
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179 | |
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180 | if (!OpenPIC) |
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181 | rtems_panic("No OpenPIC found"); |
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182 | |
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183 | t = openpic_read(&OpenPIC->Global.Feature_Reporting0); |
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184 | switch (t & OPENPIC_FEATURE_VERSION_MASK) { |
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185 | case 1: |
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186 | version = "1.0"; |
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187 | break; |
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188 | case 2: |
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189 | version = "1.2"; |
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190 | break; |
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191 | default: |
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192 | version = "?"; |
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193 | break; |
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194 | } |
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195 | NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >> |
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196 | OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1; |
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197 | NumSources = ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >> |
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198 | OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1; |
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199 | t = openpic_read(&OpenPIC->Global.Vendor_Identification); |
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200 | |
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201 | vendorid = t & OPENPIC_VENDOR_ID_VENDOR_ID_MASK; |
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202 | devid = (t & OPENPIC_VENDOR_ID_DEVICE_ID_MASK) >> |
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203 | OPENPIC_VENDOR_ID_DEVICE_ID_SHIFT; |
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204 | stepping = (t & OPENPIC_VENDOR_ID_STEPPING_MASK) >> |
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205 | OPENPIC_VENDOR_ID_STEPPING_SHIFT; |
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206 | |
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207 | /* Kludge for the Raven */ |
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208 | /* |
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209 | pci_read_config_dword(0, 0, 0, 0, &t); |
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210 | */ |
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211 | if (t == PCI_VENDOR_ID_MOTOROLA + (PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) { |
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212 | vendor = "Motorola"; |
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213 | device = "Raven"; |
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214 | NumSources += 1; |
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215 | } |
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216 | else if (t == PCI_VENDOR_ID_MOTOROLA + (PCI_DEVICE_ID_MOTOROLA_HAWK<<16)) { |
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217 | vendor = "Motorola"; |
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218 | device = "Hawk"; |
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219 | NumSources += 1; |
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220 | } else { |
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221 | switch (vendorid) { |
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222 | case OPENPIC_VENDOR_ID_APPLE: |
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223 | vendor = "Apple"; |
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224 | break; |
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225 | default: |
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226 | vendor = "Unknown"; |
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227 | break; |
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228 | } |
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229 | switch (devid) { |
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230 | case OPENPIC_DEVICE_ID_APPLE_HYDRA: |
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231 | device = "Hydra"; |
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232 | break; |
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233 | default: |
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234 | device = "Unknown"; |
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235 | break; |
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236 | } |
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237 | } |
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238 | printk("OpenPIC Version %s (%d CPUs and %d IRQ sources) at 0x%08" PRIuPTR "\n", version, |
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239 | NumProcessors, NumSources, (uintptr_t) OpenPIC); |
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240 | |
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241 | printk("OpenPIC Vendor %d (%s), Device %d (%s), Stepping %d\n", vendorid, |
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242 | vendor, devid, device, stepping); |
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243 | |
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244 | /* Override if they desire */ |
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245 | if ( num_sources ) { |
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246 | if ( NumSources != num_sources ) |
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247 | printk("Overriding NumSources (%i) from configuration with %i\n", |
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248 | NumSources, num_sources); |
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249 | NumSources = num_sources; |
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250 | } |
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251 | |
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252 | openpic_src_offst = source_offset; |
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253 | |
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254 | timerfreq = openpic_read(&OpenPIC->Global.Timer_Frequency); |
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255 | printk("OpenPIC timer frequency is "); |
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256 | if (timerfreq) |
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257 | printk("%d Hz\n", timerfreq); |
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258 | else |
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259 | printk("not set\n"); |
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260 | |
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261 | if ( main_pic ) |
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262 | { |
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263 | /* Initialize timer interrupts */ |
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264 | for (i = 0; i < OPENPIC_NUM_TIMERS; i++) { |
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265 | /* Disabled, Priority 0 */ |
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266 | openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i); |
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267 | /* No processor */ |
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268 | openpic_maptimer(i, 0); |
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269 | } |
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270 | |
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271 | /* Initialize IPI interrupts */ |
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272 | for (i = 0; i < OPENPIC_NUM_IPI; i++) { |
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273 | /* Disabled, Priority 0 */ |
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274 | openpic_initipi(i, 0, OPENPIC_VEC_IPI+i); |
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275 | } |
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276 | |
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277 | /* Initialize external interrupts */ |
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278 | for (i = 0; i < NumSources; i++) { |
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279 | /* Enabled, Priority 8 */ |
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280 | openpic_initirq(i, 8, OPENPIC_VEC_SOURCE+i, |
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281 | polarities ? polarities[i] : 0, |
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282 | senses ? senses[i] : 1); |
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283 | /* Processor 0 */ |
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284 | openpic_mapirq(i, 1<<0); |
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285 | } |
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286 | |
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287 | /* Initialize the spurious interrupt */ |
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288 | openpic_set_spurious(OPENPIC_VEC_SPURIOUS); |
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289 | #if 0 |
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290 | if (request_irq(IRQ_8259_CASCADE, no_action, SA_INTERRUPT, |
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291 | "82c59 cascade", NULL)) |
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292 | printk("Unable to get OpenPIC IRQ 0 for cascade\n"); |
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293 | #endif |
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294 | openpic_set_priority(0, 0); |
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295 | openpic_disable_8259_pass_through(); |
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296 | } |
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297 | if ( epic_freq ) { |
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298 | /* Speed up the serial interface; if it is too slow then we might get spurious |
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299 | * interrupts: |
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300 | * After an ISR clears the interrupt condition at the source/device, the wire |
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301 | * remains asserted during the propagation delay introduced by the serial interface |
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302 | * (something really stupid). If the ISR returns while the wire is not released |
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303 | * yet, then a spurious interrupt happens. |
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304 | * The book says we should be careful if the serial clock is > 33MHz. |
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305 | * Empirically, it seems that running it at 33MHz is fast enough. Otherwise, |
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306 | * we should introduce a delay in openpic_eoi(). |
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307 | * The maximal delay are 16 (serial) clock cycles. If the divisor is 8 |
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308 | * [power-up default] then the lag is 2us [66MHz SDRAM clock; I assume this |
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309 | * is equal to the bus frequency]. |
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310 | * FIXME: This should probably be a EPIC-specific piece in 'openpic.c' |
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311 | * Unfortunately, there is no easy way of figuring out if the |
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312 | * device is an EPIC or not. |
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313 | */ |
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314 | uint32_t eicr_val, ratio; |
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315 | /* On the 8240 this is the EICR register */ |
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316 | eicr_val = in_le32( (volatile uint32_t *)&OpenPIC->Global.Global_Configuration1 ) & ~(7<<28); |
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317 | if ( (1<<27) & eicr_val ) { |
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318 | /* serial interface mode enabled */ |
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319 | |
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320 | /* round to nearest integer: |
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321 | * round(Bus_freq/33000000) = floor( 2*(Bus_freq/33e6) + 1 ) / 2 |
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322 | */ |
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323 | ratio = epic_freq / 16500000 + 1; |
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324 | ratio >>= 2; /* EICR value is half actual divisor */ |
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325 | if ( 0==ratio ) |
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326 | ratio = 1; |
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327 | out_le32((volatile uint32_t *)&OpenPIC->Global.Global_Configuration1, eicr_val | ((ratio &7) << 28)); |
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328 | /* Delay in TB cycles (assuming TB runs at 1/4 of the bus frequency) */ |
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329 | openpic_set_eoi_delay( 16 * (2*ratio) / 4 ); |
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330 | } |
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331 | } |
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332 | } |
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333 | |
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334 | /* |
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335 | * Reset the OpenPIC |
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336 | */ |
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337 | |
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338 | void openpic_reset(void) |
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339 | { |
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340 | openpic_setfield(&OpenPIC->Global.Global_Configuration0, |
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341 | OPENPIC_CONFIG_RESET); |
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342 | } |
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343 | |
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344 | /* |
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345 | * Enable/disable 8259 Pass Through Mode |
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346 | */ |
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347 | |
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348 | void openpic_enable_8259_pass_through(void) |
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349 | { |
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350 | openpic_clearfield(&OpenPIC->Global.Global_Configuration0, |
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351 | OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE); |
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352 | } |
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353 | |
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354 | void openpic_disable_8259_pass_through(void) |
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355 | { |
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356 | openpic_setfield(&OpenPIC->Global.Global_Configuration0, |
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357 | OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE); |
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358 | } |
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359 | |
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360 | /* |
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361 | * Find out the current interrupt |
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362 | */ |
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363 | |
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364 | unsigned int openpic_irq(unsigned int cpu) |
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365 | { |
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366 | unsigned int vec; |
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367 | |
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368 | check_arg_cpu(cpu); |
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369 | vec = openpic_readfield(&OpenPIC->THIS_CPU.Interrupt_Acknowledge, |
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370 | OPENPIC_VECTOR_MASK); |
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371 | return vec; |
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372 | } |
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373 | |
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374 | /* |
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375 | * Signal end of interrupt (EOI) processing |
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376 | */ |
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377 | |
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378 | void openpic_eoi(unsigned int cpu) |
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379 | { |
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380 | check_arg_cpu(cpu); |
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381 | if ( openpic_eoi_delay ) |
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382 | rtems_bsp_delay_in_bus_cycles(openpic_eoi_delay); |
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383 | openpic_write(&OpenPIC->THIS_CPU.EOI, 0); |
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384 | } |
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385 | |
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386 | unsigned openpic_set_eoi_delay(unsigned tb_cycles) |
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387 | { |
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388 | unsigned rval = openpic_eoi_delay; |
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389 | openpic_eoi_delay = tb_cycles; |
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390 | return rval; |
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391 | } |
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392 | |
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393 | /* |
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394 | * Get/set the current task priority |
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395 | */ |
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396 | |
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397 | unsigned int openpic_get_priority(unsigned int cpu) |
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398 | { |
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399 | CHECK_THIS_CPU; |
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400 | return openpic_readfield(&OpenPIC->THIS_CPU.Current_Task_Priority, |
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401 | OPENPIC_CURRENT_TASK_PRIORITY_MASK); |
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402 | } |
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403 | |
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404 | void openpic_set_priority(unsigned int cpu, unsigned int pri) |
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405 | { |
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406 | CHECK_THIS_CPU; |
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407 | check_arg_pri(pri); |
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408 | openpic_writefield(&OpenPIC->THIS_CPU.Current_Task_Priority, |
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409 | OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri); |
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410 | } |
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411 | |
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412 | /* |
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413 | * Get/set the spurious vector |
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414 | */ |
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415 | |
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416 | unsigned int openpic_get_spurious(void) |
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417 | { |
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418 | return openpic_readfield(&OpenPIC->Global.Spurious_Vector, |
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419 | OPENPIC_VECTOR_MASK); |
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420 | } |
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421 | |
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422 | void openpic_set_spurious(unsigned int vec) |
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423 | { |
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424 | check_arg_vec(vec); |
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425 | openpic_writefield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK, |
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426 | vec); |
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427 | } |
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428 | |
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429 | /* |
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430 | * Initialize one or more CPUs |
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431 | */ |
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432 | |
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433 | void openpic_init_processor(unsigned int cpumask) |
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434 | { |
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435 | openpic_write(&OpenPIC->Global.Processor_Initialization, cpumask); |
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436 | } |
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437 | |
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438 | /* -------- Interprocessor Interrupts -------------------------------------- */ |
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439 | |
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440 | /* |
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441 | * Initialize an interprocessor interrupt (and disable it) |
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442 | * |
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443 | * ipi: OpenPIC interprocessor interrupt number |
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444 | * pri: interrupt source priority |
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445 | * vec: the vector it will produce |
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446 | */ |
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447 | |
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448 | void openpic_initipi(unsigned int ipi, unsigned int pri, unsigned int vec) |
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449 | { |
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450 | check_arg_timer(ipi); |
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451 | check_arg_pri(pri); |
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452 | check_arg_vec(vec); |
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453 | openpic_safe_writefield(&OpenPIC->Global.IPI_Vector_Priority(ipi), |
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454 | OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK, |
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455 | (pri << OPENPIC_PRIORITY_SHIFT) | vec); |
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456 | } |
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457 | |
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458 | /* |
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459 | * Send an IPI to one or more CPUs |
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460 | */ |
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461 | |
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462 | void openpic_cause_IPI(unsigned int cpu, unsigned int ipi, unsigned int cpumask) |
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463 | { |
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464 | CHECK_THIS_CPU; |
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465 | check_arg_ipi(ipi); |
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466 | openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi), cpumask); |
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467 | } |
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468 | |
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469 | /* -------- Timer Interrupts ----------------------------------------------- */ |
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470 | |
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471 | /* |
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472 | * Initialize a timer interrupt (and disable it) |
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473 | * |
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474 | * timer: OpenPIC timer number |
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475 | * pri: interrupt source priority |
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476 | * vec: the vector it will produce |
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477 | */ |
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478 | |
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479 | void openpic_inittimer(unsigned int timer, unsigned int pri, unsigned int vec) |
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480 | { |
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481 | check_arg_timer(timer); |
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482 | check_arg_pri(pri); |
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483 | check_arg_vec(vec); |
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484 | openpic_safe_writefield(&OpenPIC->Global.Timer[timer].Vector_Priority, |
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485 | OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK, |
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486 | (pri << OPENPIC_PRIORITY_SHIFT) | vec); |
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487 | } |
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488 | |
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489 | /* |
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490 | * Map a timer interrupt to one or more CPUs |
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491 | */ |
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492 | |
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493 | void openpic_maptimer(unsigned int timer, unsigned int cpumask) |
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494 | { |
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495 | check_arg_timer(timer); |
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496 | openpic_write(&OpenPIC->Global.Timer[timer].Destination, cpumask); |
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497 | } |
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498 | |
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499 | /* |
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500 | * Set base count and / or enable / disable interrupt. |
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501 | */ |
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502 | |
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503 | |
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504 | void openpic_settimer(unsigned int timer, unsigned int base_count, int irq_enable) |
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505 | { |
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506 | check_arg_timer(timer); |
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507 | if ( base_count ) |
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508 | openpic_write(&OpenPIC->Global.Timer[timer].Base_Count, base_count); |
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509 | if ( irq_enable ) |
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510 | openpic_clearfield(&OpenPIC->Global.Timer[timer].Vector_Priority, OPENPIC_MASK); |
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511 | else |
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512 | openpic_setfield(&OpenPIC->Global.Timer[timer].Vector_Priority, OPENPIC_MASK); |
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513 | } |
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514 | |
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515 | unsigned int openpic_gettimer(unsigned int timer) |
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516 | { |
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517 | check_arg_timer(timer); |
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518 | return (openpic_read(&OpenPIC->Global.Timer[timer].Current_Count) & ~OPENPIC_MASK); |
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519 | } |
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520 | |
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521 | /* -------- Interrupt Sources ---------------------------------------------- */ |
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522 | |
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523 | /* |
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524 | * Enable/disable an interrupt source |
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525 | */ |
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526 | |
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527 | void openpic_enable_irq(unsigned int irq) |
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528 | { |
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529 | unsigned long flags; |
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530 | check_arg_irq(irq); |
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531 | rtems_interrupt_disable(flags); |
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532 | openpic_clearfield(&OpenPIC->SOURCE(irq).Vector_Priority, OPENPIC_MASK); |
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533 | rtems_interrupt_enable(flags); |
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534 | } |
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535 | |
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536 | int openpic_disable_irq(unsigned int irq) |
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537 | { |
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538 | int rval; |
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539 | unsigned long flags; |
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540 | check_arg_irq(irq); |
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541 | if ( irq < 0 || irq >=NumSources ) |
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542 | return -1; |
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543 | rtems_interrupt_disable(flags); |
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544 | rval = openpic_readfield(&OpenPIC->SOURCE(irq).Vector_Priority, OPENPIC_MASK) ? 0 : 1; |
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545 | openpic_setfield(&OpenPIC->SOURCE(irq).Vector_Priority, OPENPIC_MASK); |
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546 | rtems_interrupt_enable(flags); |
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547 | return rval; |
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548 | } |
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549 | |
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550 | /* |
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551 | * Initialize an interrupt source (and disable it!) |
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552 | * |
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553 | * irq: OpenPIC interrupt number |
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554 | * pri: interrupt source priority |
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555 | * vec: the vector it will produce |
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556 | * pol: polarity (1 for positive, 0 for negative) |
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557 | * sense: 1 for level, 0 for edge |
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558 | */ |
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559 | |
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560 | void openpic_initirq(unsigned int irq, unsigned int pri, unsigned int vec, int pol, int sense) |
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561 | { |
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562 | #if 0 |
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563 | printk("openpic_initirq: irq=%d pri=%d vec=%d pol=%d sense=%d\n", |
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564 | irq, pri, vec, pol, sense); |
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565 | #endif |
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566 | |
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567 | check_arg_irq(irq); |
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568 | check_arg_pri(pri); |
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569 | check_arg_vec(vec); |
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570 | openpic_safe_writefield(&OpenPIC->SOURCE(irq).Vector_Priority, |
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571 | OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK | |
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572 | OPENPIC_SENSE_POLARITY | OPENPIC_SENSE_LEVEL, |
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573 | (pri << OPENPIC_PRIORITY_SHIFT) | vec | |
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574 | (pol ? OPENPIC_SENSE_POLARITY : 0) | |
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575 | (sense ? OPENPIC_SENSE_LEVEL : 0)); |
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576 | } |
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577 | |
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578 | /* |
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579 | * Map an interrupt source to one or more CPUs |
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580 | */ |
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581 | |
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582 | void openpic_mapirq(unsigned int irq, unsigned int cpumask) |
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583 | { |
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584 | check_arg_irq(irq); |
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585 | openpic_write(&OpenPIC->SOURCE(irq).Destination, cpumask); |
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586 | } |
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587 | |
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588 | /* |
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589 | * Get the current priority of an external interrupt |
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590 | */ |
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591 | unsigned int openpic_get_source_priority(unsigned int irq) |
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592 | { |
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593 | check_arg_irq(irq); |
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594 | return openpic_readfield(&OpenPIC->SOURCE(irq).Vector_Priority, |
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595 | OPENPIC_PRIORITY_MASK) >> OPENPIC_PRIORITY_SHIFT; |
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596 | } |
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597 | |
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598 | void openpic_set_source_priority(unsigned int irq, unsigned int pri) |
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599 | { |
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600 | unsigned long flags; |
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601 | check_arg_irq(irq); |
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602 | check_arg_pri(pri); |
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603 | rtems_interrupt_disable(flags); |
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604 | openpic_writefield( |
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605 | &OpenPIC->SOURCE(irq).Vector_Priority, |
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606 | OPENPIC_PRIORITY_MASK, |
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607 | pri << OPENPIC_PRIORITY_SHIFT); |
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608 | rtems_interrupt_enable(flags); |
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609 | } |
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610 | /* |
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611 | * Set the sense for an interrupt source (and disable it!) |
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612 | * |
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613 | * sense: 1 for level, 0 for edge |
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614 | */ |
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615 | |
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616 | void openpic_set_sense(unsigned int irq, int sense) |
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617 | { |
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618 | check_arg_irq(irq); |
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619 | openpic_safe_writefield(&OpenPIC->SOURCE(irq).Vector_Priority, |
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620 | OPENPIC_SENSE_LEVEL, |
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621 | (sense ? OPENPIC_SENSE_LEVEL : 0)); |
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622 | } |
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