[acc25ee] | 1 | /* |
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| 2 | * openpic.c -- OpenPIC Interrupt Handling |
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| 3 | * |
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| 4 | * Copyright (C) 1997 Geert Uytterhoeven |
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| 5 | * |
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| 6 | * Modified to compile in RTEMS development environment |
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| 7 | * by Eric Valette |
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| 8 | * |
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| 9 | * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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| 10 | * |
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| 11 | * The license and distribution terms for this file may be |
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| 12 | * found in found in the file LICENSE in this distribution or at |
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[e831de8] | 13 | * http://www.rtems.com/license/LICENSE. |
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[acc25ee] | 14 | * |
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| 15 | * $Id$ |
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| 16 | */ |
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| 17 | |
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| 18 | /* |
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| 19 | * Note: Interprocessor Interrupt (IPI) and Timer support is incomplete |
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| 20 | */ |
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| 21 | |
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[ec6422e] | 22 | #include <rtems.h> |
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[e79a1947] | 23 | #include <bsp.h> |
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[20603d1] | 24 | #include <rtems/bspIo.h> |
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[acc25ee] | 25 | #include <bsp/openpic.h> |
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| 26 | #include <bsp/pci.h> |
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| 27 | #include <libcpu/io.h> |
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| 28 | #include <libcpu/byteorder.h> |
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[69ed59f] | 29 | #include <rtems/bspIo.h> |
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[acc25ee] | 30 | |
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[69ed59f] | 31 | #ifndef NULL |
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[acc25ee] | 32 | #define NULL 0 |
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[69ed59f] | 33 | #endif |
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[acc25ee] | 34 | #define REGISTER_DEBUG |
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| 35 | #undef REGISTER_DEBUG |
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| 36 | |
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| 37 | volatile struct OpenPIC *OpenPIC = NULL; |
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| 38 | |
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| 39 | static unsigned int NumProcessors; |
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| 40 | static unsigned int NumSources; |
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| 41 | |
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| 42 | /* |
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| 43 | * Accesses to the current processor's registers |
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| 44 | */ |
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| 45 | |
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| 46 | #define THIS_CPU Processor[cpu] |
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| 47 | #define CHECK_THIS_CPU check_arg_cpu(cpu) |
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| 48 | |
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| 49 | /* |
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| 50 | * Sanity checks |
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| 51 | */ |
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| 52 | |
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| 53 | #if 1 |
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| 54 | #define check_arg_ipi(ipi) \ |
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| 55 | if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \ |
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| 56 | printk("openpic.c:%d: illegal ipi %d\n", __LINE__, ipi); |
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| 57 | #define check_arg_timer(timer) \ |
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| 58 | if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \ |
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| 59 | printk("openpic.c:%d: illegal timer %d\n", __LINE__, timer); |
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| 60 | #define check_arg_vec(vec) \ |
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| 61 | if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \ |
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| 62 | printk("openpic.c:%d: illegal vector %d\n", __LINE__, vec); |
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| 63 | #define check_arg_pri(pri) \ |
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| 64 | if (pri < 0 || pri >= OPENPIC_NUM_PRI) \ |
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| 65 | printk("openpic.c:%d: illegal priority %d\n", __LINE__, pri); |
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| 66 | #define check_arg_irq(irq) \ |
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| 67 | if (irq < 0 || irq >= NumSources) \ |
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[0d6849e7] | 68 | printk("openpic.c:%d: illegal irq %d from 0x%08x,[0x%08x],[[0x%08x]]\n", \ |
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[acc25ee] | 69 | __LINE__, irq, __builtin_return_address(0), \ |
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| 70 | __builtin_return_address(1), __builtin_return_address(2) \ |
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| 71 | ); |
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| 72 | #define check_arg_cpu(cpu) \ |
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| 73 | if (cpu < 0 || cpu >= NumProcessors) \ |
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| 74 | printk("openpic.c:%d: illegal cpu %d\n", __LINE__, cpu); |
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| 75 | #else |
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| 76 | #define check_arg_ipi(ipi) do {} while (0) |
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| 77 | #define check_arg_timer(timer) do {} while (0) |
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| 78 | #define check_arg_vec(vec) do {} while (0) |
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| 79 | #define check_arg_pri(pri) do {} while (0) |
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| 80 | #define check_arg_irq(irq) do {} while (0) |
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| 81 | #define check_arg_cpu(cpu) do {} while (0) |
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| 82 | #endif |
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| 83 | |
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| 84 | /* |
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| 85 | * I/O functions |
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| 86 | */ |
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| 87 | |
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| 88 | static inline unsigned int openpic_read(volatile unsigned int *addr) |
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| 89 | { |
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| 90 | unsigned int val; |
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| 91 | |
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[ec6422e] | 92 | val = in_le32(addr); |
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[acc25ee] | 93 | #ifdef REGISTER_DEBUG |
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| 94 | printk("openpic_read(0x%08x) = 0x%08x\n", (unsigned int)addr, val); |
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| 95 | #endif |
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| 96 | return val; |
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| 97 | } |
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| 98 | |
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| 99 | static inline void openpic_write(volatile unsigned int *addr, unsigned int val) |
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| 100 | { |
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| 101 | #ifdef REGISTER_DEBUG |
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| 102 | printk("openpic_write(0x%08x, 0x%08x)\n", (unsigned int)addr, val); |
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| 103 | #endif |
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| 104 | out_le32(addr, val); |
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| 105 | } |
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| 106 | |
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| 107 | static inline unsigned int openpic_readfield(volatile unsigned int *addr, unsigned int mask) |
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| 108 | { |
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| 109 | unsigned int val = openpic_read(addr); |
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| 110 | return val & mask; |
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| 111 | } |
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| 112 | |
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| 113 | inline void openpic_writefield(volatile unsigned int *addr, unsigned int mask, |
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| 114 | unsigned int field) |
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| 115 | { |
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| 116 | unsigned int val = openpic_read(addr); |
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| 117 | openpic_write(addr, (val & ~mask) | (field & mask)); |
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| 118 | } |
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| 119 | |
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| 120 | static inline void openpic_clearfield(volatile unsigned int *addr, unsigned int mask) |
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| 121 | { |
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| 122 | openpic_writefield(addr, mask, 0); |
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| 123 | } |
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| 124 | |
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| 125 | static inline void openpic_setfield(volatile unsigned int *addr, unsigned int mask) |
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| 126 | { |
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| 127 | openpic_writefield(addr, mask, mask); |
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| 128 | } |
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| 129 | |
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| 130 | /* |
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| 131 | * Update a Vector/Priority register in a safe manner. The interrupt will |
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| 132 | * be disabled. |
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| 133 | */ |
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| 134 | |
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| 135 | static void openpic_safe_writefield(volatile unsigned int *addr, unsigned int mask, |
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| 136 | unsigned int field) |
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| 137 | { |
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| 138 | openpic_setfield(addr, OPENPIC_MASK); |
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| 139 | /* wait until it's not in use */ |
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| 140 | while (openpic_read(addr) & OPENPIC_ACTIVITY); |
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| 141 | openpic_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK); |
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| 142 | } |
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| 143 | |
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| 144 | /* -------- Global Operations ---------------------------------------------- */ |
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| 145 | |
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| 146 | /* |
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| 147 | * Initialize the OpenPIC |
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| 148 | * |
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| 149 | * Add some kludge to use the Motorola Raven OpenPIC which does not |
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| 150 | * report vendor and device id, and gets the wrong number of interrupts. |
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| 151 | * (Motorola did a great job on that one!) |
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[69ed59f] | 152 | * |
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| 153 | * T. Straumann, 12/20/2001: polarities and senses are now passed as |
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| 154 | * parameters, eliminated global vars. |
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| 155 | * IRQ0 is no longer treated specially. |
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[acc25ee] | 156 | */ |
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| 157 | |
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[69ed59f] | 158 | void openpic_init(int main_pic, unsigned char *polarities, unsigned char *senses) |
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[acc25ee] | 159 | { |
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| 160 | unsigned int t, i; |
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| 161 | unsigned int vendorid, devid, stepping, timerfreq; |
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| 162 | const char *version, *vendor, *device; |
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| 163 | |
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| 164 | if (!OpenPIC) |
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| 165 | BSP_panic("No OpenPIC found"); |
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| 166 | |
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| 167 | t = openpic_read(&OpenPIC->Global.Feature_Reporting0); |
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| 168 | switch (t & OPENPIC_FEATURE_VERSION_MASK) { |
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| 169 | case 1: |
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| 170 | version = "1.0"; |
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| 171 | break; |
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| 172 | case 2: |
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| 173 | version = "1.2"; |
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| 174 | break; |
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| 175 | default: |
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| 176 | version = "?"; |
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| 177 | break; |
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| 178 | } |
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| 179 | NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >> |
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| 180 | OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1; |
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| 181 | NumSources = ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >> |
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| 182 | OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1; |
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| 183 | t = openpic_read(&OpenPIC->Global.Vendor_Identification); |
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| 184 | |
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| 185 | vendorid = t & OPENPIC_VENDOR_ID_VENDOR_ID_MASK; |
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| 186 | devid = (t & OPENPIC_VENDOR_ID_DEVICE_ID_MASK) >> |
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| 187 | OPENPIC_VENDOR_ID_DEVICE_ID_SHIFT; |
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| 188 | stepping = (t & OPENPIC_VENDOR_ID_STEPPING_MASK) >> |
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| 189 | OPENPIC_VENDOR_ID_STEPPING_SHIFT; |
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| 190 | |
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| 191 | /* Kludge for the Raven */ |
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[e79a1947] | 192 | /* |
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[acc25ee] | 193 | pci_read_config_dword(0, 0, 0, 0, &t); |
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[e79a1947] | 194 | */ |
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[acc25ee] | 195 | if (t == PCI_VENDOR_ID_MOTOROLA + (PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) { |
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| 196 | vendor = "Motorola"; |
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| 197 | device = "Raven"; |
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| 198 | NumSources += 1; |
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| 199 | } else { |
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| 200 | switch (vendorid) { |
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| 201 | case OPENPIC_VENDOR_ID_APPLE: |
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| 202 | vendor = "Apple"; |
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| 203 | break; |
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| 204 | default: |
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| 205 | vendor = "Unknown"; |
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| 206 | break; |
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| 207 | } |
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| 208 | switch (devid) { |
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| 209 | case OPENPIC_DEVICE_ID_APPLE_HYDRA: |
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| 210 | device = "Hydra"; |
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| 211 | break; |
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| 212 | default: |
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| 213 | device = "Unknown"; |
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| 214 | break; |
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| 215 | } |
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| 216 | } |
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[0d6849e7] | 217 | printk("OpenPIC Version %s (%d CPUs and %d IRQ sources) at 0x%08x\n", version, |
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[acc25ee] | 218 | NumProcessors, NumSources, OpenPIC); |
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| 219 | |
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| 220 | printk("OpenPIC Vendor %d (%s), Device %d (%s), Stepping %d\n", vendorid, |
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| 221 | vendor, devid, device, stepping); |
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| 222 | |
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| 223 | timerfreq = openpic_read(&OpenPIC->Global.Timer_Frequency); |
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| 224 | printk("OpenPIC timer frequency is "); |
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| 225 | if (timerfreq) |
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| 226 | printk("%d Hz\n", timerfreq); |
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| 227 | else |
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| 228 | printk("not set\n"); |
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| 229 | |
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| 230 | if ( main_pic ) |
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| 231 | { |
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| 232 | /* Initialize timer interrupts */ |
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| 233 | for (i = 0; i < OPENPIC_NUM_TIMERS; i++) { |
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| 234 | /* Disabled, Priority 0 */ |
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| 235 | openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i); |
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| 236 | /* No processor */ |
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| 237 | openpic_maptimer(i, 0); |
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| 238 | } |
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[6128a4a] | 239 | |
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[acc25ee] | 240 | /* Initialize IPI interrupts */ |
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| 241 | for (i = 0; i < OPENPIC_NUM_IPI; i++) { |
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| 242 | /* Disabled, Priority 0 */ |
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| 243 | openpic_initipi(i, 0, OPENPIC_VEC_IPI+i); |
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| 244 | } |
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[6128a4a] | 245 | |
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[acc25ee] | 246 | /* Initialize external interrupts */ |
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[69ed59f] | 247 | for (i = 0; i < NumSources; i++) { |
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[acc25ee] | 248 | /* Enabled, Priority 8 */ |
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[69ed59f] | 249 | openpic_initirq(i, 8, OPENPIC_VEC_SOURCE+i, |
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| 250 | polarities ? polarities[i] : 0, |
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| 251 | senses ? senses[i] : 1); |
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[acc25ee] | 252 | /* Processor 0 */ |
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| 253 | openpic_mapirq(i, 1<<0); |
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| 254 | } |
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[6128a4a] | 255 | |
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[acc25ee] | 256 | /* Initialize the spurious interrupt */ |
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| 257 | openpic_set_spurious(OPENPIC_VEC_SPURIOUS); |
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[6128a4a] | 258 | #if 0 |
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[acc25ee] | 259 | if (request_irq(IRQ_8259_CASCADE, no_action, SA_INTERRUPT, |
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| 260 | "82c59 cascade", NULL)) |
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| 261 | printk("Unable to get OpenPIC IRQ 0 for cascade\n"); |
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[6128a4a] | 262 | #endif |
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[acc25ee] | 263 | openpic_set_priority(0, 0); |
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| 264 | openpic_disable_8259_pass_through(); |
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| 265 | } |
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| 266 | } |
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| 267 | |
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| 268 | /* |
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| 269 | * Reset the OpenPIC |
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| 270 | */ |
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| 271 | |
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| 272 | void openpic_reset(void) |
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| 273 | { |
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| 274 | openpic_setfield(&OpenPIC->Global.Global_Configuration0, |
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| 275 | OPENPIC_CONFIG_RESET); |
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| 276 | } |
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| 277 | |
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| 278 | /* |
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| 279 | * Enable/disable 8259 Pass Through Mode |
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| 280 | */ |
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| 281 | |
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| 282 | void openpic_enable_8259_pass_through(void) |
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| 283 | { |
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| 284 | openpic_clearfield(&OpenPIC->Global.Global_Configuration0, |
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| 285 | OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE); |
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| 286 | } |
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| 287 | |
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| 288 | void openpic_disable_8259_pass_through(void) |
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| 289 | { |
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| 290 | openpic_setfield(&OpenPIC->Global.Global_Configuration0, |
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| 291 | OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE); |
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| 292 | } |
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| 293 | |
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| 294 | /* |
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| 295 | * Find out the current interrupt |
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| 296 | */ |
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| 297 | |
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| 298 | unsigned int openpic_irq(unsigned int cpu) |
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| 299 | { |
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| 300 | unsigned int vec; |
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| 301 | |
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| 302 | check_arg_cpu(cpu); |
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| 303 | vec = openpic_readfield(&OpenPIC->THIS_CPU.Interrupt_Acknowledge, |
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| 304 | OPENPIC_VECTOR_MASK); |
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| 305 | return vec; |
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| 306 | } |
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| 307 | |
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| 308 | /* |
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| 309 | * Signal end of interrupt (EOI) processing |
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| 310 | */ |
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| 311 | |
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| 312 | void openpic_eoi(unsigned int cpu) |
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| 313 | { |
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| 314 | check_arg_cpu(cpu); |
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| 315 | openpic_write(&OpenPIC->THIS_CPU.EOI, 0); |
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| 316 | } |
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| 317 | |
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| 318 | /* |
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| 319 | * Get/set the current task priority |
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| 320 | */ |
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| 321 | |
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| 322 | unsigned int openpic_get_priority(unsigned int cpu) |
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| 323 | { |
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| 324 | CHECK_THIS_CPU; |
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| 325 | return openpic_readfield(&OpenPIC->THIS_CPU.Current_Task_Priority, |
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| 326 | OPENPIC_CURRENT_TASK_PRIORITY_MASK); |
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| 327 | } |
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| 328 | |
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| 329 | void openpic_set_priority(unsigned int cpu, unsigned int pri) |
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| 330 | { |
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| 331 | CHECK_THIS_CPU; |
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| 332 | check_arg_pri(pri); |
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| 333 | openpic_writefield(&OpenPIC->THIS_CPU.Current_Task_Priority, |
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| 334 | OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri); |
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| 335 | } |
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| 336 | |
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| 337 | /* |
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| 338 | * Get/set the spurious vector |
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| 339 | */ |
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| 340 | |
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| 341 | unsigned int openpic_get_spurious(void) |
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| 342 | { |
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| 343 | return openpic_readfield(&OpenPIC->Global.Spurious_Vector, |
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| 344 | OPENPIC_VECTOR_MASK); |
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| 345 | } |
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| 346 | |
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| 347 | void openpic_set_spurious(unsigned int vec) |
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| 348 | { |
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| 349 | check_arg_vec(vec); |
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| 350 | openpic_writefield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK, |
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| 351 | vec); |
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| 352 | } |
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| 353 | |
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| 354 | /* |
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| 355 | * Initialize one or more CPUs |
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| 356 | */ |
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| 357 | |
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| 358 | void openpic_init_processor(unsigned int cpumask) |
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| 359 | { |
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| 360 | openpic_write(&OpenPIC->Global.Processor_Initialization, cpumask); |
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| 361 | } |
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| 362 | |
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| 363 | /* -------- Interprocessor Interrupts -------------------------------------- */ |
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| 364 | |
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| 365 | /* |
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| 366 | * Initialize an interprocessor interrupt (and disable it) |
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| 367 | * |
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| 368 | * ipi: OpenPIC interprocessor interrupt number |
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| 369 | * pri: interrupt source priority |
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| 370 | * vec: the vector it will produce |
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| 371 | */ |
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| 372 | |
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| 373 | void openpic_initipi(unsigned int ipi, unsigned int pri, unsigned int vec) |
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| 374 | { |
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| 375 | check_arg_timer(ipi); |
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| 376 | check_arg_pri(pri); |
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| 377 | check_arg_vec(vec); |
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| 378 | openpic_safe_writefield(&OpenPIC->Global.IPI_Vector_Priority(ipi), |
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| 379 | OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK, |
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| 380 | (pri << OPENPIC_PRIORITY_SHIFT) | vec); |
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| 381 | } |
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| 382 | |
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| 383 | /* |
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| 384 | * Send an IPI to one or more CPUs |
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| 385 | */ |
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| 386 | |
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| 387 | void openpic_cause_IPI(unsigned int cpu, unsigned int ipi, unsigned int cpumask) |
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| 388 | { |
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| 389 | CHECK_THIS_CPU; |
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| 390 | check_arg_ipi(ipi); |
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| 391 | openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi), cpumask); |
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| 392 | } |
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| 393 | |
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| 394 | /* -------- Timer Interrupts ----------------------------------------------- */ |
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| 395 | |
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| 396 | /* |
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| 397 | * Initialize a timer interrupt (and disable it) |
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| 398 | * |
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| 399 | * timer: OpenPIC timer number |
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| 400 | * pri: interrupt source priority |
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| 401 | * vec: the vector it will produce |
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| 402 | */ |
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| 403 | |
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| 404 | void openpic_inittimer(unsigned int timer, unsigned int pri, unsigned int vec) |
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| 405 | { |
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| 406 | check_arg_timer(timer); |
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| 407 | check_arg_pri(pri); |
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| 408 | check_arg_vec(vec); |
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| 409 | openpic_safe_writefield(&OpenPIC->Global.Timer[timer].Vector_Priority, |
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| 410 | OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK, |
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| 411 | (pri << OPENPIC_PRIORITY_SHIFT) | vec); |
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| 412 | } |
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| 413 | |
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| 414 | /* |
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| 415 | * Map a timer interrupt to one or more CPUs |
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| 416 | */ |
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| 417 | |
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| 418 | void openpic_maptimer(unsigned int timer, unsigned int cpumask) |
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| 419 | { |
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| 420 | check_arg_timer(timer); |
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| 421 | openpic_write(&OpenPIC->Global.Timer[timer].Destination, cpumask); |
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| 422 | } |
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| 423 | |
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| 424 | /* -------- Interrupt Sources ---------------------------------------------- */ |
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| 425 | |
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| 426 | /* |
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| 427 | * Enable/disable an interrupt source |
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| 428 | */ |
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| 429 | |
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| 430 | void openpic_enable_irq(unsigned int irq) |
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| 431 | { |
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[ec6422e] | 432 | unsigned long flags; |
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[acc25ee] | 433 | check_arg_irq(irq); |
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[ec6422e] | 434 | rtems_interrupt_disable(flags); |
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[acc25ee] | 435 | openpic_clearfield(&OpenPIC->Source[irq].Vector_Priority, OPENPIC_MASK); |
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[ec6422e] | 436 | rtems_interrupt_enable(flags); |
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[acc25ee] | 437 | } |
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| 438 | |
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| 439 | void openpic_disable_irq(unsigned int irq) |
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| 440 | { |
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[ec6422e] | 441 | unsigned long flags; |
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[acc25ee] | 442 | check_arg_irq(irq); |
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[ec6422e] | 443 | rtems_interrupt_disable(flags); |
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[acc25ee] | 444 | openpic_setfield(&OpenPIC->Source[irq].Vector_Priority, OPENPIC_MASK); |
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[ec6422e] | 445 | rtems_interrupt_enable(flags); |
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[acc25ee] | 446 | } |
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| 447 | |
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| 448 | /* |
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| 449 | * Initialize an interrupt source (and disable it!) |
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| 450 | * |
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| 451 | * irq: OpenPIC interrupt number |
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| 452 | * pri: interrupt source priority |
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| 453 | * vec: the vector it will produce |
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| 454 | * pol: polarity (1 for positive, 0 for negative) |
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| 455 | * sense: 1 for level, 0 for edge |
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| 456 | */ |
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| 457 | |
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| 458 | void openpic_initirq(unsigned int irq, unsigned int pri, unsigned int vec, int pol, int sense) |
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| 459 | { |
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[e79a1947] | 460 | #if 0 |
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| 461 | printk("openpic_initirq: irq=%d pri=%d vec=%d pol=%d sense=%d\n", |
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| 462 | irq, pri, vec, pol, sense); |
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| 463 | #endif |
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| 464 | |
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[acc25ee] | 465 | check_arg_irq(irq); |
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| 466 | check_arg_pri(pri); |
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| 467 | check_arg_vec(vec); |
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| 468 | openpic_safe_writefield(&OpenPIC->Source[irq].Vector_Priority, |
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| 469 | OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK | |
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| 470 | OPENPIC_SENSE_POLARITY | OPENPIC_SENSE_LEVEL, |
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| 471 | (pri << OPENPIC_PRIORITY_SHIFT) | vec | |
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| 472 | (pol ? OPENPIC_SENSE_POLARITY : 0) | |
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| 473 | (sense ? OPENPIC_SENSE_LEVEL : 0)); |
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| 474 | } |
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| 475 | |
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| 476 | /* |
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| 477 | * Map an interrupt source to one or more CPUs |
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| 478 | */ |
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| 479 | |
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| 480 | void openpic_mapirq(unsigned int irq, unsigned int cpumask) |
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| 481 | { |
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| 482 | check_arg_irq(irq); |
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| 483 | openpic_write(&OpenPIC->Source[irq].Destination, cpumask); |
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| 484 | } |
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| 485 | |
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[ec6422e] | 486 | /* |
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| 487 | * Get the current priority of an external interrupt |
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| 488 | */ |
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| 489 | unsigned int openpic_get_source_priority(unsigned int irq) |
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| 490 | { |
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| 491 | check_arg_irq(irq); |
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| 492 | return openpic_readfield(&OpenPIC->Source[irq].Vector_Priority, |
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| 493 | OPENPIC_PRIORITY_MASK) >> OPENPIC_PRIORITY_SHIFT; |
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| 494 | } |
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[acc25ee] | 495 | |
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[ec6422e] | 496 | void openpic_set_source_priority(unsigned int irq, unsigned int pri) |
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| 497 | { |
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| 498 | unsigned long flags; |
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| 499 | check_arg_irq(irq); |
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| 500 | check_arg_pri(pri); |
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| 501 | rtems_interrupt_disable(flags); |
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| 502 | openpic_writefield( |
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| 503 | &OpenPIC->Source[irq].Vector_Priority, |
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| 504 | OPENPIC_PRIORITY_MASK, |
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| 505 | pri << OPENPIC_PRIORITY_SHIFT); |
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| 506 | rtems_interrupt_enable(flags); |
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| 507 | } |
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[acc25ee] | 508 | /* |
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| 509 | * Set the sense for an interrupt source (and disable it!) |
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| 510 | * |
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| 511 | * sense: 1 for level, 0 for edge |
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| 512 | */ |
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| 513 | |
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| 514 | void openpic_set_sense(unsigned int irq, int sense) |
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| 515 | { |
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| 516 | check_arg_irq(irq); |
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| 517 | openpic_safe_writefield(&OpenPIC->Source[irq].Vector_Priority, |
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| 518 | OPENPIC_SENSE_LEVEL, |
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| 519 | (sense ? OPENPIC_SENSE_LEVEL : 0)); |
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| 520 | } |
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