[acc25ee] | 1 | /* |
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| 2 | * openpic.c -- OpenPIC Interrupt Handling |
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| 3 | * |
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| 4 | * Copyright (C) 1997 Geert Uytterhoeven |
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| 5 | * |
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| 6 | * Modified to compile in RTEMS development environment |
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| 7 | * by Eric Valette |
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| 8 | * |
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| 9 | * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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| 10 | * |
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| 11 | * The license and distribution terms for this file may be |
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| 12 | * found in found in the file LICENSE in this distribution or at |
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| 13 | * http://www.OARcorp.com/rtems/license.html. |
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| 14 | * |
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| 15 | * $Id$ |
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| 16 | */ |
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| 17 | |
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| 18 | /* |
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| 19 | * Note: Interprocessor Interrupt (IPI) and Timer support is incomplete |
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| 20 | */ |
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| 21 | |
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[2742cc3] | 22 | #include <rtems.h> |
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[20603d1] | 23 | #include <rtems/bspIo.h> |
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[acc25ee] | 24 | #include <bsp/openpic.h> |
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| 25 | #include <bsp/pci.h> |
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| 26 | #include <bsp/consoleIo.h> |
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| 27 | #include <libcpu/io.h> |
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| 28 | #include <libcpu/byteorder.h> |
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| 29 | #include <bsp.h> |
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[69ed59f] | 30 | #include <rtems/bspIo.h> |
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[acc25ee] | 31 | |
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[69ed59f] | 32 | #ifndef NULL |
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[acc25ee] | 33 | #define NULL 0 |
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[69ed59f] | 34 | #endif |
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[acc25ee] | 35 | #define REGISTER_DEBUG |
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| 36 | #undef REGISTER_DEBUG |
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| 37 | |
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| 38 | |
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| 39 | volatile struct OpenPIC *OpenPIC = NULL; |
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| 40 | |
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| 41 | static unsigned int NumProcessors; |
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| 42 | static unsigned int NumSources; |
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| 43 | |
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| 44 | |
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| 45 | /* |
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| 46 | * Accesses to the current processor's registers |
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| 47 | */ |
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| 48 | |
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| 49 | #define THIS_CPU Processor[cpu] |
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| 50 | #define CHECK_THIS_CPU check_arg_cpu(cpu) |
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| 51 | |
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| 52 | |
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| 53 | /* |
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| 54 | * Sanity checks |
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| 55 | */ |
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| 56 | |
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| 57 | #if 1 |
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| 58 | #define check_arg_ipi(ipi) \ |
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| 59 | if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \ |
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| 60 | printk("openpic.c:%d: illegal ipi %d\n", __LINE__, ipi); |
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| 61 | #define check_arg_timer(timer) \ |
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| 62 | if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \ |
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| 63 | printk("openpic.c:%d: illegal timer %d\n", __LINE__, timer); |
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| 64 | #define check_arg_vec(vec) \ |
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| 65 | if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \ |
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| 66 | printk("openpic.c:%d: illegal vector %d\n", __LINE__, vec); |
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| 67 | #define check_arg_pri(pri) \ |
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| 68 | if (pri < 0 || pri >= OPENPIC_NUM_PRI) \ |
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| 69 | printk("openpic.c:%d: illegal priority %d\n", __LINE__, pri); |
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| 70 | #define check_arg_irq(irq) \ |
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| 71 | if (irq < 0 || irq >= NumSources) \ |
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| 72 | printk("openpic.c:%d: illegal irq %d from %p,[%p],[[%p]]\n", \ |
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| 73 | __LINE__, irq, __builtin_return_address(0), \ |
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| 74 | __builtin_return_address(1), __builtin_return_address(2) \ |
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| 75 | ); |
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| 76 | #define check_arg_cpu(cpu) \ |
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| 77 | if (cpu < 0 || cpu >= NumProcessors) \ |
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| 78 | printk("openpic.c:%d: illegal cpu %d\n", __LINE__, cpu); |
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| 79 | #else |
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| 80 | #define check_arg_ipi(ipi) do {} while (0) |
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| 81 | #define check_arg_timer(timer) do {} while (0) |
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| 82 | #define check_arg_vec(vec) do {} while (0) |
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| 83 | #define check_arg_pri(pri) do {} while (0) |
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| 84 | #define check_arg_irq(irq) do {} while (0) |
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| 85 | #define check_arg_cpu(cpu) do {} while (0) |
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| 86 | #endif |
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| 87 | |
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| 88 | |
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| 89 | |
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| 90 | /* |
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| 91 | * I/O functions |
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| 92 | */ |
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| 93 | |
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| 94 | static inline unsigned int openpic_read(volatile unsigned int *addr) |
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| 95 | { |
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| 96 | unsigned int val; |
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| 97 | |
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[2742cc3] | 98 | val = in_le32(addr); |
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[acc25ee] | 99 | #ifdef REGISTER_DEBUG |
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| 100 | printk("openpic_read(0x%08x) = 0x%08x\n", (unsigned int)addr, val); |
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| 101 | #endif |
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| 102 | return val; |
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| 103 | } |
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| 104 | |
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| 105 | static inline void openpic_write(volatile unsigned int *addr, unsigned int val) |
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| 106 | { |
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| 107 | #ifdef REGISTER_DEBUG |
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| 108 | printk("openpic_write(0x%08x, 0x%08x)\n", (unsigned int)addr, val); |
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| 109 | #endif |
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| 110 | out_le32(addr, val); |
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| 111 | } |
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| 112 | |
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| 113 | |
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| 114 | static inline unsigned int openpic_readfield(volatile unsigned int *addr, unsigned int mask) |
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| 115 | { |
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| 116 | unsigned int val = openpic_read(addr); |
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| 117 | return val & mask; |
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| 118 | } |
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| 119 | |
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| 120 | inline void openpic_writefield(volatile unsigned int *addr, unsigned int mask, |
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| 121 | unsigned int field) |
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| 122 | { |
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| 123 | unsigned int val = openpic_read(addr); |
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| 124 | openpic_write(addr, (val & ~mask) | (field & mask)); |
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| 125 | } |
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| 126 | |
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| 127 | static inline void openpic_clearfield(volatile unsigned int *addr, unsigned int mask) |
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| 128 | { |
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| 129 | openpic_writefield(addr, mask, 0); |
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| 130 | } |
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| 131 | |
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| 132 | static inline void openpic_setfield(volatile unsigned int *addr, unsigned int mask) |
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| 133 | { |
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| 134 | openpic_writefield(addr, mask, mask); |
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| 135 | } |
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| 136 | |
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| 137 | |
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| 138 | /* |
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| 139 | * Update a Vector/Priority register in a safe manner. The interrupt will |
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| 140 | * be disabled. |
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| 141 | */ |
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| 142 | |
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| 143 | static void openpic_safe_writefield(volatile unsigned int *addr, unsigned int mask, |
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| 144 | unsigned int field) |
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| 145 | { |
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| 146 | openpic_setfield(addr, OPENPIC_MASK); |
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| 147 | /* wait until it's not in use */ |
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| 148 | while (openpic_read(addr) & OPENPIC_ACTIVITY); |
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| 149 | openpic_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK); |
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| 150 | } |
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| 151 | |
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| 152 | |
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| 153 | /* -------- Global Operations ---------------------------------------------- */ |
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| 154 | |
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| 155 | |
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| 156 | /* |
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| 157 | * Initialize the OpenPIC |
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| 158 | * |
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| 159 | * Add some kludge to use the Motorola Raven OpenPIC which does not |
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| 160 | * report vendor and device id, and gets the wrong number of interrupts. |
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| 161 | * (Motorola did a great job on that one!) |
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[69ed59f] | 162 | * |
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| 163 | * T. Straumann, 12/20/2001: polarities and senses are now passed as |
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| 164 | * parameters, eliminated global vars. |
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| 165 | * IRQ0 is no longer treated specially. |
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[acc25ee] | 166 | */ |
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| 167 | |
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[69ed59f] | 168 | void openpic_init(int main_pic, unsigned char *polarities, unsigned char *senses) |
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[acc25ee] | 169 | { |
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| 170 | unsigned int t, i; |
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| 171 | unsigned int vendorid, devid, stepping, timerfreq; |
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| 172 | const char *version, *vendor, *device; |
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| 173 | |
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| 174 | if (!OpenPIC) |
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| 175 | BSP_panic("No OpenPIC found"); |
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| 176 | |
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| 177 | t = openpic_read(&OpenPIC->Global.Feature_Reporting0); |
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| 178 | switch (t & OPENPIC_FEATURE_VERSION_MASK) { |
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| 179 | case 1: |
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| 180 | version = "1.0"; |
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| 181 | break; |
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| 182 | case 2: |
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| 183 | version = "1.2"; |
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| 184 | break; |
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| 185 | default: |
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| 186 | version = "?"; |
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| 187 | break; |
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| 188 | } |
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| 189 | NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >> |
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| 190 | OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1; |
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| 191 | NumSources = ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >> |
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| 192 | OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1; |
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| 193 | t = openpic_read(&OpenPIC->Global.Vendor_Identification); |
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| 194 | |
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| 195 | vendorid = t & OPENPIC_VENDOR_ID_VENDOR_ID_MASK; |
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| 196 | devid = (t & OPENPIC_VENDOR_ID_DEVICE_ID_MASK) >> |
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| 197 | OPENPIC_VENDOR_ID_DEVICE_ID_SHIFT; |
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| 198 | stepping = (t & OPENPIC_VENDOR_ID_STEPPING_MASK) >> |
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| 199 | OPENPIC_VENDOR_ID_STEPPING_SHIFT; |
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| 200 | |
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| 201 | /* Kludge for the Raven */ |
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| 202 | pci_read_config_dword(0, 0, 0, 0, &t); |
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| 203 | if (t == PCI_VENDOR_ID_MOTOROLA + (PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) { |
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| 204 | vendor = "Motorola"; |
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| 205 | device = "Raven"; |
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| 206 | NumSources += 1; |
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| 207 | } else { |
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| 208 | switch (vendorid) { |
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| 209 | case OPENPIC_VENDOR_ID_APPLE: |
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| 210 | vendor = "Apple"; |
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| 211 | break; |
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| 212 | default: |
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| 213 | vendor = "Unknown"; |
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| 214 | break; |
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| 215 | } |
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| 216 | switch (devid) { |
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| 217 | case OPENPIC_DEVICE_ID_APPLE_HYDRA: |
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| 218 | device = "Hydra"; |
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| 219 | break; |
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| 220 | default: |
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| 221 | device = "Unknown"; |
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| 222 | break; |
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| 223 | } |
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| 224 | } |
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| 225 | printk("OpenPIC Version %s (%d CPUs and %d IRQ sources) at %p\n", version, |
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| 226 | NumProcessors, NumSources, OpenPIC); |
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| 227 | |
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| 228 | printk("OpenPIC Vendor %d (%s), Device %d (%s), Stepping %d\n", vendorid, |
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| 229 | vendor, devid, device, stepping); |
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| 230 | |
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| 231 | timerfreq = openpic_read(&OpenPIC->Global.Timer_Frequency); |
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| 232 | printk("OpenPIC timer frequency is "); |
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| 233 | if (timerfreq) |
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| 234 | printk("%d Hz\n", timerfreq); |
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| 235 | else |
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| 236 | printk("not set\n"); |
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| 237 | |
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| 238 | if ( main_pic ) |
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| 239 | { |
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| 240 | /* Initialize timer interrupts */ |
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| 241 | for (i = 0; i < OPENPIC_NUM_TIMERS; i++) { |
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| 242 | /* Disabled, Priority 0 */ |
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| 243 | openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i); |
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| 244 | /* No processor */ |
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| 245 | openpic_maptimer(i, 0); |
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| 246 | } |
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| 247 | |
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| 248 | /* Initialize IPI interrupts */ |
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| 249 | for (i = 0; i < OPENPIC_NUM_IPI; i++) { |
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| 250 | /* Disabled, Priority 0 */ |
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| 251 | openpic_initipi(i, 0, OPENPIC_VEC_IPI+i); |
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| 252 | } |
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| 253 | |
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| 254 | /* Initialize external interrupts */ |
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[69ed59f] | 255 | for (i = 0; i < NumSources; i++) { |
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[acc25ee] | 256 | /* Enabled, Priority 8 */ |
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[69ed59f] | 257 | openpic_initirq(i, 8, OPENPIC_VEC_SOURCE+i, |
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| 258 | polarities ? polarities[i] : 0, |
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| 259 | senses ? senses[i] : 1); |
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[acc25ee] | 260 | /* Processor 0 */ |
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| 261 | openpic_mapirq(i, 1<<0); |
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| 262 | } |
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| 263 | |
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| 264 | /* Initialize the spurious interrupt */ |
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| 265 | openpic_set_spurious(OPENPIC_VEC_SPURIOUS); |
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| 266 | #if 0 |
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| 267 | if (request_irq(IRQ_8259_CASCADE, no_action, SA_INTERRUPT, |
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| 268 | "82c59 cascade", NULL)) |
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| 269 | printk("Unable to get OpenPIC IRQ 0 for cascade\n"); |
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| 270 | #endif |
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| 271 | openpic_set_priority(0, 0); |
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| 272 | openpic_disable_8259_pass_through(); |
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| 273 | } |
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| 274 | } |
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| 275 | |
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| 276 | |
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| 277 | /* |
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| 278 | * Reset the OpenPIC |
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| 279 | */ |
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| 280 | |
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| 281 | void openpic_reset(void) |
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| 282 | { |
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| 283 | openpic_setfield(&OpenPIC->Global.Global_Configuration0, |
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| 284 | OPENPIC_CONFIG_RESET); |
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| 285 | } |
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| 286 | |
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| 287 | |
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| 288 | /* |
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| 289 | * Enable/disable 8259 Pass Through Mode |
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| 290 | */ |
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| 291 | |
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| 292 | void openpic_enable_8259_pass_through(void) |
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| 293 | { |
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| 294 | openpic_clearfield(&OpenPIC->Global.Global_Configuration0, |
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| 295 | OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE); |
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| 296 | } |
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| 297 | |
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| 298 | void openpic_disable_8259_pass_through(void) |
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| 299 | { |
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| 300 | openpic_setfield(&OpenPIC->Global.Global_Configuration0, |
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| 301 | OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE); |
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| 302 | } |
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| 303 | |
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| 304 | |
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| 305 | /* |
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| 306 | * Find out the current interrupt |
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| 307 | */ |
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| 308 | |
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| 309 | unsigned int openpic_irq(unsigned int cpu) |
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| 310 | { |
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| 311 | unsigned int vec; |
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| 312 | |
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| 313 | check_arg_cpu(cpu); |
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| 314 | vec = openpic_readfield(&OpenPIC->THIS_CPU.Interrupt_Acknowledge, |
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| 315 | OPENPIC_VECTOR_MASK); |
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| 316 | return vec; |
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| 317 | } |
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| 318 | |
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| 319 | |
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| 320 | /* |
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| 321 | * Signal end of interrupt (EOI) processing |
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| 322 | */ |
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| 323 | |
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| 324 | void openpic_eoi(unsigned int cpu) |
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| 325 | { |
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| 326 | check_arg_cpu(cpu); |
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| 327 | openpic_write(&OpenPIC->THIS_CPU.EOI, 0); |
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| 328 | } |
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| 329 | |
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| 330 | |
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| 331 | /* |
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| 332 | * Get/set the current task priority |
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| 333 | */ |
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| 334 | |
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| 335 | unsigned int openpic_get_priority(unsigned int cpu) |
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| 336 | { |
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| 337 | CHECK_THIS_CPU; |
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| 338 | return openpic_readfield(&OpenPIC->THIS_CPU.Current_Task_Priority, |
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| 339 | OPENPIC_CURRENT_TASK_PRIORITY_MASK); |
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| 340 | } |
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| 341 | |
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| 342 | void openpic_set_priority(unsigned int cpu, unsigned int pri) |
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| 343 | { |
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| 344 | CHECK_THIS_CPU; |
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| 345 | check_arg_pri(pri); |
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| 346 | openpic_writefield(&OpenPIC->THIS_CPU.Current_Task_Priority, |
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| 347 | OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri); |
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| 348 | } |
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| 349 | |
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| 350 | /* |
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| 351 | * Get/set the spurious vector |
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| 352 | */ |
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| 353 | |
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| 354 | unsigned int openpic_get_spurious(void) |
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| 355 | { |
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| 356 | return openpic_readfield(&OpenPIC->Global.Spurious_Vector, |
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| 357 | OPENPIC_VECTOR_MASK); |
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| 358 | } |
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| 359 | |
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| 360 | void openpic_set_spurious(unsigned int vec) |
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| 361 | { |
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| 362 | check_arg_vec(vec); |
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| 363 | openpic_writefield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK, |
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| 364 | vec); |
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| 365 | } |
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| 366 | |
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| 367 | |
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| 368 | /* |
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| 369 | * Initialize one or more CPUs |
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| 370 | */ |
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| 371 | |
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| 372 | void openpic_init_processor(unsigned int cpumask) |
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| 373 | { |
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| 374 | openpic_write(&OpenPIC->Global.Processor_Initialization, cpumask); |
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| 375 | } |
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| 376 | |
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| 377 | |
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| 378 | /* -------- Interprocessor Interrupts -------------------------------------- */ |
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| 379 | |
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| 380 | |
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| 381 | /* |
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| 382 | * Initialize an interprocessor interrupt (and disable it) |
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| 383 | * |
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| 384 | * ipi: OpenPIC interprocessor interrupt number |
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| 385 | * pri: interrupt source priority |
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| 386 | * vec: the vector it will produce |
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| 387 | */ |
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| 388 | |
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| 389 | void openpic_initipi(unsigned int ipi, unsigned int pri, unsigned int vec) |
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| 390 | { |
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| 391 | check_arg_timer(ipi); |
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| 392 | check_arg_pri(pri); |
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| 393 | check_arg_vec(vec); |
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| 394 | openpic_safe_writefield(&OpenPIC->Global.IPI_Vector_Priority(ipi), |
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| 395 | OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK, |
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| 396 | (pri << OPENPIC_PRIORITY_SHIFT) | vec); |
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| 397 | } |
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| 398 | |
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| 399 | |
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| 400 | /* |
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| 401 | * Send an IPI to one or more CPUs |
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| 402 | */ |
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| 403 | |
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| 404 | void openpic_cause_IPI(unsigned int cpu, unsigned int ipi, unsigned int cpumask) |
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| 405 | { |
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| 406 | CHECK_THIS_CPU; |
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| 407 | check_arg_ipi(ipi); |
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| 408 | openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi), cpumask); |
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| 409 | } |
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| 410 | |
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| 411 | |
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| 412 | /* -------- Timer Interrupts ----------------------------------------------- */ |
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| 413 | |
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| 414 | |
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| 415 | /* |
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| 416 | * Initialize a timer interrupt (and disable it) |
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| 417 | * |
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| 418 | * timer: OpenPIC timer number |
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| 419 | * pri: interrupt source priority |
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| 420 | * vec: the vector it will produce |
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| 421 | */ |
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| 422 | |
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| 423 | void openpic_inittimer(unsigned int timer, unsigned int pri, unsigned int vec) |
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| 424 | { |
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| 425 | check_arg_timer(timer); |
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| 426 | check_arg_pri(pri); |
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| 427 | check_arg_vec(vec); |
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| 428 | openpic_safe_writefield(&OpenPIC->Global.Timer[timer].Vector_Priority, |
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| 429 | OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK, |
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| 430 | (pri << OPENPIC_PRIORITY_SHIFT) | vec); |
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| 431 | } |
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| 432 | |
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| 433 | |
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| 434 | /* |
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| 435 | * Map a timer interrupt to one or more CPUs |
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| 436 | */ |
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| 437 | |
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| 438 | void openpic_maptimer(unsigned int timer, unsigned int cpumask) |
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| 439 | { |
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| 440 | check_arg_timer(timer); |
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| 441 | openpic_write(&OpenPIC->Global.Timer[timer].Destination, cpumask); |
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| 442 | } |
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| 443 | |
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| 444 | |
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| 445 | /* -------- Interrupt Sources ---------------------------------------------- */ |
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| 446 | |
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| 447 | |
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| 448 | /* |
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| 449 | * Enable/disable an interrupt source |
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| 450 | */ |
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| 451 | |
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| 452 | void openpic_enable_irq(unsigned int irq) |
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| 453 | { |
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[2742cc3] | 454 | unsigned long flags; |
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[acc25ee] | 455 | check_arg_irq(irq); |
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[2742cc3] | 456 | rtems_interrupt_disable(flags); |
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[acc25ee] | 457 | openpic_clearfield(&OpenPIC->Source[irq].Vector_Priority, OPENPIC_MASK); |
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[2742cc3] | 458 | rtems_interrupt_enable(flags); |
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[acc25ee] | 459 | } |
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| 460 | |
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| 461 | void openpic_disable_irq(unsigned int irq) |
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| 462 | { |
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[2742cc3] | 463 | unsigned long flags; |
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[acc25ee] | 464 | check_arg_irq(irq); |
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[2742cc3] | 465 | rtems_interrupt_disable(flags); |
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[acc25ee] | 466 | openpic_setfield(&OpenPIC->Source[irq].Vector_Priority, OPENPIC_MASK); |
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[2742cc3] | 467 | rtems_interrupt_enable(flags); |
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[acc25ee] | 468 | } |
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| 469 | |
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| 470 | |
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| 471 | /* |
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| 472 | * Initialize an interrupt source (and disable it!) |
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| 473 | * |
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| 474 | * irq: OpenPIC interrupt number |
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| 475 | * pri: interrupt source priority |
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| 476 | * vec: the vector it will produce |
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| 477 | * pol: polarity (1 for positive, 0 for negative) |
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| 478 | * sense: 1 for level, 0 for edge |
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| 479 | */ |
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| 480 | |
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| 481 | void openpic_initirq(unsigned int irq, unsigned int pri, unsigned int vec, int pol, int sense) |
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| 482 | { |
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| 483 | check_arg_irq(irq); |
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| 484 | check_arg_pri(pri); |
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| 485 | check_arg_vec(vec); |
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| 486 | openpic_safe_writefield(&OpenPIC->Source[irq].Vector_Priority, |
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| 487 | OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK | |
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| 488 | OPENPIC_SENSE_POLARITY | OPENPIC_SENSE_LEVEL, |
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| 489 | (pri << OPENPIC_PRIORITY_SHIFT) | vec | |
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| 490 | (pol ? OPENPIC_SENSE_POLARITY : 0) | |
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| 491 | (sense ? OPENPIC_SENSE_LEVEL : 0)); |
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| 492 | } |
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| 493 | |
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| 494 | |
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| 495 | /* |
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| 496 | * Map an interrupt source to one or more CPUs |
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| 497 | */ |
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| 498 | |
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| 499 | void openpic_mapirq(unsigned int irq, unsigned int cpumask) |
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| 500 | { |
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| 501 | check_arg_irq(irq); |
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| 502 | openpic_write(&OpenPIC->Source[irq].Destination, cpumask); |
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| 503 | } |
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| 504 | |
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[2742cc3] | 505 | /* |
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| 506 | * Get the current priority of an external interrupt |
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| 507 | */ |
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| 508 | unsigned int openpic_get_source_priority(unsigned int irq) |
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| 509 | { |
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| 510 | check_arg_irq(irq); |
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| 511 | return openpic_readfield(&OpenPIC->Source[irq].Vector_Priority, |
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| 512 | OPENPIC_PRIORITY_MASK) >> OPENPIC_PRIORITY_SHIFT; |
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| 513 | } |
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[acc25ee] | 514 | |
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[2742cc3] | 515 | void openpic_set_source_priority(unsigned int irq, unsigned int pri) |
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| 516 | { |
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| 517 | unsigned long flags; |
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| 518 | check_arg_irq(irq); |
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| 519 | check_arg_pri(pri); |
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| 520 | rtems_interrupt_disable(flags); |
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| 521 | openpic_writefield( |
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| 522 | &OpenPIC->Source[irq].Vector_Priority, |
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| 523 | OPENPIC_PRIORITY_MASK, |
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| 524 | pri << OPENPIC_PRIORITY_SHIFT); |
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| 525 | rtems_interrupt_enable(flags); |
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| 526 | } |
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[acc25ee] | 527 | /* |
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| 528 | * Set the sense for an interrupt source (and disable it!) |
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| 529 | * |
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| 530 | * sense: 1 for level, 0 for edge |
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| 531 | */ |
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| 532 | |
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| 533 | void openpic_set_sense(unsigned int irq, int sense) |
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| 534 | { |
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| 535 | check_arg_irq(irq); |
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| 536 | openpic_safe_writefield(&OpenPIC->Source[irq].Vector_Priority, |
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| 537 | OPENPIC_SENSE_LEVEL, |
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| 538 | (sense ? OPENPIC_SENSE_LEVEL : 0)); |
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| 539 | } |
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