1 | /* |
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2 | * |
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3 | * This file contains the i8259/openpic-specific implementation of the function described in irq.h |
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4 | * |
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5 | * Copyright (C) 1998, 1999 valette@crf.canon.fr |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in found in the file LICENSE in this distribution or at |
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9 | * http://www.rtems.com/license/LICENSE. |
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10 | * |
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11 | * $Id$ |
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12 | */ |
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13 | |
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14 | #include <stdlib.h> |
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15 | |
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16 | #include <bsp.h> |
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17 | #include <bsp/irq.h> |
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18 | #include <bsp/VMEConfig.h> |
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19 | #include <bsp/openpic.h> |
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20 | #include <libcpu/raw_exception.h> |
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21 | #include <libcpu/io.h> |
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22 | #include <bsp/vectors.h> |
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23 | #include <stdlib.h> |
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24 | |
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25 | #include <rtems/bspIo.h> /* for printk */ |
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26 | #define RAVEN_INTR_ACK_REG 0xfeff0030 |
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27 | |
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28 | /* |
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29 | * pointer to the mask representing the additionnal irq vectors |
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30 | * that must be disabled when a particular entry is activated. |
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31 | * They will be dynamically computed from the priority table given |
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32 | * in BSP_rtems_irq_mngt_set(); |
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33 | * CAUTION : this table is accessed directly by interrupt routine |
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34 | * prologue. |
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35 | */ |
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36 | rtems_i8259_masks irq_mask_or_tbl[BSP_IRQ_NUMBER]; |
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37 | |
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38 | /* |
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39 | * default handler connected on each irq after bsp initialization |
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40 | */ |
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41 | static rtems_irq_connect_data default_rtems_entry; |
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42 | |
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43 | static rtems_irq_connect_data* rtems_hdl_tbl; |
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44 | |
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45 | #ifdef BSP_PCI_ISA_BRIDGE_IRQ |
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46 | /* |
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47 | * Check if IRQ is an ISA IRQ |
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48 | */ |
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49 | static inline int is_isa_irq(const rtems_irq_number irqLine) |
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50 | { |
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51 | return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) & |
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52 | ((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET) |
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53 | ); |
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54 | } |
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55 | #endif |
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56 | |
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57 | /* |
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58 | * Check if IRQ is an OPENPIC IRQ |
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59 | */ |
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60 | static inline int is_pci_irq(const rtems_irq_number irqLine) |
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61 | { |
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62 | return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) & |
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63 | ((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET) |
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64 | ); |
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65 | } |
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66 | |
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67 | /* |
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68 | * ------------------------ RTEMS Irq helper functions ---------------- |
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69 | */ |
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70 | |
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71 | #ifdef BSP_PCI_ISA_BRIDGE_IRQ |
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72 | /* |
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73 | * Caution : this function assumes the variable "*config" |
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74 | * is already set and that the tables it contains are still valid |
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75 | * and accessible. |
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76 | */ |
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77 | static void compute_i8259_masks_from_prio (rtems_irq_global_settings* config) |
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78 | { |
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79 | int i; |
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80 | int j; |
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81 | /* |
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82 | * Always mask at least current interrupt to prevent re-entrance |
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83 | */ |
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84 | for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) { |
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85 | * ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i); |
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86 | for (j = BSP_ISA_IRQ_LOWEST_OFFSET; j < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; j++) { |
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87 | /* |
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88 | * Mask interrupts at i8259 level that have a lower priority |
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89 | */ |
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90 | if (config->irqPrioTbl [i] > config->irqPrioTbl [j]) { |
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91 | * ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j); |
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92 | } |
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93 | } |
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94 | } |
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95 | } |
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96 | #endif |
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97 | |
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98 | void |
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99 | BSP_enable_irq_at_pic(const rtems_irq_number name) |
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100 | { |
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101 | #ifdef BSP_PCI_ISA_BRIDGE_IRQ |
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102 | if (is_isa_irq(name)) { |
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103 | /* |
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104 | * Enable interrupt at PIC level |
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105 | */ |
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106 | BSP_irq_enable_at_i8259s ((int) name - BSP_ISA_IRQ_LOWEST_OFFSET); |
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107 | } |
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108 | #endif |
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109 | |
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110 | if (is_pci_irq(name)) { |
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111 | /* |
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112 | * Enable interrupt at OPENPIC level |
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113 | */ |
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114 | openpic_enable_irq ((int) name - BSP_PCI_IRQ_LOWEST_OFFSET); |
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115 | } |
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116 | } |
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117 | |
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118 | void |
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119 | BSP_disable_irq_at_pic(const rtems_irq_number name) |
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120 | { |
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121 | #ifdef BSP_PCI_ISA_BRIDGE_IRQ |
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122 | if (is_isa_irq(name)) { |
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123 | /* |
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124 | * disable interrupt at PIC level |
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125 | */ |
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126 | BSP_irq_disable_at_i8259s ((int) name - BSP_ISA_IRQ_LOWEST_OFFSET); |
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127 | } |
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128 | #endif |
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129 | if (is_pci_irq(name)) { |
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130 | /* |
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131 | * disable interrupt at OPENPIC level |
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132 | */ |
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133 | openpic_disable_irq ((int) name - BSP_PCI_IRQ_LOWEST_OFFSET); |
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134 | } |
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135 | } |
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136 | |
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137 | /* |
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138 | * RTEMS Global Interrupt Handler Management Routines |
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139 | */ |
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140 | int BSP_setup_the_pic(rtems_irq_global_settings* config) |
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141 | { |
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142 | int i; |
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143 | /* |
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144 | * Store various code accelerators |
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145 | */ |
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146 | default_rtems_entry = config->defaultEntry; |
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147 | rtems_hdl_tbl = config->irqHdlTbl; |
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148 | |
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149 | /* |
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150 | * set up internal tables used by rtems interrupt prologue |
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151 | */ |
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152 | |
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153 | #ifdef BSP_PCI_ISA_BRIDGE_IRQ |
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154 | /* |
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155 | * start with ISA IRQ |
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156 | */ |
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157 | compute_i8259_masks_from_prio (config); |
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158 | |
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159 | for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) { |
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160 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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161 | BSP_irq_enable_at_i8259s (i); |
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162 | } |
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163 | else { |
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164 | BSP_irq_disable_at_i8259s (i); |
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165 | } |
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166 | } |
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167 | |
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168 | if ( BSP_ISA_IRQ_NUMBER > 0 ) { |
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169 | /* |
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170 | * must enable slave pic anyway |
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171 | */ |
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172 | BSP_irq_enable_at_i8259s (2); |
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173 | } |
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174 | #endif |
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175 | |
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176 | /* |
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177 | * continue with PCI IRQ |
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178 | */ |
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179 | for (i=BSP_PCI_IRQ_LOWEST_OFFSET; i < BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER ; i++) { |
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180 | /* |
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181 | * Note that openpic_set_priority() sets the TASK priority of the PIC |
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182 | */ |
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183 | openpic_set_source_priority(i - BSP_PCI_IRQ_LOWEST_OFFSET, |
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184 | config->irqPrioTbl[i]); |
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185 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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186 | openpic_enable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET); |
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187 | } |
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188 | else { |
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189 | openpic_disable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET); |
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190 | } |
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191 | } |
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192 | |
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193 | #ifdef BSP_PCI_ISA_BRIDGE_IRQ |
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194 | if ( BSP_ISA_IRQ_NUMBER > 0 ) { |
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195 | /* |
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196 | * Must enable PCI/ISA bridge IRQ |
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197 | */ |
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198 | openpic_enable_irq (0); |
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199 | } |
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200 | #endif |
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201 | |
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202 | return 1; |
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203 | } |
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204 | |
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205 | int _BSP_vme_bridge_irq = -1; |
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206 | |
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207 | unsigned BSP_spuriousIntr = 0; |
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208 | /* |
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209 | * High level IRQ handler called from shared_raw_irq_code_entry |
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210 | */ |
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211 | void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) |
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212 | { |
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213 | register unsigned int irq; |
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214 | #ifdef BSP_PCI_ISA_BRIDGE_IRQ |
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215 | register unsigned isaIntr; /* boolean */ |
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216 | register unsigned oldMask = 0; /* old isa pic masks */ |
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217 | register unsigned newMask; /* new isa pic masks */ |
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218 | #endif |
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219 | register unsigned msr; |
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220 | register unsigned new_msr; |
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221 | |
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222 | if (excNum == ASM_DEC_VECTOR) { |
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223 | _CPU_MSR_GET(msr); |
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224 | new_msr = msr | MSR_EE; |
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225 | _CPU_MSR_SET(new_msr); |
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226 | |
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227 | rtems_hdl_tbl[BSP_DECREMENTER].hdl(rtems_hdl_tbl[BSP_DECREMENTER].handle); |
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228 | |
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229 | _CPU_MSR_SET(msr); |
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230 | return; |
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231 | |
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232 | } |
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233 | irq = openpic_irq(0); |
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234 | if (irq == OPENPIC_VEC_SPURIOUS) { |
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235 | ++BSP_spuriousIntr; |
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236 | return; |
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237 | } |
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238 | |
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239 | /* some BSPs might want to use a different numbering... */ |
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240 | irq = irq - OPENPIC_VEC_SOURCE + BSP_PCI_IRQ_LOWEST_OFFSET; |
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241 | |
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242 | #ifdef BSP_PCI_ISA_BRIDGE_IRQ |
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243 | isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ); |
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244 | if (isaIntr) { |
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245 | /* |
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246 | * Acknowledge and read 8259 vector |
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247 | */ |
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248 | irq = (unsigned int) (*(unsigned char *) RAVEN_INTR_ACK_REG); |
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249 | /* |
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250 | * store current PIC mask |
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251 | */ |
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252 | oldMask = i8259s_cache; |
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253 | newMask = oldMask | irq_mask_or_tbl [irq]; |
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254 | i8259s_cache = newMask; |
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255 | outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); |
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256 | outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); |
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257 | BSP_irq_ack_at_i8259s (irq); |
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258 | openpic_eoi(0); |
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259 | } |
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260 | #endif |
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261 | _CPU_MSR_GET(msr); |
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262 | new_msr = msr | MSR_EE; |
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263 | _CPU_MSR_SET(new_msr); |
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264 | |
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265 | /* rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle); */ |
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266 | { |
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267 | rtems_irq_connect_data* vchain; |
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268 | for( vchain = &rtems_hdl_tbl[irq]; |
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269 | ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); |
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270 | vchain = (rtems_irq_connect_data*)vchain->next_handler ) |
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271 | { |
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272 | vchain->hdl(vchain->handle); |
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273 | } |
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274 | } |
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275 | |
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276 | _CPU_MSR_SET(msr); |
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277 | |
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278 | #ifdef BSP_PCI_ISA_BRIDGE_IRQ |
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279 | if (isaIntr) { |
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280 | i8259s_cache = oldMask; |
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281 | outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); |
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282 | outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); |
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283 | } |
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284 | else |
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285 | #endif |
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286 | { |
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287 | #ifdef BSP_PCI_VME_DRIVER_DOES_EOI |
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288 | /* leave it to the VME bridge driver to do EOI, so |
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289 | * it can re-enable the openpic while handling |
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290 | * VME interrupts (-> VME priorities in software) |
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291 | */ |
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292 | if (_BSP_vme_bridge_irq != irq) |
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293 | #endif |
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294 | openpic_eoi(0); |
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295 | } |
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296 | } |
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