source: rtems/c/src/lib/libbsp/powerpc/shared/irq/openpic_i8259_irq.c @ 98afe31

4.104.114.84.9
Last change on this file since 98afe31 was 8c9fffd, checked in by Till Straumann <strauman@…>, on Nov 4, 2005 at 1:39:45 AM

2005-11-03 <strauman@…>

  • shared/irq/openpic_i8259_irq.c: New file.
  • ChangeLog?, Makefile.am, motorola_powerpc/ChangeLog, motorola_powerpc/Makefile.am, shared/irq/irq.c, shared/irq/irq.h, shared/irq/irq_asm.S, shared/irq/irq_init.c: Separated openpic/i8259 specifica from generic irq handling into openpic_i8259_irq.c; added some compilation conditionals to help BSPs without ISA to omit ISA interrupts and calling i8259 code.
  • Property mode set to 100644
File size: 7.3 KB
Line 
1/*
2 *
3 *  This file contains the i8259/openpic-specific implementation of the function described in irq.h
4 *
5 *  Copyright (C) 1998, 1999 valette@crf.canon.fr
6 *
7 *  The license and distribution terms for this file may be
8 *  found in found in the file LICENSE in this distribution or at
9 *  http://www.rtems.com/license/LICENSE.
10 *
11 *  $Id$
12 */
13
14#include <stdlib.h>
15
16#include <bsp.h>
17#include <bsp/irq.h>
18#include <bsp/VMEConfig.h>
19#include <bsp/openpic.h>
20#include <libcpu/raw_exception.h>
21#include <libcpu/io.h>
22#include <bsp/vectors.h>
23#include <stdlib.h>
24
25#include <rtems/bspIo.h> /* for printk */
26#define RAVEN_INTR_ACK_REG 0xfeff0030
27
28/*
29 * pointer to the mask representing the additionnal irq vectors
30 * that must be disabled when a particular entry is activated.
31 * They will be dynamically computed from the priority table given
32 * in BSP_rtems_irq_mngt_set();
33 * CAUTION : this table is accessed directly by interrupt routine
34 *           prologue.
35 */
36rtems_i8259_masks       irq_mask_or_tbl[BSP_IRQ_NUMBER];
37
38/*
39 * default handler connected on each irq after bsp initialization
40 */
41static rtems_irq_connect_data   default_rtems_entry;
42
43static rtems_irq_connect_data*          rtems_hdl_tbl;
44
45#ifdef BSP_PCI_ISA_BRIDGE_IRQ
46/*
47 * Check if IRQ is an ISA IRQ
48 */
49static inline int is_isa_irq(const rtems_irq_number irqLine)
50{
51  return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) &
52          ((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET)
53         );
54}
55#endif
56
57/*
58 * Check if IRQ is an OPENPIC IRQ
59 */
60static inline int is_pci_irq(const rtems_irq_number irqLine)
61{
62  return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) &
63          ((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET)
64         );
65}
66
67/*
68 * ------------------------ RTEMS Irq helper functions ----------------
69 */
70
71#ifdef BSP_PCI_ISA_BRIDGE_IRQ
72/*
73 * Caution : this function assumes the variable "*config"
74 * is already set and that the tables it contains are still valid
75 * and accessible.
76 */
77static void compute_i8259_masks_from_prio (rtems_irq_global_settings* config)
78{
79  int i;
80  int j;
81  /*
82   * Always mask at least current interrupt to prevent re-entrance
83   */
84  for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
85    * ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i);
86    for (j = BSP_ISA_IRQ_LOWEST_OFFSET; j < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; j++) {
87      /*
88       * Mask interrupts at i8259 level that have a lower priority
89       */
90      if (config->irqPrioTbl [i] > config->irqPrioTbl [j]) {
91        * ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j);
92      }
93    }
94  }
95}
96#endif
97
98void
99BSP_enable_irq_at_pic(const rtems_irq_number name)
100{
101#ifdef BSP_PCI_ISA_BRIDGE_IRQ
102    if (is_isa_irq(name)) {
103      /*
104       * Enable interrupt at PIC level
105       */
106      BSP_irq_enable_at_i8259s ((int) name - BSP_ISA_IRQ_LOWEST_OFFSET);
107    }
108#endif
109   
110    if (is_pci_irq(name)) {
111      /*
112       * Enable interrupt at OPENPIC level
113       */
114      openpic_enable_irq ((int) name - BSP_PCI_IRQ_LOWEST_OFFSET);
115    }
116}
117
118void
119BSP_disable_irq_at_pic(const rtems_irq_number name)
120{
121#ifdef BSP_PCI_ISA_BRIDGE_IRQ
122    if (is_isa_irq(name)) {
123      /*
124       * disable interrupt at PIC level
125       */
126      BSP_irq_disable_at_i8259s ((int) name - BSP_ISA_IRQ_LOWEST_OFFSET);
127    }
128#endif
129    if (is_pci_irq(name)) {
130      /*
131       * disable interrupt at OPENPIC level
132       */
133      openpic_disable_irq ((int) name - BSP_PCI_IRQ_LOWEST_OFFSET);
134    }
135}
136
137/*
138 * RTEMS Global Interrupt Handler Management Routines
139 */
140int BSP_setup_the_pic(rtems_irq_global_settings* config)
141{
142    int i;
143   /*
144    * Store various code accelerators
145    */
146    default_rtems_entry = config->defaultEntry;
147    rtems_hdl_tbl               = config->irqHdlTbl;
148
149    /*
150     * set up internal tables used by rtems interrupt prologue
151     */
152
153#ifdef BSP_PCI_ISA_BRIDGE_IRQ
154    /*
155     * start with ISA IRQ
156     */
157    compute_i8259_masks_from_prio (config);
158
159    for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
160      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
161         BSP_irq_enable_at_i8259s (i);
162      }
163      else {
164         BSP_irq_disable_at_i8259s (i);
165      }
166    }
167
168        if ( BSP_ISA_IRQ_NUMBER > 0 ) {
169        /*
170                 * must enable slave pic anyway
171                 */
172                BSP_irq_enable_at_i8259s (2);
173        }
174#endif
175
176    /*
177     * continue with PCI IRQ
178     */
179    for (i=BSP_PCI_IRQ_LOWEST_OFFSET; i < BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER ; i++) {
180      /*
181       * Note that openpic_set_priority() sets the TASK priority of the PIC
182       */
183      openpic_set_source_priority(i - BSP_PCI_IRQ_LOWEST_OFFSET,
184                                  config->irqPrioTbl[i]);
185      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
186         openpic_enable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET);
187      }
188      else {
189         openpic_disable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET);
190      }
191    }
192
193#ifdef BSP_PCI_ISA_BRIDGE_IRQ
194        if ( BSP_ISA_IRQ_NUMBER > 0 ) {
195        /*
196             * Must enable PCI/ISA bridge IRQ
197             */
198        openpic_enable_irq (0);
199        }
200#endif
201
202    return 1;
203}
204
205int _BSP_vme_bridge_irq = -1;
206
207unsigned BSP_spuriousIntr = 0;
208/*
209 * High level IRQ handler called from shared_raw_irq_code_entry
210 */
211void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
212{
213  register unsigned int irq;
214#ifdef BSP_PCI_ISA_BRIDGE_IRQ
215  register unsigned isaIntr;                  /* boolean */
216  register unsigned oldMask = 0;              /* old isa pic masks */
217  register unsigned newMask;                  /* new isa pic masks */
218#endif
219  register unsigned msr;
220  register unsigned new_msr;
221
222  if (excNum == ASM_DEC_VECTOR) {
223    _CPU_MSR_GET(msr);
224    new_msr = msr | MSR_EE;
225    _CPU_MSR_SET(new_msr);
226
227    rtems_hdl_tbl[BSP_DECREMENTER].hdl(rtems_hdl_tbl[BSP_DECREMENTER].handle);
228
229    _CPU_MSR_SET(msr);
230    return;
231
232  }
233  irq = openpic_irq(0);
234  if (irq == OPENPIC_VEC_SPURIOUS) {
235    ++BSP_spuriousIntr;
236    return;
237  }
238
239  /* some BSPs might want to use a different numbering... */
240  irq = irq - OPENPIC_VEC_SOURCE + BSP_PCI_IRQ_LOWEST_OFFSET;
241
242#ifdef BSP_PCI_ISA_BRIDGE_IRQ
243  isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ);
244  if (isaIntr)  {
245    /*
246     * Acknowledge and read 8259 vector
247     */
248    irq = (unsigned int) (*(unsigned char *) RAVEN_INTR_ACK_REG);
249    /*
250     * store current PIC mask
251     */
252    oldMask = i8259s_cache;
253    newMask = oldMask | irq_mask_or_tbl [irq];
254    i8259s_cache = newMask;
255    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
256    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
257    BSP_irq_ack_at_i8259s (irq);
258    openpic_eoi(0);
259  }
260#endif
261  _CPU_MSR_GET(msr);
262  new_msr = msr | MSR_EE;
263  _CPU_MSR_SET(new_msr);
264
265  /* rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle); */
266  {
267     rtems_irq_connect_data* vchain;
268     for( vchain = &rtems_hdl_tbl[irq];
269          ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
270          vchain = (rtems_irq_connect_data*)vchain->next_handler )
271     {
272        vchain->hdl(vchain->handle);
273     }
274  }
275
276  _CPU_MSR_SET(msr);
277
278#ifdef BSP_PCI_ISA_BRIDGE_IRQ
279  if (isaIntr)  {
280    i8259s_cache = oldMask;
281    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
282    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
283  }
284  else
285#endif
286  {
287#ifdef BSP_PCI_VME_DRIVER_DOES_EOI
288        /* leave it to the VME bridge driver to do EOI, so
289     * it can re-enable the openpic while handling
290     * VME interrupts (-> VME priorities in software)
291         */
292        if (_BSP_vme_bridge_irq != irq)
293#endif
294                openpic_eoi(0);
295  }
296}
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