1 | /* irq_init.c |
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2 | * |
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3 | * This file contains the implementation of rtems initialization |
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4 | * related to interrupt handling. |
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5 | * |
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6 | * CopyRight (C) 1999 valette@crf.canon.fr |
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7 | * |
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8 | * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com> |
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9 | * to make it valid for MVME2300 Motorola boards. |
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10 | * |
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11 | * Till Straumann <strauman@slac.stanford.edu>, 12/20/2001: |
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12 | * Use the new interface to openpic_init |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in the file LICENSE in this distribution or at |
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16 | * http://www.rtems.com/license/LICENSE. |
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17 | */ |
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18 | |
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19 | #include <libcpu/io.h> |
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20 | #include <libcpu/spr.h> |
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21 | #include <bsp/pci.h> |
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22 | #include <bsp/residual.h> |
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23 | #include <bsp/irq.h> |
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24 | #if BSP_PCI_IRQ_NUMBER > 0 |
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25 | #include <bsp/openpic.h> |
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26 | #endif |
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27 | #include <bsp/irq_supp.h> |
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28 | #include <bsp.h> |
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29 | #include <bsp/motorola.h> |
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30 | #include <rtems/bspIo.h> |
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31 | |
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32 | typedef struct { |
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33 | unsigned char bus; /* few chance the PCI/ISA bridge is not on first bus but ... */ |
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34 | unsigned char device; |
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35 | unsigned char function; |
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36 | } pci_isa_bridge_device; |
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37 | |
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38 | pci_isa_bridge_device* via_82c586 = 0; |
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39 | #ifndef qemu |
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40 | static pci_isa_bridge_device bridge; |
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41 | #endif |
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42 | |
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43 | /* |
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44 | * default methods |
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45 | */ |
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46 | static void nop_hdl(rtems_irq_hdl_param ignored) |
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47 | { |
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48 | } |
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49 | |
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50 | static void nop_irq_enable(const struct __rtems_irq_connect_data__*ignored) |
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51 | { |
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52 | } |
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53 | |
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54 | static int irq_is_connected(const struct __rtems_irq_connect_data__*ignored) |
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55 | { |
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56 | return 0; |
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57 | } |
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58 | |
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59 | |
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60 | static rtems_irq_connect_data rtemsIrq[BSP_IRQ_NUMBER]; |
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61 | static rtems_irq_global_settings initial_config; |
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62 | static rtems_irq_connect_data defaultIrq = { |
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63 | 0, /* vector */ |
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64 | nop_hdl, /* hdl */ |
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65 | NULL, /* handle */ |
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66 | nop_irq_enable, /* on */ |
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67 | nop_irq_enable, /* off */ |
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68 | irq_is_connected /* isOn */ |
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69 | #ifdef BSP_SHARED_HANDLER_SUPPORT |
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70 | , NULL /* next_handler */ |
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71 | #endif |
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72 | }; |
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73 | static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={ |
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74 | /* |
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75 | * actual priorities for interrupt : |
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76 | * 0 means that only current interrupt is masked |
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77 | * 255 means all other interrupts are masked |
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78 | */ |
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79 | /* |
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80 | * ISA interrupts. |
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81 | * The second entry has a priority of 255 because |
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82 | * it is the slave pic entry and should always remain |
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83 | * unmasked. |
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84 | */ |
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85 | 0,0, |
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86 | 255, |
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87 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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88 | #if BSP_PCI_IRQ_NUMBER > 0 |
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89 | /* |
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90 | * PCI Interrupts |
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91 | */ |
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92 | 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, /* for raven prio 0 means unactive... */ |
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93 | #endif |
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94 | /* |
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95 | * Processor exceptions handled as interrupts |
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96 | */ |
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97 | 0 |
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98 | }; |
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99 | |
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100 | #if BSP_PCI_IRQ_NUMBER > 0 |
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101 | #if defined(mvme2100) |
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102 | static unsigned char mvme2100_openpic_initpolarities[16] = { |
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103 | 0, /* Not used - should be disabled */ |
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104 | 0, /* DEC21143 Controller */ |
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105 | 0, /* PMC/PC-MIP Type I Slot 0 */ |
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106 | 0, /* PC-MIP Type I Slot 1 */ |
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107 | 0, /* PC-MIP Type II Slot 0 */ |
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108 | 0, /* PC-MIP Type II Slot 1 */ |
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109 | 0, /* Not used - should be disabled */ |
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110 | 0, /* PCI Expansion Interrupt A/Universe II (LINT0) */ |
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111 | 0, /* PCI Expansion Interrupt B/Universe II (LINT1) */ |
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112 | 0, /* PCI Expansion Interrupt C/Universe II (LINT2) */ |
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113 | 0, /* PCI Expansion Interrupt D/Universe II (LINT3) */ |
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114 | 0, /* Not used - should be disabled */ |
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115 | 0, /* Not used - should be disabled */ |
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116 | 1, /* 16550 UART */ |
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117 | 0, /* Front panel Abort Switch */ |
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118 | 0, /* RTC IRQ */ |
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119 | }; |
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120 | |
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121 | static unsigned char mvme2100_openpic_initsenses[] = { |
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122 | 0, /* Not used - should be disabled */ |
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123 | 1, /* DEC21143 Controller */ |
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124 | 1, /* PMC/PC-MIP Type I Slot 0 */ |
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125 | 1, /* PC-MIP Type I Slot 1 */ |
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126 | 1, /* PC-MIP Type II Slot 0 */ |
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127 | 1, /* PC-MIP Type II Slot 1 */ |
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128 | 0, /* Not used - should be disabled */ |
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129 | 1, /* PCI Expansion Interrupt A/Universe II (LINT0) */ |
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130 | 1, /* PCI Expansion Interrupt B/Universe II (LINT1) */ |
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131 | 1, /* PCI Expansion Interrupt C/Universe II (LINT2) */ |
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132 | 1, /* PCI Expansion Interrupt D/Universe II (LINT3) */ |
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133 | 0, /* Not used - should be disabled */ |
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134 | 0, /* Not used - should be disabled */ |
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135 | 1, /* 16550 UART */ |
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136 | 0, /* Front panel Abort Switch */ |
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137 | 1, /* RTC IRQ */ |
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138 | }; |
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139 | #else |
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140 | static unsigned char mcp750_openpic_initpolarities[16] = { |
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141 | 1, /* 8259 cascade */ |
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142 | 0, /* all the rest of them */ |
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143 | }; |
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144 | |
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145 | static unsigned char mcp750_openpic_initsenses[] = { |
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146 | 1, /* MCP750_INT_PCB(8259) */ |
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147 | 0, /* MCP750_INT_FALCON_ECC_ERR */ |
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148 | 1, /* MCP750_INT_PCI_ETHERNET */ |
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149 | 1, /* MCP750_INT_PCI_PMC */ |
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150 | 1, /* MCP750_INT_PCI_WATCHDOG_TIMER1 */ |
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151 | 1, /* MCP750_INT_PCI_PRST_SIGNAL */ |
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152 | 1, /* MCP750_INT_PCI_FALL_SIGNAL */ |
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153 | 1, /* MCP750_INT_PCI_DEG_SIGNAL */ |
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154 | 1, /* MCP750_INT_PCI_BUS1_INTA */ |
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155 | 1, /* MCP750_INT_PCI_BUS1_INTB */ |
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156 | 1, /* MCP750_INT_PCI_BUS1_INTC */ |
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157 | 1, /* MCP750_INT_PCI_BUS1_INTD */ |
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158 | 1, /* MCP750_INT_PCI_BUS2_INTA */ |
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159 | 1, /* MCP750_INT_PCI_BUS2_INTB */ |
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160 | 1, /* MCP750_INT_PCI_BUS2_INTC */ |
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161 | 1, /* MCP750_INT_PCI_BUS2_INTD */ |
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162 | }; |
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163 | #endif |
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164 | #endif |
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165 | |
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166 | #if BSP_ISA_IRQ_NUMBER > 0 && !defined(qemu) |
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167 | void VIA_isa_bridge_interrupts_setup(void) |
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168 | { |
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169 | pci_isa_bridge_device pci_dev; |
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170 | uint32_t temp; |
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171 | unsigned char tmp; |
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172 | unsigned char maxBus; |
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173 | unsigned found = 0; |
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174 | |
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175 | maxBus = pci_bus_count(); |
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176 | pci_dev.function = 0; /* Assumes the bidge is the first function */ |
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177 | |
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178 | for (pci_dev.bus = 0; pci_dev.bus < maxBus; pci_dev.bus++) { |
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179 | #ifdef SCAN_PCI_PRINT |
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180 | printk("isa_bridge_interrupts_setup: Scanning bus %d\n", pci_dev.bus); |
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181 | #endif |
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182 | for (pci_dev.device = 0; pci_dev.device < PCI_MAX_DEVICES; pci_dev.device++) { |
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183 | #ifdef SCAN_PCI_PRINT |
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184 | printk("isa_bridge_interrupts_setup: Scanning device %d\n", pci_dev.device); |
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185 | #endif |
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186 | pci_read_config_dword(pci_dev.bus, pci_dev.device, pci_dev.function, |
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187 | PCI_VENDOR_ID, &temp); |
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188 | #ifdef SCAN_PCI_PRINT |
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189 | printk("Vendor/device = %x\n", temp); |
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190 | #endif |
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191 | if ((temp == (((unsigned short) PCI_VENDOR_ID_VIA) | (PCI_DEVICE_ID_VIA_82C586_0 << 16))) |
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192 | ) { |
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193 | bridge = pci_dev; |
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194 | via_82c586 = &bridge; |
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195 | #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS |
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196 | /* |
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197 | * Should print : bus = 0, device = 11, function = 0 on a MCP750. |
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198 | */ |
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199 | printk("Via PCI/ISA bridge found at bus = %d, device = %d, function = %d\n", |
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200 | via_82c586->bus, |
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201 | via_82c586->device, |
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202 | via_82c586->function); |
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203 | #endif |
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204 | found = 1; |
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205 | goto loop_exit; |
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206 | |
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207 | } |
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208 | } |
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209 | } |
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210 | loop_exit: |
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211 | if (!found) BSP_panic("VIA_82C586 PCI/ISA bridge not found!n"); |
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212 | |
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213 | tmp = inb(0x810); |
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214 | if ( !(tmp & 0x2)) { |
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215 | #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS |
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216 | printk("This is a second generation MCP750 board\n"); |
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217 | printk("We must reprogram the PCI/ISA bridge...\n"); |
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218 | #endif |
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219 | pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function, |
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220 | 0x47, &tmp); |
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221 | #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS |
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222 | printk(" PCI ISA bridge control2 = %x\n", (unsigned) tmp); |
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223 | #endif |
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224 | /* |
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225 | * Enable 4D0/4D1 ISA interrupt level/edge config registers |
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226 | */ |
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227 | tmp |= 0x20; |
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228 | pci_write_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function, |
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229 | 0x47, tmp); |
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230 | /* |
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231 | * Now program the ISA interrupt edge/level |
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232 | */ |
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233 | tmp = ELCRS_INT9_LVL | ELCRS_INT10_LVL | ELCRS_INT11_LVL; |
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234 | outb(tmp, ISA8259_S_ELCR); |
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235 | tmp = ELCRM_INT5_LVL; |
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236 | outb(tmp, ISA8259_M_ELCR); |
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237 | /* |
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238 | * Set the Interrupt inputs to non-inverting level interrupt |
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239 | */ |
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240 | pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function, |
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241 | 0x54, &tmp); |
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242 | #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS |
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243 | printk(" PCI ISA bridge PCI/IRQ Edge/Level Select = %x\n", (unsigned) tmp); |
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244 | #endif |
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245 | tmp = 0; |
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246 | pci_write_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function, |
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247 | 0x54, tmp); |
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248 | } |
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249 | else { |
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250 | #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS |
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251 | printk("This is a first generation MCP750 board\n"); |
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252 | printk("We just show the actual value used by PCI/ISA bridge\n"); |
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253 | #endif |
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254 | pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function, |
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255 | 0x47, &tmp); |
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256 | #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS |
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257 | printk(" PCI ISA bridge control2 = %x\n", (unsigned) tmp); |
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258 | #endif |
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259 | /* |
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260 | * Show the Interrupt inputs inverting/non-inverting level status |
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261 | */ |
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262 | pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function, |
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263 | 0x54, &tmp); |
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264 | #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS |
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265 | printk(" PCI ISA bridge PCI/IRQ Edge/Level Select = %x\n", (unsigned) tmp); |
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266 | #endif |
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267 | } |
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268 | } |
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269 | #endif |
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270 | |
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271 | /* |
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272 | * This code assumes the exceptions management setup has already |
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273 | * been done. We just need to replace the exceptions that will |
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274 | * be handled like interrupt. On mcp750/mpc750 and many PPC processors |
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275 | * this means the decrementer exception and the external exception. |
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276 | */ |
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277 | void BSP_rtems_irq_mng_init(unsigned cpuId) |
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278 | { |
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279 | #if BSP_ISA_IRQ_NUMBER > 0 && !defined(mvme2100) |
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280 | int known_cpi_isa_bridge = 0; |
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281 | #endif |
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282 | int i; |
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283 | |
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284 | /* |
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285 | * First initialize the Interrupt management hardware |
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286 | */ |
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287 | #if defined(mvme2100) |
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288 | #ifdef TRACE_IRQ_INIT |
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289 | printk("Going to initialize EPIC interrupt controller (openpic compliant)\n"); |
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290 | #endif |
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291 | /* EPIC sources don't start at the regular place; define appropriate offset |
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292 | * prior to initializing the PIC. |
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293 | */ |
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294 | openpic_init(1, mvme2100_openpic_initpolarities, mvme2100_openpic_initsenses, 16, 16, BSP_bus_frequency); |
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295 | #else |
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296 | #if BSP_PCI_IRQ_NUMBER > 0 |
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297 | #ifdef TRACE_IRQ_INIT |
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298 | printk("Going to initialize raven interrupt controller (openpic compliant)\n"); |
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299 | #endif |
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300 | openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses, 0, 0, 0); |
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301 | #ifdef TRACE_IRQ_INIT |
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302 | printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n"); |
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303 | #endif |
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304 | #endif |
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305 | |
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306 | #if BSP_ISA_IRQ_NUMBER > 0 |
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307 | if ( currentBoard == MESQUITE ) { |
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308 | #ifndef qemu |
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309 | VIA_isa_bridge_interrupts_setup(); |
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310 | #endif |
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311 | known_cpi_isa_bridge = 1; |
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312 | } |
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313 | if ( currentBoard == MVME_2300 ) { |
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314 | /* nothing to do for W83C553 bridge */ |
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315 | known_cpi_isa_bridge = 1; |
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316 | } |
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317 | if ( currentBoard == MTX_WO_PP || currentBoard == MTX_W_PP ) { |
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318 | /* W83C554, don't to anything at the moment. gregm 11/6/2002 */ |
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319 | known_cpi_isa_bridge = 1; |
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320 | } |
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321 | |
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322 | if (!known_cpi_isa_bridge) { |
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323 | printk("Please add code for PCI/ISA bridge init to libbsp/powerpc/shared/irq/irq_init.c\n"); |
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324 | printk("If your card works correctly please add a test and set known_cpi_isa_bridge to true\n"); |
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325 | printk("currentBoard = %i\n", currentBoard); |
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326 | } |
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327 | #ifdef TRACE_IRQ_INIT |
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328 | printk("Going to initialize the ISA PC legacy IRQ management hardware\n"); |
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329 | #endif |
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330 | BSP_i8259s_init(); |
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331 | #endif |
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332 | |
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333 | #endif |
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334 | |
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335 | /* |
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336 | * Initialize RTEMS management interrupt table |
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337 | */ |
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338 | /* |
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339 | * re-init the rtemsIrq table |
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340 | */ |
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341 | for (i = 0; i < BSP_IRQ_NUMBER; i++) { |
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342 | rtemsIrq[i] = defaultIrq; |
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343 | rtemsIrq[i].name = i; |
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344 | } |
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345 | /* |
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346 | * Init initial Interrupt management config |
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347 | */ |
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348 | initial_config.irqNb = BSP_IRQ_NUMBER; |
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349 | initial_config.defaultEntry = defaultIrq; |
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350 | initial_config.irqHdlTbl = rtemsIrq; |
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351 | initial_config.irqBase = BSP_LOWEST_OFFSET; |
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352 | initial_config.irqPrioTbl = irqPrioTable; |
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353 | |
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354 | if (!BSP_rtems_irq_mngt_set(&initial_config)) { |
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355 | /* |
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356 | * put something here that will show the failure... |
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357 | */ |
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358 | BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n"); |
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359 | } |
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360 | |
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361 | #ifdef TRACE_IRQ_INIT |
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362 | printk("RTEMS IRQ management is now operational\n"); |
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363 | #endif |
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364 | } |
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