source: rtems/c/src/lib/libbsp/powerpc/shared/irq/irq_init.c @ 00b5917

4.104.115
Last change on this file since 00b5917 was 00b5917, checked in by Joel Sherrill <joel.sherrill@…>, on 04/28/10 at 18:51:58

2010-04-28 Joel Sherrill <joel.sherrilL@…>

  • shared/bootloader/em86.c, shared/bootloader/mm.c, shared/console/polled_io.c, shared/irq/irq_init.c, shared/startup/bspstart.c: Remove warnings.
  • Property mode set to 100644
File size: 10.5 KB
Line 
1/* irq_init.c
2 *
3 *  This file contains the implementation of rtems initialization
4 *  related to interrupt handling.
5 *
6 *  CopyRight (C) 1999 valette@crf.canon.fr
7 *
8 * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
9 * to make it valid for MVME2300 Motorola boards.
10 *
11 * Till Straumann <strauman@slac.stanford.edu>, 12/20/2001:
12 * Use the new interface to openpic_init
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.com/license/LICENSE.
17 *
18 *  $Id$
19 */
20
21#include <libcpu/io.h>
22#include <libcpu/spr.h>
23#include <bsp/pci.h>
24#include <bsp/residual.h>
25#include <bsp/openpic.h>
26#include <bsp/irq.h>
27#include <bsp/irq_supp.h>
28#include <bsp.h>
29#include <bsp/motorola.h>
30#include <rtems/bspIo.h>
31
32typedef struct {
33  unsigned char bus;    /* few chance the PCI/ISA bridge is not on first bus but ... */
34  unsigned char device;
35  unsigned char function;
36} pci_isa_bridge_device;
37
38pci_isa_bridge_device* via_82c586 = 0;
39static pci_isa_bridge_device bridge;
40
41/*
42 * default methods
43 */
44static void nop_hdl(rtems_irq_hdl_param ignored)
45{
46}
47
48static void nop_irq_enable(const struct __rtems_irq_connect_data__*ignored)
49{
50}
51
52static int irq_is_connected(const struct __rtems_irq_connect_data__*ignored)
53{
54  return 0;
55}
56
57
58static rtems_irq_connect_data           rtemsIrq[BSP_IRQ_NUMBER];
59static rtems_irq_global_settings        initial_config;
60static rtems_irq_connect_data           defaultIrq = {
61  0,                /* vector */
62  nop_hdl,          /* hdl */
63  NULL,             /* handle */
64  nop_irq_enable,   /* on */
65  nop_irq_enable,   /* off */
66  irq_is_connected  /* isOn */
67#ifdef BSP_SHARED_HANDLER_SUPPORT
68  , NULL /* next_handler */
69#endif
70};
71static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
72  /*
73   * actual priorities for interrupt :
74   *    0   means that only current interrupt is masked
75   *    255 means all other interrupts are masked
76   */
77  /*
78   * ISA interrupts.
79   * The second entry has a priority of 255 because
80   * it is the slave pic entry and should always remain
81   * unmasked.
82   */
83  0,0,
84  255,
85  0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
86  /*
87   * PCI Interrupts
88   */
89  8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, /* for raven prio 0 means unactive... */
90  /*
91   * Processor exceptions handled as interrupts
92   */
93  0
94};
95
96#if defined(mvme2100)
97static unsigned char mvme2100_openpic_initpolarities[16] = {
98    0,  /* Not used - should be disabled */
99    0,  /* DEC21143 Controller */
100    0,  /* PMC/PC-MIP Type I Slot 0 */
101    0,  /* PC-MIP Type I Slot 1 */
102    0,  /* PC-MIP Type II Slot 0 */
103    0,  /* PC-MIP Type II Slot 1 */
104    0,  /* Not used - should be disabled */
105    0,  /* PCI Expansion Interrupt A/Universe II (LINT0) */
106    0,  /* PCI Expansion Interrupt B/Universe II (LINT1) */
107    0,  /* PCI Expansion Interrupt C/Universe II (LINT2) */
108    0,  /* PCI Expansion Interrupt D/Universe II (LINT3) */
109    0,  /* Not used - should be disabled */
110    0,  /* Not used - should be disabled */
111    1,  /* 16550 UART */
112    0,  /* Front panel Abort Switch */
113    0,  /* RTC IRQ */
114};
115
116static unsigned char mvme2100_openpic_initsenses[] = {
117    0,  /* Not used - should be disabled */
118    1,  /* DEC21143 Controller */
119    1,  /* PMC/PC-MIP Type I Slot 0 */
120    1,  /* PC-MIP Type I Slot 1 */
121    1,  /* PC-MIP Type II Slot 0 */
122    1,  /* PC-MIP Type II Slot 1 */
123    0,  /* Not used - should be disabled */
124    1,  /* PCI Expansion Interrupt A/Universe II (LINT0) */
125    1,  /* PCI Expansion Interrupt B/Universe II (LINT1) */
126    1,  /* PCI Expansion Interrupt C/Universe II (LINT2) */
127    1,  /* PCI Expansion Interrupt D/Universe II (LINT3) */
128    0,  /* Not used - should be disabled */
129    0,  /* Not used - should be disabled */
130    1,  /* 16550 UART */
131    0,  /* Front panel Abort Switch */
132    1,  /* RTC IRQ */
133};
134#else
135static unsigned char mcp750_openpic_initpolarities[16] = {
136    1,  /* 8259 cascade */
137    0,  /* all the rest of them */
138};
139
140static unsigned char mcp750_openpic_initsenses[] = {
141    1,  /* MCP750_INT_PCB(8259) */
142    0,  /* MCP750_INT_FALCON_ECC_ERR */
143    1,  /* MCP750_INT_PCI_ETHERNET */
144    1,  /* MCP750_INT_PCI_PMC */
145    1,  /* MCP750_INT_PCI_WATCHDOG_TIMER1 */
146    1,  /* MCP750_INT_PCI_PRST_SIGNAL */
147    1,  /* MCP750_INT_PCI_FALL_SIGNAL */
148    1,  /* MCP750_INT_PCI_DEG_SIGNAL */
149    1,  /* MCP750_INT_PCI_BUS1_INTA */
150    1,  /* MCP750_INT_PCI_BUS1_INTB */
151    1,  /* MCP750_INT_PCI_BUS1_INTC */
152    1,  /* MCP750_INT_PCI_BUS1_INTD */
153    1,  /* MCP750_INT_PCI_BUS2_INTA */
154    1,  /* MCP750_INT_PCI_BUS2_INTB */
155    1,  /* MCP750_INT_PCI_BUS2_INTC */
156    1,  /* MCP750_INT_PCI_BUS2_INTD */
157};
158#endif
159
160void VIA_isa_bridge_interrupts_setup(void)
161{
162  pci_isa_bridge_device pci_dev;
163  uint32_t temp;
164  unsigned char tmp;
165  unsigned char maxBus;
166  unsigned found = 0;
167
168  maxBus = pci_bus_count();
169  pci_dev.function      = 0; /* Assumes the bidge is the first function */
170
171  for (pci_dev.bus = 0; pci_dev.bus < maxBus; pci_dev.bus++) {
172#ifdef SCAN_PCI_PRINT
173    printk("isa_bridge_interrupts_setup: Scanning bus %d\n", pci_dev.bus);
174#endif
175    for (pci_dev.device = 0; pci_dev.device < PCI_MAX_DEVICES; pci_dev.device++) {
176#ifdef SCAN_PCI_PRINT
177      printk("isa_bridge_interrupts_setup: Scanning device %d\n", pci_dev.device);
178#endif
179      pci_read_config_dword(pci_dev.bus, pci_dev.device,  pci_dev.function,
180                               PCI_VENDOR_ID, &temp);
181#ifdef SCAN_PCI_PRINT
182      printk("Vendor/device = %x\n", temp);
183#endif
184      if ((temp == (((unsigned short) PCI_VENDOR_ID_VIA) | (PCI_DEVICE_ID_VIA_82C586_0 << 16)))
185         ) {
186        bridge = pci_dev;
187        via_82c586 = &bridge;
188#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
189        /*
190         * Should print : bus = 0, device = 11, function = 0 on a MCP750.
191         */
192        printk("Via PCI/ISA bridge found at bus = %d, device = %d, function = %d\n",
193               via_82c586->bus,
194               via_82c586->device,
195               via_82c586->function);
196#endif
197        found = 1;
198        goto loop_exit;
199
200      }
201    }
202  }
203loop_exit:
204  if (!found) BSP_panic("VIA_82C586 PCI/ISA bridge not found!n");
205
206  tmp = inb(0x810);
207  if  ( !(tmp & 0x2)) {
208#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
209    printk("This is a second generation MCP750 board\n");
210    printk("We must reprogram the PCI/ISA bridge...\n");
211#endif
212    pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
213                         0x47,  &tmp);
214#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
215    printk(" PCI ISA bridge control2 = %x\n", (unsigned) tmp);
216#endif
217    /*
218     * Enable 4D0/4D1 ISA interrupt level/edge config registers
219     */
220    tmp |= 0x20;
221    pci_write_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
222                          0x47, tmp);
223    /*
224     * Now program the ISA interrupt edge/level
225     */
226    tmp = ELCRS_INT9_LVL | ELCRS_INT10_LVL | ELCRS_INT11_LVL;
227    outb(tmp, ISA8259_S_ELCR);
228    tmp = ELCRM_INT5_LVL;
229    outb(tmp, ISA8259_M_ELCR);;
230    /*
231     * Set the Interrupt inputs to non-inverting level interrupt
232     */
233    pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
234                            0x54, &tmp);
235#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
236    printk(" PCI ISA bridge PCI/IRQ Edge/Level Select = %x\n", (unsigned) tmp);
237#endif
238    tmp = 0;
239    pci_write_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
240                          0x54, tmp);
241  }
242  else {
243#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
244    printk("This is a first generation MCP750 board\n");
245    printk("We just show the actual value used by PCI/ISA bridge\n");
246#endif
247    pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
248                         0x47,  &tmp);
249#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
250    printk(" PCI ISA bridge control2 = %x\n", (unsigned) tmp);
251#endif
252    /*
253     * Show the Interrupt inputs inverting/non-inverting level status
254     */
255    pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
256                         0x54, &tmp);
257#ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
258    printk(" PCI ISA bridge PCI/IRQ Edge/Level Select = %x\n", (unsigned) tmp);
259#endif
260  }
261}
262
263  /*
264   * This code assumes the exceptions management setup has already
265   * been done. We just need to replace the exceptions that will
266   * be handled like interrupt. On mcp750/mpc750 and many PPC processors
267   * this means the decrementer exception and the external exception.
268   */
269void BSP_rtems_irq_mng_init(unsigned cpuId)
270{
271#if !defined(mvme2100)
272  int known_cpi_isa_bridge = 0;
273#endif
274  int i;
275
276  /*
277   * First initialize the Interrupt management hardware
278   */
279#if defined(mvme2100)
280#ifdef TRACE_IRQ_INIT
281  printk("Going to initialize EPIC interrupt controller (openpic compliant)\n");
282#endif
283  /* EPIC sources don't start at the regular place; define appropriate offset
284   * prior to initializing the PIC.
285   */
286  openpic_init(1, mvme2100_openpic_initpolarities, mvme2100_openpic_initsenses, 16, 16, BSP_bus_frequency);
287#else
288#ifdef TRACE_IRQ_INIT
289  printk("Going to initialize raven interrupt controller (openpic compliant)\n");
290#endif
291  openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses, 0, 0, 0);
292#ifdef TRACE_IRQ_INIT
293  printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n");
294#endif
295  if ( currentBoard == MESQUITE ) {
296    VIA_isa_bridge_interrupts_setup();
297    known_cpi_isa_bridge = 1;
298  }
299  if ( currentBoard == MVME_2300 ) {
300    /* nothing to do for W83C553 bridge */
301    known_cpi_isa_bridge = 1;
302  }
303  if ( currentBoard == MTX_WO_PP || currentBoard == MTX_W_PP ) {
304     /* W83C554, don't to anything at the moment.  gregm 11/6/2002 */
305     known_cpi_isa_bridge = 1;
306  }
307
308  if (!known_cpi_isa_bridge) {
309    printk("Please add code for PCI/ISA bridge init to libbsp/powerpc/shared/irq/irq_init.c\n");
310    printk("If your card works correctly please add a test and set known_cpi_isa_bridge to true\n");
311    printk("currentBoard = %i\n", currentBoard);
312  }
313#ifdef TRACE_IRQ_INIT
314  printk("Going to initialize the ISA PC legacy IRQ management hardware\n");
315#endif
316  BSP_i8259s_init();
317#endif
318
319  /*
320   * Initialize RTEMS management interrupt table
321   */
322    /*
323     * re-init the rtemsIrq table
324     */
325    for (i = 0; i < BSP_IRQ_NUMBER; i++) {
326      rtemsIrq[i]      = defaultIrq;
327      rtemsIrq[i].name = i;
328    }
329    /*
330     * Init initial Interrupt management config
331     */
332    initial_config.irqNb        = BSP_IRQ_NUMBER;
333    initial_config.defaultEntry = defaultIrq;
334    initial_config.irqHdlTbl    = rtemsIrq;
335    initial_config.irqBase      = BSP_LOWEST_OFFSET;
336    initial_config.irqPrioTbl   = irqPrioTable;
337
338    if (!BSP_rtems_irq_mngt_set(&initial_config)) {
339      /*
340       * put something here that will show the failure...
341       */
342      BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n");
343    }
344
345#ifdef TRACE_IRQ_INIT
346    printk("RTEMS IRQ management is now operational\n");
347#endif
348}
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