[acc25ee] | 1 | /* |
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| 2 | * This file contains the assembly code for the PowerPC |
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| 3 | * IRQ veneers for RTEMS. |
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| 4 | * |
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| 5 | * The license and distribution terms for this file may be |
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| 6 | * found in found in the file LICENSE in this distribution or at |
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[e831de8] | 7 | * http://www.rtems.com/license/LICENSE. |
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[acc25ee] | 8 | * |
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| 9 | * Modified to support the MCP750. |
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| 10 | * Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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| 11 | * |
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[ec821af] | 12 | * Till Straumann <strauman@slac.stanford.edu>, 2003/7: |
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| 13 | * - store isr nesting level in _ISR_Nest_level rather than |
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| 14 | * SPRG0 - RTEMS relies on that variable. |
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[acc25ee] | 15 | * |
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| 16 | * $Id$ |
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| 17 | */ |
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| 18 | |
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[cd35cf9] | 19 | #include <asm.h> |
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| 20 | #include <rtems/score/cpu.h> |
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[acc25ee] | 21 | #include <bsp/vectors.h> |
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| 22 | #include <libcpu/raw_exception.h> |
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| 23 | |
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| 24 | |
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| 25 | #define SYNC \ |
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| 26 | sync; \ |
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| 27 | isync |
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| 28 | |
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| 29 | .text |
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| 30 | .p2align 5 |
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| 31 | |
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| 32 | PUBLIC_VAR(decrementer_exception_vector_prolog_code) |
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| 33 | |
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| 34 | SYM (decrementer_exception_vector_prolog_code): |
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| 35 | /* |
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| 36 | * let room for exception frame |
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| 37 | */ |
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| 38 | stwu r1, - (EXCEPTION_FRAME_END)(r1) |
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| 39 | stw r4, GPR4_OFFSET(r1) |
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| 40 | li r4, ASM_DEC_VECTOR |
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| 41 | ba shared_raw_irq_code_entry |
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| 42 | |
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| 43 | PUBLIC_VAR (decrementer_exception_vector_prolog_code_size) |
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| 44 | |
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| 45 | decrementer_exception_vector_prolog_code_size = . - decrementer_exception_vector_prolog_code |
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| 46 | |
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| 47 | PUBLIC_VAR(external_exception_vector_prolog_code) |
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| 48 | |
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| 49 | SYM (external_exception_vector_prolog_code): |
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| 50 | /* |
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| 51 | * let room for exception frame |
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| 52 | */ |
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| 53 | stwu r1, - (EXCEPTION_FRAME_END)(r1) |
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| 54 | stw r4, GPR4_OFFSET(r1) |
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| 55 | li r4, ASM_EXT_VECTOR |
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| 56 | ba shared_raw_irq_code_entry |
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| 57 | |
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| 58 | PUBLIC_VAR (external_exception_vector_prolog_code_size) |
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| 59 | |
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| 60 | external_exception_vector_prolog_code_size = . - external_exception_vector_prolog_code |
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| 61 | |
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| 62 | PUBLIC_VAR(shared_raw_irq_code_entry) |
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| 63 | PUBLIC_VAR(C_dispatch_irq_handler) |
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| 64 | |
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| 65 | .p2align 5 |
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| 66 | SYM (shared_raw_irq_code_entry): |
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| 67 | /* |
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| 68 | * Entry conditions : |
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| 69 | * Registers already saved : R1, R4 |
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| 70 | * R1 : points to a location with enough room for the |
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| 71 | * interrupt frame |
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| 72 | * R4 : vector number |
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| 73 | */ |
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| 74 | /* |
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| 75 | * Save SRR0/SRR1 As soon As possible as it is the minimal needed |
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| 76 | * to reenable exception processing |
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| 77 | */ |
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| 78 | stw r0, GPR0_OFFSET(r1) |
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[4f3e4f33] | 79 | /* PPC EABI: R2 is reserved (pointer to short data .sdata2) - we won't touch it |
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| 80 | * but we still save/restore it, just in case... |
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| 81 | */ |
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[acc25ee] | 82 | stw r2, GPR2_OFFSET(r1) |
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| 83 | stw r3, GPR3_OFFSET(r1) |
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| 84 | |
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| 85 | mfsrr0 r0 |
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[4f3e4f33] | 86 | mfsrr1 r3 |
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[acc25ee] | 87 | |
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| 88 | stw r0, SRR0_FRAME_OFFSET(r1) |
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[4f3e4f33] | 89 | stw r3, SRR1_FRAME_OFFSET(r1) |
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| 90 | |
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| 91 | mfmsr r3 |
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[acc25ee] | 92 | /* |
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| 93 | * Enable data and instruction address translation, exception recovery |
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[df49c60] | 94 | * |
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| 95 | * also, on CPUs with FP, enable FP so that FP context can be |
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| 96 | * saved and restored (using FP instructions) |
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[acc25ee] | 97 | */ |
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[df49c60] | 98 | #if (PPC_HAS_FPU == 0) |
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[acc25ee] | 99 | ori r3, r3, MSR_RI | MSR_IR | MSR_DR |
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[df49c60] | 100 | #else |
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| 101 | ori r3, r3, MSR_RI | MSR_IR | MSR_DR | MSR_FP |
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| 102 | #endif |
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[acc25ee] | 103 | mtmsr r3 |
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| 104 | SYNC |
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| 105 | /* |
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| 106 | * Push C scratch registers on the current stack. It may |
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| 107 | * actually be the thread stack or the interrupt stack. |
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| 108 | * Anyway we have to make it in order to be able to call C/C++ |
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| 109 | * functions. Depending on the nesting interrupt level, we will |
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| 110 | * switch to the right stack later. |
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| 111 | */ |
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| 112 | stw r5, GPR5_OFFSET(r1) |
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| 113 | stw r6, GPR6_OFFSET(r1) |
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| 114 | stw r7, GPR7_OFFSET(r1) |
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| 115 | stw r8, GPR8_OFFSET(r1) |
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| 116 | stw r9, GPR9_OFFSET(r1) |
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| 117 | stw r10, GPR10_OFFSET(r1) |
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| 118 | stw r11, GPR11_OFFSET(r1) |
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| 119 | stw r12, GPR12_OFFSET(r1) |
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| 120 | stw r13, GPR13_OFFSET(r1) |
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| 121 | |
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| 122 | mfcr r5 |
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| 123 | mfctr r6 |
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| 124 | mfxer r7 |
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| 125 | mflr r8 |
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| 126 | |
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| 127 | stw r5, EXC_CR_OFFSET(r1) |
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| 128 | stw r6, EXC_CTR_OFFSET(r1) |
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| 129 | stw r7, EXC_XER_OFFSET(r1) |
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| 130 | stw r8, EXC_LR_OFFSET(r1) |
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| 131 | |
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| 132 | /* |
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| 133 | * Add some non volatile registers to store information |
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| 134 | * that will be used when returning from C handler |
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| 135 | */ |
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| 136 | stw r14, GPR14_OFFSET(r1) |
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| 137 | stw r15, GPR15_OFFSET(r1) |
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| 138 | /* |
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| 139 | * save current stack pointer location in R14 |
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| 140 | */ |
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| 141 | addi r14, r1, 0 |
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| 142 | /* |
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| 143 | * store part of _Thread_Dispatch_disable_level address in R15 |
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| 144 | */ |
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| 145 | addis r15,0, _Thread_Dispatch_disable_level@ha |
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[ec821af] | 146 | #if BROKEN_ISR_NEST_LEVEL |
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[acc25ee] | 147 | /* |
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[4f3e4f33] | 148 | * Get current nesting level in R3 |
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[acc25ee] | 149 | */ |
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[4f3e4f33] | 150 | mfspr r3, SPRG0 |
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[ec821af] | 151 | #else |
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| 152 | /* |
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| 153 | * Retrieve current nesting level from _ISR_Nest_level |
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| 154 | */ |
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| 155 | lis r7, _ISR_Nest_level@ha |
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| 156 | lwz r3, _ISR_Nest_level@l(r7) |
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| 157 | #endif |
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[acc25ee] | 158 | /* |
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| 159 | * Check if stack switch is necessary |
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| 160 | */ |
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[4f3e4f33] | 161 | cmpwi r3,0 |
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[acc25ee] | 162 | bne nested |
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| 163 | mfspr r1, SPRG1 |
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| 164 | |
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| 165 | nested: |
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| 166 | /* |
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[4f3e4f33] | 167 | * Start Incrementing nesting level in R3 |
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[acc25ee] | 168 | */ |
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[4f3e4f33] | 169 | addi r3,r3,1 |
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[acc25ee] | 170 | /* |
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| 171 | * Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level |
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| 172 | */ |
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| 173 | lwz r6,_Thread_Dispatch_disable_level@l(r15) |
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[ec821af] | 174 | #if BROKEN_ISR_NEST_LEVEL |
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[acc25ee] | 175 | /* |
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[ec821af] | 176 | * Store new nesting level in SPRG0 |
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[acc25ee] | 177 | */ |
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[4f3e4f33] | 178 | mtspr SPRG0, r3 |
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[ec821af] | 179 | #else |
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| 180 | /* store new nesting level in _ISR_Nest_level */ |
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| 181 | stw r3, _ISR_Nest_level@l(r7) |
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| 182 | #endif |
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[acc25ee] | 183 | |
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| 184 | addi r6, r6, 1 |
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| 185 | mfmsr r5 |
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| 186 | /* |
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| 187 | * store new _Thread_Dispatch_disable_level value |
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| 188 | */ |
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| 189 | stw r6, _Thread_Dispatch_disable_level@l(r15) |
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| 190 | /* |
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| 191 | * We are now running on the interrupt stack. External and decrementer |
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| 192 | * exceptions are still disabled. I see no purpose trying to optimize |
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| 193 | * further assembler code. |
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| 194 | */ |
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| 195 | /* |
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| 196 | * Call C exception handler for decrementer Interrupt frame is passed just |
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| 197 | * in case... |
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| 198 | */ |
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| 199 | addi r3, r14, 0x8 |
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| 200 | bl C_dispatch_irq_handler /* C_dispatch_irq_handler(cpu_interrupt_frame* r3, vector r4) */ |
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| 201 | /* |
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| 202 | * start decrementing nesting level. Note : do not test result against 0 |
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| 203 | * value as an easy exit condition because if interrupt nesting level > 1 |
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| 204 | * then _Thread_Dispatch_disable_level > 1 |
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| 205 | */ |
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[ec821af] | 206 | #if BROKEN_ISR_NEST_LEVEL |
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[4f3e4f33] | 207 | mfspr r4, SPRG0 |
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[ec821af] | 208 | #else |
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| 209 | lis r7, _ISR_Nest_level@ha |
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| 210 | lwz r4, _ISR_Nest_level@l(r7) |
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| 211 | #endif |
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[acc25ee] | 212 | /* |
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| 213 | * start decrementing _Thread_Dispatch_disable_level |
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| 214 | */ |
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| 215 | lwz r3,_Thread_Dispatch_disable_level@l(r15) |
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[4f3e4f33] | 216 | addi r4, r4, -1 /* Continue decrementing nesting level */ |
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[acc25ee] | 217 | addi r3, r3, -1 /* Continue decrementing _Thread_Dispatch_disable_level */ |
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[ec821af] | 218 | #if BROKEN_ISR_NEST_LEVEL |
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[4f3e4f33] | 219 | mtspr SPRG0, r4 /* End decrementing nesting level */ |
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[ec821af] | 220 | #else |
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| 221 | stw r4, _ISR_Nest_level@l(r7) /* End decrementing nesting level */ |
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| 222 | #endif |
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[acc25ee] | 223 | stw r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */ |
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| 224 | cmpwi r3, 0 |
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| 225 | /* |
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| 226 | * switch back to original stack (done here just optimize registers |
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| 227 | * contention. Could have been done before...) |
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| 228 | */ |
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| 229 | addi r1, r14, 0 |
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| 230 | bne easy_exit /* if (_Thread_Dispatch_disable_level != 0) goto easy_exit */ |
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| 231 | /* |
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| 232 | * Here we are running again on the thread system stack. |
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| 233 | * We have interrupt nesting level = _Thread_Dispatch_disable_level = 0. |
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| 234 | * Interrupt are still disabled. Time to check if scheduler request to |
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| 235 | * do something with the current thread... |
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| 236 | */ |
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| 237 | addis r4, 0, _Context_Switch_necessary@ha |
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| 238 | lwz r5, _Context_Switch_necessary@l(r4) |
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| 239 | cmpwi r5, 0 |
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| 240 | bne switch |
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| 241 | |
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| 242 | addis r6, 0, _ISR_Signals_to_thread_executing@ha |
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| 243 | lwz r7, _ISR_Signals_to_thread_executing@l(r6) |
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| 244 | cmpwi r7, 0 |
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| 245 | li r8, 0 |
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| 246 | beq easy_exit |
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| 247 | stw r8, _ISR_Signals_to_thread_executing@l(r6) |
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| 248 | /* |
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| 249 | * going to call _ThreadProcessSignalsFromIrq |
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| 250 | * Push a complete exception like frame... |
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| 251 | */ |
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| 252 | stmw r16, GPR16_OFFSET(r1) |
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| 253 | addi r3, r1, 0x8 |
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[4f3e4f33] | 254 | /* |
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| 255 | * compute SP at exception entry |
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| 256 | */ |
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| 257 | addi r4, r1, EXCEPTION_FRAME_END |
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| 258 | /* |
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| 259 | * store it at the right place |
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| 260 | */ |
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| 261 | stw r4, GPR1_OFFSET(r1) |
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[acc25ee] | 262 | /* |
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| 263 | * Call High Level signal handling code |
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| 264 | */ |
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[e06d5aed] | 265 | bl _ThreadProcessSignalsFromIrq |
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[acc25ee] | 266 | /* |
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| 267 | * start restoring exception like frame |
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| 268 | */ |
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| 269 | lwz r31, EXC_CTR_OFFSET(r1) |
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| 270 | lwz r30, EXC_XER_OFFSET(r1) |
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| 271 | lwz r29, EXC_CR_OFFSET(r1) |
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| 272 | lwz r28, EXC_LR_OFFSET(r1) |
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| 273 | |
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| 274 | mtctr r31 |
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| 275 | mtxer r30 |
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| 276 | mtcr r29 |
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| 277 | mtlr r28 |
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| 278 | |
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| 279 | lmw r4, GPR4_OFFSET(r1) |
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| 280 | lwz r2, GPR2_OFFSET(r1) |
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| 281 | lwz r0, GPR0_OFFSET(r1) |
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| 282 | |
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| 283 | /* |
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| 284 | * Disable data and instruction translation. Make path non recoverable... |
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| 285 | */ |
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| 286 | mfmsr r3 |
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| 287 | xori r3, r3, MSR_RI | MSR_IR | MSR_DR |
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| 288 | mtmsr r3 |
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| 289 | SYNC |
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| 290 | /* |
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| 291 | * Restore rfi related settings |
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| 292 | */ |
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| 293 | |
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| 294 | lwz r3, SRR1_FRAME_OFFSET(r1) |
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| 295 | mtsrr1 r3 |
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| 296 | lwz r3, SRR0_FRAME_OFFSET(r1) |
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| 297 | mtsrr0 r3 |
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| 298 | |
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| 299 | lwz r3, GPR3_OFFSET(r1) |
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| 300 | addi r1,r1, EXCEPTION_FRAME_END |
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| 301 | SYNC |
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| 302 | rfi |
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| 303 | |
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| 304 | switch: |
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| 305 | bl SYM (_Thread_Dispatch) |
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| 306 | |
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| 307 | easy_exit: |
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| 308 | /* |
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| 309 | * start restoring interrupt frame |
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| 310 | */ |
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| 311 | lwz r3, EXC_CTR_OFFSET(r1) |
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| 312 | lwz r4, EXC_XER_OFFSET(r1) |
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| 313 | lwz r5, EXC_CR_OFFSET(r1) |
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| 314 | lwz r6, EXC_LR_OFFSET(r1) |
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| 315 | |
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| 316 | mtctr r3 |
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| 317 | mtxer r4 |
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| 318 | mtcr r5 |
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| 319 | mtlr r6 |
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| 320 | |
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| 321 | lwz r15, GPR15_OFFSET(r1) |
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| 322 | lwz r14, GPR14_OFFSET(r1) |
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| 323 | lwz r13, GPR13_OFFSET(r1) |
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| 324 | lwz r12, GPR12_OFFSET(r1) |
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| 325 | lwz r11, GPR11_OFFSET(r1) |
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| 326 | lwz r10, GPR10_OFFSET(r1) |
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| 327 | lwz r9, GPR9_OFFSET(r1) |
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| 328 | lwz r8, GPR8_OFFSET(r1) |
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| 329 | lwz r7, GPR7_OFFSET(r1) |
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| 330 | lwz r6, GPR6_OFFSET(r1) |
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| 331 | lwz r5, GPR5_OFFSET(r1) |
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| 332 | |
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| 333 | /* |
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| 334 | * Disable nested exception processing, data and instruction |
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| 335 | * translation. |
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| 336 | */ |
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| 337 | mfmsr r3 |
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| 338 | xori r3, r3, MSR_RI | MSR_IR | MSR_DR |
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| 339 | mtmsr r3 |
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| 340 | SYNC |
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| 341 | /* |
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| 342 | * Restore rfi related settings |
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| 343 | */ |
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| 344 | |
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| 345 | lwz r4, SRR1_FRAME_OFFSET(r1) |
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[4f3e4f33] | 346 | lwz r3, SRR0_FRAME_OFFSET(r1) |
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| 347 | lwz r2, GPR2_OFFSET(r1) |
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[acc25ee] | 348 | lwz r0, GPR0_OFFSET(r1) |
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| 349 | |
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| 350 | mtsrr1 r4 |
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[4f3e4f33] | 351 | mtsrr0 r3 |
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[acc25ee] | 352 | lwz r4, GPR4_OFFSET(r1) |
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[4f3e4f33] | 353 | lwz r3, GPR3_OFFSET(r1) |
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[acc25ee] | 354 | addi r1,r1, EXCEPTION_FRAME_END |
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| 355 | SYNC |
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| 356 | rfi |
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| 357 | |
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