source: rtems/c/src/lib/libbsp/powerpc/shared/irq/irq.h @ 2d0d029

4.104.114.84.9
Last change on this file since 2d0d029 was 2d0d029, checked in by Jennifer Averett <Jennifer.Averett@…>, on Apr 15, 2005 at 5:52:46 PM

2005-04-15 Jennifer Averett <jennifer.averett@…>

PR 779/bsp

  • clock/p_clock.c, console/console.c, console/uart.c, console/uart.h, irq/irq.c, irq/irq.h, irq/irq_init.c: powerpc: add parameter to new exception interrupt handlers
  • Property mode set to 100644
File size: 12.2 KB
Line 
1/* irq.h
2 *
3 *  This include file describe the data structure and the functions implemented
4 *  by RTEMS to write interrupt handlers.
5 *
6 *  Copyright (C) 1999 valette@crf.canon.fr
7 *
8 *  This code is heavilly inspired by the public specification of STREAM V2
9 *  that can be found at :
10 *
11 *      <http://www.chorus.com/Documentation/index.html> by following
12 *  the STREAM API Specification Document link.
13 *
14 *  The license and distribution terms for this file may be
15 *  found in found in the file LICENSE in this distribution or at
16 *  http://www.rtems.com/license/LICENSE.
17 *
18 *  $Id$
19 */
20
21#ifndef LIBBSP_POWERPC_MCP750_IRQ_IRQ_H
22#define LIBBSP_POWERPC_MCP750_IRQ_IRQ_H
23
24/*
25 * 8259 edge/level control definitions at VIA
26 */
27#define ISA8259_M_ELCR          0x4d0
28#define ISA8259_S_ELCR          0x4d1
29
30#define ELCRS_INT15_LVL         0x80
31#define ELCRS_INT14_LVL         0x40
32#define ELCRS_INT13_LVL         0x20
33#define ELCRS_INT12_LVL         0x10
34#define ELCRS_INT11_LVL         0x08
35#define ELCRS_INT10_LVL         0x04
36#define ELCRS_INT9_LVL          0x02
37#define ELCRS_INT8_LVL          0x01
38#define ELCRM_INT7_LVL          0x80
39#define ELCRM_INT6_LVL          0x40
40#define ELCRM_INT5_LVL          0x20
41#define ELCRM_INT4_LVL          0x10
42#define ELCRM_INT3_LVL          0x8
43#define ELCRM_INT2_LVL          0x4
44#define ELCRM_INT1_LVL          0x2
45#define ELCRM_INT0_LVL          0x1
46
47#define BSP_ASM_IRQ_VECTOR_BASE 0x0
48    /* PIC's command and mask registers */
49#define PIC_MASTER_COMMAND_IO_PORT              0x20    /* Master PIC command register */
50#define PIC_SLAVE_COMMAND_IO_PORT               0xa0    /* Slave PIC command register */
51#define PIC_MASTER_IMR_IO_PORT                  0x21    /* Master PIC Interrupt Mask Register */
52#define PIC_SLAVE_IMR_IO_PORT                   0xa1    /* Slave PIC Interrupt Mask Register */
53
54    /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
55#define PIC_EOSI        0x60    /* End of Specific Interrupt (EOSI) */
56#define SLAVE_PIC_EOSI  0x62    /* End of Specific Interrupt (EOSI) for cascade */
57#define PIC_EOI         0x20    /* Generic End of Interrupt (EOI) */
58
59#ifndef ASM
60
61#ifdef __cplusplus
62extern "C" {
63#endif
64
65/*
66 * Symbolic IRQ names and related definitions
67 */
68
69typedef enum {
70  /* Base vector for our ISA IRQ handlers. */
71  BSP_ISA_IRQ_VECTOR_BASE       = BSP_ASM_IRQ_VECTOR_BASE,
72  /*
73   * ISA IRQ handler related definitions
74   */
75  BSP_ISA_IRQ_NUMBER            = 16,
76  BSP_ISA_IRQ_LOWEST_OFFSET     = 0,
77  BSP_ISA_IRQ_MAX_OFFSET        = BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1,
78  /*
79   * PCI IRQ handlers related definitions
80   * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
81   */
82  BSP_PCI_IRQ_NUMBER            = 16,
83  BSP_PCI_IRQ_LOWEST_OFFSET     = BSP_ISA_IRQ_NUMBER,
84  BSP_PCI_IRQ_MAX_OFFSET        = BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1,
85  /*
86   * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
87   * handler might be connected
88   */
89  BSP_PROCESSOR_IRQ_NUMBER      = 1,
90  BSP_PROCESSOR_IRQ_LOWEST_OFFSET = BSP_PCI_IRQ_MAX_OFFSET + 1,
91  BSP_PROCESSOR_IRQ_MAX_OFFSET  = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1,
92  /* Misc vectors for OPENPIC irqs (IPI, timers)
93   */
94  BSP_MISC_IRQ_NUMBER           = 8,
95  BSP_MISC_IRQ_LOWEST_OFFSET    = BSP_PROCESSOR_IRQ_MAX_OFFSET + 1,
96  BSP_MISC_IRQ_MAX_OFFSET       = BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1,
97  /*
98   * Summary
99   */
100  BSP_IRQ_NUMBER                = BSP_MISC_IRQ_MAX_OFFSET + 1,
101  BSP_LOWEST_OFFSET             = BSP_ISA_IRQ_LOWEST_OFFSET,
102  BSP_MAX_OFFSET                = BSP_MISC_IRQ_MAX_OFFSET,
103    /*
104     * Some ISA IRQ symbolic name definition
105     */
106  BSP_ISA_PERIODIC_TIMER        = 0,
107  BSP_ISA_KEYBOARD              = 1,
108  BSP_ISA_UART_COM2_IRQ         = 3,
109  BSP_ISA_UART_COM1_IRQ         = 4,
110  BSP_ISA_RT_TIMER1             = 8,
111  BSP_ISA_RT_TIMER3             = 10,
112    /*
113     * Some PCI IRQ symbolic name definition
114     */
115  BSP_PCI_IRQ0                  = BSP_PCI_IRQ_LOWEST_OFFSET,
116  BSP_PCI_ISA_BRIDGE_IRQ        = BSP_PCI_IRQ0,
117
118#if defined(mvme2100)
119  BSP_DEC21143_IRQ                = BSP_PCI_IRQ_LOWEST_OFFSET + 1,
120  BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ   = BSP_PCI_IRQ_LOWEST_OFFSET + 2,
121  BSP_PCMIP_TYPE1_SLOT1_IRQ       = BSP_PCI_IRQ_LOWEST_OFFSET + 3,
122  BSP_PCMIP_TYPE2_SLOT0_IRQ       = BSP_PCI_IRQ_LOWEST_OFFSET + 4,
123  BSP_PCMIP_TYPE2_SLOT1_IRQ       = BSP_PCI_IRQ_LOWEST_OFFSET + 5,
124  BSP_PCI_INTA_UNIVERSE_LINT0_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 7,
125  BSP_PCI_INTB_UNIVERSE_LINT1_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 8,
126  BSP_PCI_INTC_UNIVERSE_LINT2_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 9,
127  BSP_PCI_INTD_UNIVERSE_LINT3_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 10,
128  BSP_UART_COM1_IRQ               = BSP_PCI_IRQ_LOWEST_OFFSET + 13,
129  BSP_FRONT_PANEL_ABORT_IRQ       = BSP_PCI_IRQ_LOWEST_OFFSET + 14,
130  BSP_RTC_IRQ                     = BSP_PCI_IRQ_LOWEST_OFFSET + 15,
131#endif
132
133    /*
134     * Some Processor execption handled as RTEMS IRQ symbolic name definition
135     */
136  BSP_DECREMENTER               = BSP_PROCESSOR_IRQ_LOWEST_OFFSET
137
138} rtems_irq_symbolic_name;
139
140/*
141 * Type definition for RTEMS managed interrupts
142 */
143typedef unsigned char  rtems_irq_prio;
144typedef unsigned short rtems_i8259_masks;
145
146extern  volatile rtems_i8259_masks i8259s_cache;
147
148struct  __rtems_irq_connect_data__;     /* forward declaratiuon */
149
150typedef void *rtems_irq_hdl_param;
151typedef void (*rtems_irq_hdl)           (rtems_irq_hdl_param);
152typedef void (*rtems_irq_enable)        (const struct __rtems_irq_connect_data__*);
153typedef void (*rtems_irq_disable)       (const struct __rtems_irq_connect_data__*);
154typedef int  (*rtems_irq_is_enabled)    (const struct __rtems_irq_connect_data__*);
155
156typedef struct __rtems_irq_connect_data__ {
157      /*
158       * IRQ line
159       */
160      rtems_irq_symbolic_name   name;
161      /*
162       * handler. See comment on handler properties below in function prototype.
163       */
164      rtems_irq_hdl                     hdl;
165     /*
166      * Handler handle to store private data
167      */
168      rtems_irq_hdl_param               handle;
169      /*
170       * function for enabling interrupts at device level (ONLY!).
171       * The BSP code will automatically enable it at i8259s level and openpic level.
172       * RATIONALE : anyway such code has to exist in current driver code.
173       * It is usually called immediately AFTER connecting the interrupt handler.
174       * RTEMS may well need such a function when restoring normal interrupt
175       * processing after a debug session.
176       *
177       */
178      rtems_irq_enable          on;
179      /*
180       * function for disabling interrupts at device level (ONLY!).
181       * The code will disable it at i8259s level. RATIONALE : anyway
182       * such code has to exist for clean shutdown. It is usually called
183       * BEFORE disconnecting the interrupt. RTEMS may well need such
184       * a function when disabling normal interrupt processing for
185       * a debug session. May well be a NOP function.
186       */
187      rtems_irq_disable         off;
188      /*
189       * function enabling to know what interrupt may currently occur
190       * if someone manipulates the i8259s interrupt mask without care...
191       */
192      rtems_irq_is_enabled      isOn;
193      /*
194       *  Set to -1 for vectors forced to have only 1 handler
195       */
196      void *next_handler;
197
198}rtems_irq_connect_data;
199
200typedef struct {
201  /*
202   * size of all the table fields (*Tbl) described below.
203   */
204  unsigned int                  irqNb;
205  /*
206   * Default handler used when disconnecting interrupts.
207   */
208  rtems_irq_connect_data        defaultEntry;
209  /*
210   * Table containing initials/current value.
211   */
212  rtems_irq_connect_data*       irqHdlTbl;
213  /*
214   * actual value of BSP_ISA_IRQ_VECTOR_BASE...
215   */
216  rtems_irq_symbolic_name       irqBase;
217  /*
218   * software priorities associated with interrupts.
219   * if (*irqPrio  [i]  >  intrPrio  [j]  it  means  that
220   * interrupt handler hdl connected for interrupt name i
221   * will  not be interrupted by the handler connected for interrupt j
222   * The interrupt source  will be physically masked at i8259 level.
223   */
224    rtems_irq_prio*             irqPrioTbl;
225}rtems_irq_global_settings;
226
227/*-------------------------------------------------------------------------+
228| Function Prototypes.
229+--------------------------------------------------------------------------*/
230/*
231 * ------------------------ Intel 8259 (or emulation) Mngt Routines -------
232 */
233
234/*
235 * function to disable a particular irq at 8259 level. After calling
236 * this function, even if the device asserts the interrupt line it will
237 * not be propagated further to the processor
238 */
239int BSP_irq_disable_at_i8259s        (const rtems_irq_symbolic_name irqLine);
240/*
241 * function to enable a particular irq at 8259 level. After calling
242 * this function, if the device asserts the interrupt line it will
243 * be propagated further to the processor
244 */
245int BSP_irq_enable_at_i8259s            (const rtems_irq_symbolic_name irqLine);
246/*
247 * function to acknowledge a particular irq at 8259 level. After calling
248 * this function, if a device asserts an enabled interrupt line it will
249 * be propagated further to the processor. Mainly usefull for people
250 * writing raw handlers as this is automagically done for RTEMS managed
251 * handlers.
252 */
253int BSP_irq_ack_at_i8259s               (const rtems_irq_symbolic_name irqLine);
254/*
255 * function to check if a particular irq is enabled at 8259 level. After calling
256 */
257int BSP_irq_enabled_at_i8259s           (const rtems_irq_symbolic_name irqLine);
258/*
259 * ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
260 */
261/*
262 * function to connect a particular irq handler. This hanlder will NOT be called
263 * directly as the result of the corresponding interrupt. Instead, a RTEMS
264 * irq prologue will be called that will :
265 *
266 *      1) save the C scratch registers,
267 *      2) switch to a interrupt stack if the interrupt is not nested,
268 *      3) store the current i8259s' interrupt masks
269 *      4) modify them to disable the current interrupt at 8259 level (and may
270 *      be others depending on software priorities)
271 *      5) acknowledge the i8259s',
272 *      6) demask the processor,
273 *      7) call the application handler
274 *
275 * As a result the hdl function provided
276 *
277 *      a) can perfectly be written is C,
278 *      b) may also well directly call the part of the RTEMS API that can be
279 *      used from interrupt level,
280 *      c) It only responsible for handling the jobs that need to be done at
281 *      the device level including (aknowledging/re-enabling the interrupt
282 *      at device, level, getting the data,...)
283 *
284 *      When returning from the function, the following will be performed by
285 *      the RTEMS irq epilogue:
286 *
287 *      1) masks the interrupts again,
288 *      2) restore the original i8259s' interrupt masks
289 *      3) switch back on the orinal stack if needed,
290 *      4) perform rescheduling when necessary,
291 *      5) restore the C scratch registers...
292 *      6) restore initial execution flow
293 */
294int BSP_install_rtems_irq_handler       (const rtems_irq_connect_data*);
295int BSP_install_rtems_shared_irq_handler  (const rtems_irq_connect_data*);
296
297#define BSP_SHARED_HANDLER_SUPPORT      1
298
299/*
300 * function to get the current RTEMS irq handler for ptr->name. It enables to
301 * define hanlder chain...
302 */
303int BSP_get_current_rtems_irq_handler   (rtems_irq_connect_data* ptr);
304/*
305 * function to get disconnect the RTEMS irq handler for ptr->name.
306 * This function checks that the value given is the current one for safety
307 * reasons.
308 * The user can use the previous function to get it.
309 */
310int BSP_remove_rtems_irq_handler        (const rtems_irq_connect_data*);
311
312/*
313 * ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------
314 */
315/*
316 * (Re) Initialize the RTEMS interrupt management.
317 *
318 * The result of calling this function will be the same as if each individual
319 * handler (config->irqHdlTbl[i].hdl)  different from "config->defaultEntry.hdl"
320 * has been individualy connected via
321 *      BSP_install_rtems_irq_handler(&config->irqHdlTbl[i])
322 * And each handler currently equal to config->defaultEntry.hdl
323 * has been previously disconnected via
324 *       BSP_remove_rtems_irq_handler (&config->irqHdlTbl[i])
325 *
326 * This is to say that all information given will be used and not just
327 * only the space.
328 *
329 * CAUTION : the various table address contained in config will be used
330 *           directly by the interrupt mangement code in order to save
331 *           data size so they must stay valid after the call => they should
332 *           not be modified or declared on a stack.
333 */
334
335int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config);
336/*
337 * (Re) get info on current RTEMS interrupt management.
338 */
339int BSP_rtems_irq_mngt_get(rtems_irq_global_settings**);
340
341extern void BSP_rtems_irq_mng_init(unsigned cpuId);
342extern void BSP_i8259s_init(void);
343
344#ifdef __cplusplus
345}
346#endif
347
348#endif
349
350#endif
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