[acc25ee] | 1 | /* irq.h |
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| 2 | * |
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| 3 | * This include file describe the data structure and the functions implemented |
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[e79a1947] | 4 | * by RTEMS to write interrupt handlers. |
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[acc25ee] | 5 | * |
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[e79a1947] | 6 | * Copyright (C) 1999 valette@crf.canon.fr |
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[acc25ee] | 7 | * |
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| 8 | * This code is heavilly inspired by the public specification of STREAM V2 |
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| 9 | * that can be found at : |
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| 10 | * |
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| 11 | * <http://www.chorus.com/Documentation/index.html> by following |
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| 12 | * the STREAM API Specification Document link. |
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| 13 | * |
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| 14 | * The license and distribution terms for this file may be |
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| 15 | * found in found in the file LICENSE in this distribution or at |
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[e831de8] | 16 | * http://www.rtems.com/license/LICENSE. |
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[acc25ee] | 17 | * |
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| 18 | * $Id$ |
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| 19 | */ |
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| 20 | |
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[d8999b7] | 21 | #ifndef BSP_POWERPC_IRQ_H |
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| 22 | #define BSP_POWERPC_IRQ_H |
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| 23 | |
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| 24 | #define BSP_SHARED_HANDLER_SUPPORT 1 |
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| 25 | #include <rtems/irq.h> |
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[acc25ee] | 26 | |
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| 27 | /* |
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| 28 | * 8259 edge/level control definitions at VIA |
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| 29 | */ |
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| 30 | #define ISA8259_M_ELCR 0x4d0 |
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| 31 | #define ISA8259_S_ELCR 0x4d1 |
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| 32 | |
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| 33 | #define ELCRS_INT15_LVL 0x80 |
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| 34 | #define ELCRS_INT14_LVL 0x40 |
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| 35 | #define ELCRS_INT13_LVL 0x20 |
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| 36 | #define ELCRS_INT12_LVL 0x10 |
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| 37 | #define ELCRS_INT11_LVL 0x08 |
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| 38 | #define ELCRS_INT10_LVL 0x04 |
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| 39 | #define ELCRS_INT9_LVL 0x02 |
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| 40 | #define ELCRS_INT8_LVL 0x01 |
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| 41 | #define ELCRM_INT7_LVL 0x80 |
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| 42 | #define ELCRM_INT6_LVL 0x40 |
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| 43 | #define ELCRM_INT5_LVL 0x20 |
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| 44 | #define ELCRM_INT4_LVL 0x10 |
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| 45 | #define ELCRM_INT3_LVL 0x8 |
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| 46 | #define ELCRM_INT2_LVL 0x4 |
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| 47 | #define ELCRM_INT1_LVL 0x2 |
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| 48 | #define ELCRM_INT0_LVL 0x1 |
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| 49 | |
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| 50 | #define BSP_ASM_IRQ_VECTOR_BASE 0x0 |
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| 51 | /* PIC's command and mask registers */ |
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| 52 | #define PIC_MASTER_COMMAND_IO_PORT 0x20 /* Master PIC command register */ |
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| 53 | #define PIC_SLAVE_COMMAND_IO_PORT 0xa0 /* Slave PIC command register */ |
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| 54 | #define PIC_MASTER_IMR_IO_PORT 0x21 /* Master PIC Interrupt Mask Register */ |
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| 55 | #define PIC_SLAVE_IMR_IO_PORT 0xa1 /* Slave PIC Interrupt Mask Register */ |
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| 56 | |
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| 57 | /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */ |
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| 58 | #define PIC_EOSI 0x60 /* End of Specific Interrupt (EOSI) */ |
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| 59 | #define SLAVE_PIC_EOSI 0x62 /* End of Specific Interrupt (EOSI) for cascade */ |
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| 60 | #define PIC_EOI 0x20 /* Generic End of Interrupt (EOI) */ |
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| 61 | |
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| 62 | #ifndef ASM |
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| 63 | |
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[ae1f243] | 64 | #ifdef __cplusplus |
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| 65 | extern "C" { |
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| 66 | #endif |
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| 67 | |
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[acc25ee] | 68 | /* |
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[d8999b7] | 69 | * rtems_irq_number Definitions |
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[acc25ee] | 70 | */ |
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| 71 | |
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[d8999b7] | 72 | /* Base vector for our ISA IRQ handlers. */ |
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| 73 | #define BSP_ISA_IRQ_VECTOR_BASE (BSP_ASM_IRQ_VECTOR_BASE) |
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| 74 | /* |
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| 75 | * ISA IRQ handler related definitions |
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| 76 | */ |
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| 77 | #define BSP_ISA_IRQ_NUMBER (16) |
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| 78 | #define BSP_ISA_IRQ_LOWEST_OFFSET (0) |
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| 79 | #define BSP_ISA_IRQ_MAX_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1) |
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| 80 | /* |
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| 81 | * PCI IRQ handlers related definitions |
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| 82 | * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE |
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| 83 | */ |
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| 84 | #define BSP_PCI_IRQ_NUMBER (16) |
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| 85 | #define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_ISA_IRQ_NUMBER) |
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| 86 | #define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) |
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| 87 | /* |
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| 88 | * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt |
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| 89 | * handler might be connected |
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| 90 | */ |
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| 91 | #define BSP_PROCESSOR_IRQ_NUMBER (1) |
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| 92 | #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1) |
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| 93 | #define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) |
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| 94 | /* Misc vectors for OPENPIC irqs (IPI, timers) |
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| 95 | */ |
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| 96 | #define BSP_MISC_IRQ_NUMBER (8) |
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| 97 | #define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) |
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| 98 | #define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1) |
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| 99 | /* |
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| 100 | * Summary |
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| 101 | */ |
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| 102 | #define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1) |
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| 103 | #define BSP_LOWEST_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET) |
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| 104 | #define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET) |
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| 105 | /* |
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| 106 | * Some ISA IRQ symbolic name definition |
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| 107 | */ |
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| 108 | #define BSP_ISA_PERIODIC_TIMER (0) |
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| 109 | #define BSP_ISA_KEYBOARD (1) |
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| 110 | #define BSP_ISA_UART_COM2_IRQ (3) |
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| 111 | #define BSP_ISA_UART_COM1_IRQ (4) |
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| 112 | #define BSP_ISA_RT_TIMER1 (8) |
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| 113 | #define BSP_ISA_RT_TIMER3 (10) |
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| 114 | /* |
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| 115 | * Some PCI IRQ symbolic name definition |
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| 116 | */ |
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| 117 | #define BSP_PCI_IRQ0 (BSP_PCI_IRQ_LOWEST_OFFSET) |
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| 118 | #define BSP_PCI_ISA_BRIDGE_IRQ (BSP_PCI_IRQ0) |
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[e79a1947] | 119 | |
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| 120 | #if defined(mvme2100) |
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[d8999b7] | 121 | #define BSP_DEC21143_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 1) |
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| 122 | #define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 2) |
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| 123 | #define BSP_PCMIP_TYPE1_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 3) |
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| 124 | #define BSP_PCMIP_TYPE2_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 4) |
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| 125 | #define BSP_PCMIP_TYPE2_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 5) |
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| 126 | #define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7) |
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| 127 | #define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8) |
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| 128 | #define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9) |
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| 129 | #define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10) |
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| 130 | #define BSP_UART_COM1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 13) |
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| 131 | #define BSP_FRONT_PANEL_ABORT_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 14) |
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| 132 | #define BSP_RTC_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 15) |
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[f3173c0] | 133 | #else |
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| 134 | #define BSP_UART_COM1_IRQ BSP_ISA_UART_COM1_IRQ |
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| 135 | #define BSP_UART_COM2_IRQ BSP_ISA_UART_COM2_IRQ |
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[e79a1947] | 136 | #endif |
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| 137 | |
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[d8999b7] | 138 | /* |
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| 139 | * Some Processor execption handled as RTEMS IRQ symbolic name definition |
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| 140 | */ |
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| 141 | #define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) |
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[6128a4a] | 142 | |
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[acc25ee] | 143 | |
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| 144 | /* |
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| 145 | * Type definition for RTEMS managed interrupts |
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| 146 | */ |
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| 147 | typedef unsigned short rtems_i8259_masks; |
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| 148 | |
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| 149 | extern volatile rtems_i8259_masks i8259s_cache; |
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| 150 | |
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| 151 | /*-------------------------------------------------------------------------+ |
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| 152 | | Function Prototypes. |
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| 153 | +--------------------------------------------------------------------------*/ |
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| 154 | /* |
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| 155 | * ------------------------ Intel 8259 (or emulation) Mngt Routines ------- |
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| 156 | */ |
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[8c9fffd] | 157 | void BSP_i8259s_init(void); |
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[acc25ee] | 158 | |
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| 159 | /* |
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| 160 | * function to disable a particular irq at 8259 level. After calling |
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| 161 | * this function, even if the device asserts the interrupt line it will |
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| 162 | * not be propagated further to the processor |
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| 163 | */ |
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[d8999b7] | 164 | int BSP_irq_disable_at_i8259s (const rtems_irq_number irqLine); |
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[acc25ee] | 165 | /* |
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| 166 | * function to enable a particular irq at 8259 level. After calling |
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| 167 | * this function, if the device asserts the interrupt line it will |
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| 168 | * be propagated further to the processor |
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| 169 | */ |
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[d8999b7] | 170 | int BSP_irq_enable_at_i8259s (const rtems_irq_number irqLine); |
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[acc25ee] | 171 | /* |
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[e79a1947] | 172 | * function to acknowledge a particular irq at 8259 level. After calling |
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[acc25ee] | 173 | * this function, if a device asserts an enabled interrupt line it will |
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| 174 | * be propagated further to the processor. Mainly usefull for people |
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[e79a1947] | 175 | * writing raw handlers as this is automagically done for RTEMS managed |
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[acc25ee] | 176 | * handlers. |
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| 177 | */ |
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[d8999b7] | 178 | int BSP_irq_ack_at_i8259s (const rtems_irq_number irqLine); |
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[acc25ee] | 179 | /* |
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| 180 | * function to check if a particular irq is enabled at 8259 level. After calling |
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| 181 | */ |
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[d8999b7] | 182 | int BSP_irq_enabled_at_i8259s (const rtems_irq_number irqLine); |
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[6128a4a] | 183 | |
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[acc25ee] | 184 | extern void BSP_rtems_irq_mng_init(unsigned cpuId); |
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| 185 | extern void BSP_i8259s_init(void); |
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[ae1f243] | 186 | |
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[8c9fffd] | 187 | /* |
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| 188 | * PIC-independent function to enable/disable interrupt lines at |
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| 189 | * the pic. |
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| 190 | */ |
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| 191 | extern void BSP_enable_irq_at_pic (const rtems_irq_number irqLine); |
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| 192 | extern void BSP_disable_irq_at_pic (const rtems_irq_number irqLine); |
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| 193 | |
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| 194 | extern int BSP_setup_the_pic (rtems_irq_global_settings* config); |
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[ae1f243] | 195 | #ifdef __cplusplus |
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[8c9fffd] | 196 | }; |
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[ae1f243] | 197 | #endif |
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| 198 | |
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[acc25ee] | 199 | #endif |
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| 200 | #endif |
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