source: rtems/c/src/lib/libbsp/powerpc/shared/irq/irq.c @ f05b2ac

4.104.114.84.95
Last change on this file since f05b2ac was f05b2ac, checked in by Ralf Corsepius <ralf.corsepius@…>, on 04/21/04 at 16:01:48

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1/*
2 *
3 *  This file contains the implementation of the function described in irq.h
4 *
5 *  Copyright (C) 1998, 1999 valette@crf.canon.fr
6 *
7 *  The license and distribution terms for this file may be
8 *  found in found in the file LICENSE in this distribution or at
9 *  http://www.rtems.com/license/LICENSE.
10 *
11 *  $Id$
12 */
13
14#include <stdlib.h>
15
16#include <bsp.h>
17#include <bsp/irq.h>
18#include <bsp/VME.h>
19#include <bsp/openpic.h>
20#include <rtems/score/apiext.h>  /* for post ISR signal processing */
21#include <libcpu/raw_exception.h>
22#include <libcpu/io.h>
23#include <bsp/vectors.h>
24
25#include <rtems/bspIo.h> /* for printk */
26#define RAVEN_INTR_ACK_REG 0xfeff0030
27
28/*
29 * pointer to the mask representing the additionnal irq vectors
30 * that must be disabled when a particular entry is activated.
31 * They will be dynamically computed from teh prioruty table given
32 * in BSP_rtems_irq_mngt_set();
33 * CAUTION : this table is accessed directly by interrupt routine
34 *           prologue.
35 */
36rtems_i8259_masks       irq_mask_or_tbl[BSP_IRQ_NUMBER];
37/*
38 * default handler connected on each irq after bsp initialization
39 */
40static rtems_irq_connect_data   default_rtems_entry;
41
42/*
43 * location used to store initial tables used for interrupt
44 * management.
45 */
46static rtems_irq_global_settings*       internal_config;
47static rtems_irq_connect_data*          rtems_hdl_tbl;
48
49/*
50 * Check if IRQ is an ISA IRQ
51 */
52static inline int is_isa_irq(const rtems_irq_symbolic_name irqLine)
53{
54  return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) &
55          ((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET)
56         );
57}
58
59/*
60 * Check if IRQ is an OPENPIC IRQ
61 */
62static inline int is_pci_irq(const rtems_irq_symbolic_name irqLine)
63{
64  return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) &
65          ((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET)
66         );
67}
68
69/*
70 * Check if IRQ is a Porcessor IRQ
71 */
72static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine)
73{
74  return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) &
75          ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
76         );
77}
78
79/*
80 * ------------------------ RTEMS Irq helper functions ----------------
81 */
82
83/*
84 * Caution : this function assumes the variable "internal_config"
85 * is already set and that the tables it contains are still valid
86 * and accessible.
87 */
88static void compute_i8259_masks_from_prio ()
89{
90  int i;
91  int j;
92  /*
93   * Always mask at least current interrupt to prevent re-entrance
94   */
95  for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
96    * ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i);
97    for (j = BSP_ISA_IRQ_LOWEST_OFFSET; j < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; j++) {
98      /*
99       * Mask interrupts at i8259 level that have a lower priority
100       */
101      if (internal_config->irqPrioTbl [i] > internal_config->irqPrioTbl [j]) {
102        * ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j);
103      }
104    }
105  }
106}
107
108/*
109 * This function check that the value given for the irq line
110 * is valid.
111 */
112
113static int isValidInterrupt(int irq)
114{
115  if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET))
116    return 0;
117  return 1;
118}
119
120/*
121 * ------------------------ RTEMS Shared Irq Handler Mngt Routines ----------------
122 */
123int BSP_install_rtems_shared_irq_handler  (const rtems_irq_connect_data* irq)
124{
125    unsigned int level;
126    rtems_irq_connect_data* vchain;
127
128    if (!isValidInterrupt(irq->name)) {
129      printk("Invalid interrupt vector %d\n",irq->name);
130      return 0;
131    }
132
133    _CPU_ISR_Disable(level);
134
135    if ( (int)rtems_hdl_tbl[irq->name].next_handler  == -1 ) {
136      _CPU_ISR_Enable(level);
137      printk("IRQ vector %d already connected to an unshared handler\n",irq->name);
138      return 0;
139    }
140
141     vchain = (rtems_irq_connect_data*)malloc(sizeof(rtems_irq_connect_data));
142
143    /* save off topmost handler */
144    vchain[0]= rtems_hdl_tbl[irq->name];
145
146    /*
147     * store the data provided by user
148     */
149    rtems_hdl_tbl[irq->name] = *irq;
150
151    /* link chain to new topmost handler */
152    rtems_hdl_tbl[irq->name].next_handler = (void *)vchain;
153
154    if (is_isa_irq(irq->name)) {
155      /*
156       * Enable interrupt at PIC level
157       */
158      BSP_irq_enable_at_i8259s (irq->name);
159    }
160
161    if (is_pci_irq(irq->name)) {
162      /*
163       * Enable interrupt at OPENPIC level
164       */
165      openpic_enable_irq ((int) irq->name - BSP_PCI_IRQ_LOWEST_OFFSET);
166    }
167
168    if (is_processor_irq(irq->name)) {
169      /*
170       * Enable exception at processor level
171       */
172    }
173    /*
174     * Enable interrupt on device
175     */
176    irq->on(irq);
177
178    _CPU_ISR_Enable(level);
179
180    return 1;
181}
182
183/*
184 * ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
185 */
186
187int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
188{
189    unsigned int level;
190
191    if (!isValidInterrupt(irq->name)) {
192      printk("Invalid interrupt vector %d\n",irq->name);
193      return 0;
194    }
195    /*
196     * Check if default handler is actually connected. If not issue an error.
197     * You must first get the current handler via i386_get_current_idt_entry
198     * and then disconnect it using i386_delete_idt_entry.
199     * RATIONALE : to always have the same transition by forcing the user
200     * to get the previous handler before accepting to disconnect.
201     */
202    _CPU_ISR_Disable(level);
203    if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {
204      _CPU_ISR_Enable(level);
205      printk("IRQ vector %d already connected\n",irq->name);
206      return 0;
207    }
208
209    /*
210     * store the data provided by user
211     */
212    rtems_hdl_tbl[irq->name] = *irq;
213    rtems_hdl_tbl[irq->name].next_handler = (void *)-1;
214
215    if (is_isa_irq(irq->name)) {
216      /*
217       * Enable interrupt at PIC level
218       */
219      BSP_irq_enable_at_i8259s (irq->name);
220    }
221
222    if (is_pci_irq(irq->name)) {
223      /*
224       * Enable interrupt at OPENPIC level
225       */
226      openpic_enable_irq ((int) irq->name - BSP_PCI_IRQ_LOWEST_OFFSET);
227    }
228
229    if (is_processor_irq(irq->name)) {
230      /*
231       * Enable exception at processor level
232       */
233    }
234    /*
235     * Enable interrupt on device
236     */
237    irq->on(irq);
238
239    _CPU_ISR_Enable(level);
240
241    return 1;
242}
243
244int BSP_get_current_rtems_irq_handler   (rtems_irq_connect_data* irq)
245{
246     unsigned int level;
247
248     if (!isValidInterrupt(irq->name)) {
249      return 0;
250     }
251     _CPU_ISR_Disable(level);
252     *irq = rtems_hdl_tbl[irq->name];
253     _CPU_ISR_Enable(level);
254     return 1;
255}
256
257int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
258{
259   rtems_irq_connect_data *pchain= NULL, *vchain = NULL;
260    unsigned int level;
261
262    if (!isValidInterrupt(irq->name)) {
263      return 0;
264    }
265    /*
266     * Check if default handler is actually connected. If not issue an error.
267     * You must first get the current handler via i386_get_current_idt_entry
268     * and then disconnect it using i386_delete_idt_entry.
269     * RATIONALE : to always have the same transition by forcing the user
270     * to get the previous handler before accepting to disconnect.
271     */
272    _CPU_ISR_Disable(level);
273    if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
274      _CPU_ISR_Enable(level);
275      return 0;
276    }
277
278    if( (int)rtems_hdl_tbl[irq->name].next_handler != -1 )
279    {
280       int found = 0;
281
282       for( (pchain= NULL, vchain = &rtems_hdl_tbl[irq->name]);
283            (vchain->hdl != default_rtems_entry.hdl);
284            (pchain= vchain, vchain = (rtems_irq_connect_data*)vchain->next_handler) )
285       {
286          if( vchain->hdl == irq->hdl )
287          {
288             found= -1; break;
289          }
290       }
291
292       if( !found )
293       {
294          _CPU_ISR_Enable(level);
295          return 0;
296       }
297    }
298    else
299    {
300       if (rtems_hdl_tbl[irq->name].hdl != irq->hdl)
301       {
302          _CPU_ISR_Enable(level);
303         return 0;
304       }
305    }
306
307    if (is_isa_irq(irq->name)) {
308      /*
309       * disable interrupt at PIC level
310       */
311      BSP_irq_disable_at_i8259s (irq->name);
312    }
313    if (is_pci_irq(irq->name)) {
314      /*
315       * disable interrupt at OPENPIC level
316       */
317      openpic_disable_irq ((int) irq->name - BSP_PCI_IRQ_LOWEST_OFFSET);
318    }
319    if (is_processor_irq(irq->name)) {
320      /*
321       * disable exception at processor level
322       */
323    }
324
325    /*
326     * Disable interrupt on device
327     */
328    irq->off(irq);
329
330    /*
331     * restore the default irq value
332     */
333    if( !vchain )
334    {
335       /* single handler vector... */
336       rtems_hdl_tbl[irq->name] = default_rtems_entry;
337    }
338    else
339    {
340       if( pchain )
341       {
342          /* non-first handler being removed */
343          pchain->next_handler = vchain->next_handler;
344       }
345       else
346       {
347          /* first handler isn't malloc'ed, so just overwrite it.  Since
348          the contents of vchain are being struct copied, vchain itself
349          goes away */
350          rtems_hdl_tbl[irq->name]= *vchain;
351       }
352       free(vchain);
353    }
354
355    _CPU_ISR_Enable(level);
356
357    return 1;
358}
359
360/*
361 * ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------
362 */
363
364int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
365{
366    int i;
367    unsigned int level;
368   /*
369    * Store various code accelerators
370    */
371    internal_config             = config;
372    default_rtems_entry         = config->defaultEntry;
373    rtems_hdl_tbl               = config->irqHdlTbl;
374
375    _CPU_ISR_Disable(level);
376    /*
377     * set up internal tables used by rtems interrupt prologue
378     */
379    /*
380     * start with ISA IRQ
381     */
382    compute_i8259_masks_from_prio ();
383
384    for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
385      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
386         BSP_irq_enable_at_i8259s (i);
387
388         /* rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); */
389         {
390            rtems_irq_connect_data* vchain;
391            for( vchain = &rtems_hdl_tbl[i];
392                 ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
393                 vchain = (rtems_irq_connect_data*)vchain->next_handler )
394            {
395               vchain->on(vchain);
396            }
397         }
398      }
399      else {
400         /* rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); */
401         {
402            rtems_irq_connect_data* vchain;
403            for( vchain = &rtems_hdl_tbl[i];
404                 ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
405                 vchain = (rtems_irq_connect_data*)vchain->next_handler )
406            {
407               vchain->off(vchain);
408            }
409         }
410         BSP_irq_disable_at_i8259s (i);
411      }
412    }
413    /*
414     * must enable slave pic anyway
415     */
416    BSP_irq_enable_at_i8259s (2);
417    /*
418     * continue with PCI IRQ
419     */
420    for (i=BSP_PCI_IRQ_LOWEST_OFFSET; i < BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER ; i++) {
421      /*
422       * Note that openpic_set_priority() sets the TASK priority of the PIC
423       */
424      openpic_set_source_priority(i - BSP_PCI_IRQ_LOWEST_OFFSET,
425                                  internal_config->irqPrioTbl[i]);
426      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
427         openpic_enable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET);
428         /* rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); */
429         {
430            rtems_irq_connect_data* vchain;
431            for( vchain = &rtems_hdl_tbl[i];
432                 ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
433                 vchain = (rtems_irq_connect_data*)vchain->next_handler )
434            {
435               vchain->on(vchain);
436            }
437         }
438
439      }
440      else {
441         /* rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); */
442         {
443            rtems_irq_connect_data* vchain;
444            for( vchain = &rtems_hdl_tbl[i];
445                 ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
446                 vchain = (rtems_irq_connect_data*)vchain->next_handler )
447            {
448               vchain->off(vchain);
449            }
450         }
451
452         openpic_disable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET);
453      }
454    }
455    /*
456     * Must enable PCI/ISA bridge IRQ
457     */
458    openpic_enable_irq (0);
459    /*
460     * finish with Processor exceptions handled like IRQ
461     */
462    for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER; i++) {
463      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
464         /* rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); */
465         {
466            rtems_irq_connect_data* vchain;
467            for( vchain = &rtems_hdl_tbl[i];
468                 ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
469                 vchain = (rtems_irq_connect_data*)vchain->next_handler )
470            {
471               vchain->on(vchain);
472            }
473         }
474
475      }
476      else {
477         /* rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); */
478         {
479            rtems_irq_connect_data* vchain;
480            for( vchain = &rtems_hdl_tbl[i];
481                 ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
482                 vchain = (rtems_irq_connect_data*)vchain->next_handler )
483            {
484               vchain->off(vchain);
485            }
486         }
487
488      }
489    }
490    _CPU_ISR_Enable(level);
491    return 1;
492}
493
494int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)
495{
496    *config = internal_config;
497    return 0;
498}
499
500int _BSP_vme_bridge_irq = -1;
501
502unsigned BSP_spuriousIntr = 0;
503/*
504 * High level IRQ handler called from shared_raw_irq_code_entry
505 */
506void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
507{
508  register unsigned int irq;
509  register unsigned isaIntr;                  /* boolean */
510  register unsigned oldMask = 0;              /* old isa pic masks */
511  register unsigned newMask;                  /* new isa pic masks */
512  register unsigned msr;
513  register unsigned new_msr;
514
515  if (excNum == ASM_DEC_VECTOR) {
516    _CPU_MSR_GET(msr);
517    new_msr = msr | MSR_EE;
518    _CPU_MSR_SET(new_msr);
519
520    rtems_hdl_tbl[BSP_DECREMENTER].hdl();
521
522    _CPU_MSR_SET(msr);
523    return;
524
525  }
526  irq = openpic_irq(0);
527  if (irq == OPENPIC_VEC_SPURIOUS) {
528    ++BSP_spuriousIntr;
529    return;
530  }
531  isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ);
532  if (isaIntr)  {
533    /*
534     * Acknowledge and read 8259 vector
535     */
536    irq = (unsigned int) (*(unsigned char *) RAVEN_INTR_ACK_REG);
537    /*
538     * store current PIC mask
539     */
540    oldMask = i8259s_cache;
541    newMask = oldMask | irq_mask_or_tbl [irq];
542    i8259s_cache = newMask;
543    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
544    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
545    BSP_irq_ack_at_i8259s (irq);
546    openpic_eoi(0);
547  }
548  _CPU_MSR_GET(msr);
549  new_msr = msr | MSR_EE;
550  _CPU_MSR_SET(new_msr);
551
552  /* rtems_hdl_tbl[irq].hdl(); */
553  {
554     rtems_irq_connect_data* vchain;
555     for( vchain = &rtems_hdl_tbl[irq];
556          ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
557          vchain = (rtems_irq_connect_data*)vchain->next_handler )
558     {
559        vchain->hdl();
560     }
561  }
562
563  _CPU_MSR_SET(msr);
564
565  if (isaIntr)  {
566    i8259s_cache = oldMask;
567    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
568    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
569  }
570  else {
571#ifdef BSP_PCI_VME_DRIVER_DOES_EOI
572        /* leave it to the VME bridge driver to do EOI, so
573     * it can re-enable the openpic while handling
574     * VME interrupts (-> VME priorities in software)
575         */
576        if (_BSP_vme_bridge_irq != irq)
577#endif
578                openpic_eoi(0);
579  }
580}
581
582void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
583{
584  /*
585   * Process pending signals that have not already been
586   * processed by _Thread_Displatch. This happens quite
587   * unfrequently : the ISR must have posted an action
588   * to the current running thread.
589   */
590  if ( _Thread_Do_post_task_switch_extension ||
591       _Thread_Executing->do_post_task_switch_extension ) {
592    _Thread_Executing->do_post_task_switch_extension = FALSE;
593    _API_extensions_Run_postswitch();
594  }
595  /*
596   * I plan to process other thread related events here.
597   * This will include DEBUG session requested from keyboard...
598   */
599}
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