1 | /* |
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2 | * |
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3 | * This file contains the implementation of the function described in irq.h |
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4 | * |
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5 | * Copyright (C) 1998, 1999 valette@crf.canon.fr |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in found in the file LICENSE in this distribution or at |
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9 | * http://www.OARcorp.com/rtems/license.html. |
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10 | * |
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11 | * $Id$ |
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12 | */ |
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13 | |
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14 | #include <rtems/system.h> |
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15 | #include <bsp.h> |
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16 | #include <bsp/irq.h> |
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17 | #include <bsp/VME.h> |
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18 | #include <bsp/openpic.h> |
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19 | #include <rtems/score/thread.h> |
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20 | #include <rtems/score/apiext.h> |
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21 | #include <libcpu/raw_exception.h> |
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22 | #include <libcpu/io.h> |
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23 | #include <bsp/vectors.h> |
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24 | |
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25 | #include <rtems/bspIo.h> /* for printk */ |
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26 | #define RAVEN_INTR_ACK_REG 0xfeff0030 |
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27 | |
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28 | /* |
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29 | * pointer to the mask representing the additionnal irq vectors |
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30 | * that must be disabled when a particular entry is activated. |
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31 | * They will be dynamically computed from teh prioruty table given |
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32 | * in BSP_rtems_irq_mngt_set(); |
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33 | * CAUTION : this table is accessed directly by interrupt routine |
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34 | * prologue. |
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35 | */ |
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36 | rtems_i8259_masks irq_mask_or_tbl[BSP_IRQ_NUMBER]; |
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37 | /* |
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38 | * default handler connected on each irq after bsp initialization |
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39 | */ |
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40 | static rtems_irq_connect_data default_rtems_entry; |
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41 | |
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42 | /* |
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43 | * location used to store initial tables used for interrupt |
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44 | * management. |
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45 | */ |
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46 | static rtems_irq_global_settings* internal_config; |
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47 | static rtems_irq_connect_data* rtems_hdl_tbl; |
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48 | |
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49 | /* |
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50 | * Check if IRQ is an ISA IRQ |
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51 | */ |
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52 | static inline int is_isa_irq(const rtems_irq_symbolic_name irqLine) |
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53 | { |
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54 | return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) & |
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55 | ((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET) |
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56 | ); |
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57 | } |
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58 | |
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59 | /* |
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60 | * Check if IRQ is an OPENPIC IRQ |
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61 | */ |
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62 | static inline int is_pci_irq(const rtems_irq_symbolic_name irqLine) |
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63 | { |
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64 | return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) & |
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65 | ((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET) |
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66 | ); |
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67 | } |
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68 | |
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69 | /* |
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70 | * Check if IRQ is a Porcessor IRQ |
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71 | */ |
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72 | static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine) |
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73 | { |
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74 | return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) & |
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75 | ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) |
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76 | ); |
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77 | } |
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78 | |
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79 | |
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80 | /* |
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81 | * ------------------------ RTEMS Irq helper functions ---------------- |
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82 | */ |
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83 | |
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84 | /* |
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85 | * Caution : this function assumes the variable "internal_config" |
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86 | * is already set and that the tables it contains are still valid |
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87 | * and accessible. |
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88 | */ |
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89 | static void compute_i8259_masks_from_prio () |
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90 | { |
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91 | int i; |
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92 | int j; |
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93 | /* |
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94 | * Always mask at least current interrupt to prevent re-entrance |
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95 | */ |
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96 | for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) { |
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97 | * ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i); |
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98 | for (j = BSP_ISA_IRQ_LOWEST_OFFSET; j < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; j++) { |
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99 | /* |
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100 | * Mask interrupts at i8259 level that have a lower priority |
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101 | */ |
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102 | if (internal_config->irqPrioTbl [i] > internal_config->irqPrioTbl [j]) { |
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103 | * ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j); |
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104 | } |
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105 | } |
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106 | } |
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107 | } |
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108 | |
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109 | /* |
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110 | * This function check that the value given for the irq line |
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111 | * is valid. |
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112 | */ |
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113 | |
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114 | static int isValidInterrupt(int irq) |
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115 | { |
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116 | if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET)) |
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117 | return 0; |
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118 | return 1; |
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119 | } |
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120 | |
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121 | /* |
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122 | * ------------------------ RTEMS Single Irq Handler Mngt Routines ---------------- |
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123 | */ |
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124 | |
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125 | int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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126 | { |
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127 | unsigned int level; |
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128 | |
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129 | if (!isValidInterrupt(irq->name)) { |
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130 | printk("Invalid interrupt vector %i\n",irq->name); |
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131 | return 0; |
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132 | } |
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133 | /* |
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134 | * Check if default handler is actually connected. If not issue an error. |
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135 | * You must first get the current handler via i386_get_current_idt_entry |
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136 | * and then disconnect it using i386_delete_idt_entry. |
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137 | * RATIONALE : to always have the same transition by forcing the user |
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138 | * to get the previous handler before accepting to disconnect. |
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139 | */ |
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140 | if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) { |
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141 | printk("IRQ vector %i already connected\n",irq->name); |
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142 | return 0; |
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143 | } |
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144 | _CPU_ISR_Disable(level); |
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145 | |
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146 | /* |
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147 | * store the data provided by user |
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148 | */ |
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149 | rtems_hdl_tbl[irq->name] = *irq; |
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150 | |
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151 | if (is_isa_irq(irq->name)) { |
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152 | /* |
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153 | * Enable interrupt at PIC level |
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154 | */ |
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155 | BSP_irq_enable_at_i8259s (irq->name); |
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156 | } |
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157 | |
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158 | if (is_pci_irq(irq->name)) { |
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159 | /* |
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160 | * Enable interrupt at OPENPIC level |
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161 | */ |
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162 | openpic_enable_irq ((int) irq->name - BSP_PCI_IRQ_LOWEST_OFFSET); |
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163 | } |
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164 | |
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165 | if (is_processor_irq(irq->name)) { |
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166 | /* |
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167 | * Enable exception at processor level |
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168 | */ |
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169 | } |
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170 | /* |
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171 | * Enable interrupt on device |
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172 | */ |
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173 | irq->on(irq); |
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174 | |
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175 | _CPU_ISR_Enable(level); |
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176 | |
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177 | return 1; |
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178 | } |
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179 | |
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180 | |
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181 | int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) |
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182 | { |
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183 | if (!isValidInterrupt(irq->name)) { |
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184 | return 0; |
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185 | } |
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186 | *irq = rtems_hdl_tbl[irq->name]; |
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187 | return 1; |
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188 | } |
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189 | |
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190 | int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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191 | { |
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192 | unsigned int level; |
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193 | |
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194 | if (!isValidInterrupt(irq->name)) { |
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195 | return 0; |
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196 | } |
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197 | /* |
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198 | * Check if default handler is actually connected. If not issue an error. |
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199 | * You must first get the current handler via i386_get_current_idt_entry |
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200 | * and then disconnect it using i386_delete_idt_entry. |
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201 | * RATIONALE : to always have the same transition by forcing the user |
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202 | * to get the previous handler before accepting to disconnect. |
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203 | */ |
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204 | if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) { |
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205 | return 0; |
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206 | } |
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207 | _CPU_ISR_Disable(level); |
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208 | |
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209 | if (is_isa_irq(irq->name)) { |
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210 | /* |
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211 | * disable interrupt at PIC level |
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212 | */ |
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213 | BSP_irq_disable_at_i8259s (irq->name); |
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214 | } |
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215 | if (is_pci_irq(irq->name)) { |
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216 | /* |
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217 | * disable interrupt at OPENPIC level |
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218 | */ |
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219 | openpic_disable_irq ((int) irq->name - BSP_PCI_IRQ_LOWEST_OFFSET); |
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220 | } |
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221 | if (is_processor_irq(irq->name)) { |
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222 | /* |
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223 | * disable exception at processor level |
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224 | */ |
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225 | } |
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226 | |
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227 | /* |
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228 | * Disable interrupt on device |
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229 | */ |
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230 | irq->off(irq); |
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231 | |
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232 | /* |
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233 | * restore the default irq value |
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234 | */ |
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235 | rtems_hdl_tbl[irq->name] = default_rtems_entry; |
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236 | |
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237 | _CPU_ISR_Enable(level); |
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238 | |
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239 | return 1; |
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240 | } |
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241 | |
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242 | /* |
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243 | * ------------------------ RTEMS Global Irq Handler Mngt Routines ---------------- |
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244 | */ |
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245 | |
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246 | int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) |
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247 | { |
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248 | int i; |
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249 | unsigned int level; |
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250 | /* |
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251 | * Store various code accelerators |
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252 | */ |
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253 | internal_config = config; |
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254 | default_rtems_entry = config->defaultEntry; |
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255 | rtems_hdl_tbl = config->irqHdlTbl; |
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256 | |
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257 | _CPU_ISR_Disable(level); |
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258 | /* |
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259 | * set up internal tables used by rtems interrupt prologue |
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260 | */ |
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261 | /* |
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262 | * start with ISA IRQ |
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263 | */ |
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264 | compute_i8259_masks_from_prio (); |
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265 | |
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266 | for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) { |
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267 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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268 | BSP_irq_enable_at_i8259s (i); |
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269 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
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270 | } |
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271 | else { |
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272 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
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273 | BSP_irq_disable_at_i8259s (i); |
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274 | } |
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275 | } |
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276 | /* |
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277 | * must enable slave pic anyway |
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278 | */ |
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279 | BSP_irq_enable_at_i8259s (2); |
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280 | /* |
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281 | * continue with PCI IRQ |
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282 | */ |
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283 | for (i=BSP_PCI_IRQ_LOWEST_OFFSET; i < BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER ; i++) { |
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284 | /* |
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285 | * Note that openpic_set_priority() sets the TASK priority of the PIC |
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286 | */ |
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287 | openpic_set_source_priority(i - BSP_PCI_IRQ_LOWEST_OFFSET, |
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288 | internal_config->irqPrioTbl[i]); |
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289 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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290 | openpic_enable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET); |
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291 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
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292 | } |
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293 | else { |
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294 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
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295 | openpic_disable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET); |
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296 | } |
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297 | } |
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298 | /* |
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299 | * Must enable PCI/ISA bridge IRQ |
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300 | */ |
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301 | openpic_enable_irq (0); |
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302 | /* |
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303 | * finish with Processor exceptions handled like IRQ |
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304 | */ |
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305 | for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER; i++) { |
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306 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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307 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
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308 | } |
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309 | else { |
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310 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
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311 | } |
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312 | } |
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313 | _CPU_ISR_Enable(level); |
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314 | return 1; |
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315 | } |
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316 | |
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317 | int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config) |
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318 | { |
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319 | *config = internal_config; |
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320 | return 0; |
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321 | } |
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322 | |
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323 | int _BSP_vme_bridge_irq = -1; |
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324 | |
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325 | unsigned spuriousIntr = 0; |
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326 | /* |
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327 | * High level IRQ handler called from shared_raw_irq_code_entry |
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328 | */ |
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329 | void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) |
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330 | { |
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331 | register unsigned int irq; |
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332 | register unsigned isaIntr; /* boolean */ |
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333 | register unsigned oldMask = 0; /* old isa pic masks */ |
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334 | register unsigned newMask; /* new isa pic masks */ |
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335 | register unsigned msr; |
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336 | register unsigned new_msr; |
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337 | |
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338 | |
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339 | if (excNum == ASM_DEC_VECTOR) { |
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340 | _CPU_MSR_GET(msr); |
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341 | new_msr = msr | MSR_EE; |
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342 | _CPU_MSR_SET(new_msr); |
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343 | |
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344 | rtems_hdl_tbl[BSP_DECREMENTER].hdl(); |
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345 | |
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346 | _CPU_MSR_SET(msr); |
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347 | return; |
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348 | |
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349 | } |
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350 | irq = openpic_irq(0); |
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351 | if (irq == OPENPIC_VEC_SPURIOUS) { |
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352 | ++BSP_spuriousIntr; |
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353 | return; |
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354 | } |
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355 | isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ); |
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356 | if (isaIntr) { |
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357 | /* |
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358 | * Acknowledge and read 8259 vector |
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359 | */ |
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360 | irq = (unsigned int) (*(unsigned char *) RAVEN_INTR_ACK_REG); |
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361 | /* |
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362 | * store current PIC mask |
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363 | */ |
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364 | oldMask = i8259s_cache; |
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365 | newMask = oldMask | irq_mask_or_tbl [irq]; |
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366 | i8259s_cache = newMask; |
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367 | outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); |
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368 | outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); |
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369 | BSP_irq_ack_at_i8259s (irq); |
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370 | openpic_eoi(0); |
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371 | } |
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372 | _CPU_MSR_GET(msr); |
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373 | new_msr = msr | MSR_EE; |
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374 | _CPU_MSR_SET(new_msr); |
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375 | |
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376 | rtems_hdl_tbl[irq].hdl(); |
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377 | |
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378 | _CPU_MSR_SET(msr); |
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379 | |
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380 | if (isaIntr) { |
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381 | i8259s_cache = oldMask; |
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382 | outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); |
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383 | outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); |
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384 | } |
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385 | else { |
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386 | #ifdef BSP_PCI_VME_DRIVER_DOES_EOI |
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387 | /* leave it to the VME bridge driver to do EOI, so |
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388 | * it can re-enable the openpic while handling |
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389 | * VME interrupts (-> VME priorities in software) |
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390 | */ |
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391 | if (_BSP_vme_bridge_irq != irq) |
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392 | #endif |
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393 | openpic_eoi(0); |
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394 | } |
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395 | } |
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396 | |
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397 | |
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398 | |
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399 | void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx) |
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400 | { |
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401 | /* |
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402 | * Process pending signals that have not already been |
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403 | * processed by _Thread_Displatch. This happens quite |
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404 | * unfrequently : the ISR must have posted an action |
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405 | * to the current running thread. |
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406 | */ |
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407 | if ( _Thread_Do_post_task_switch_extension || |
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408 | _Thread_Executing->do_post_task_switch_extension ) { |
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409 | _Thread_Executing->do_post_task_switch_extension = FALSE; |
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410 | _API_extensions_Run_postswitch(); |
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411 | } |
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412 | /* |
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413 | * I plan to process other thread related events here. |
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414 | * This will include DEBUG session requested from keyboard... |
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415 | */ |
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416 | } |
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