source: rtems/c/src/lib/libbsp/powerpc/shared/irq/irq.c @ 2742cc3

Last change on this file since 2742cc3 was 2742cc3, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 25, 2003 at 4:55:29 PM

2003-03-25 Till Straumann <strauman@…>

PR 360/bsps

  • irq/irq.c, irq/irq_init.c, openpic/openpic.c, openpic/openpic.h: BSP code had set the task priority register multiple times of the OpenPIC instead of setting the individual source priorities. This patch adds openpic_get_source_priority() and openpic_set_source_priority() calls and lets IRQ management code use them.
  • Property mode set to 100644
File size: 10.6 KB
Line 
1/*
2 *
3 *  This file contains the implementation of the function described in irq.h
4 *
5 *  Copyright (C) 1998, 1999 valette@crf.canon.fr
6 *
7 *  The license and distribution terms for this file may be
8 *  found in found in the file LICENSE in this distribution or at
9 *  http://www.OARcorp.com/rtems/license.html.
10 *
11 *  $Id$
12 */
13 
14#include <rtems/system.h>
15#include <bsp.h>
16#include <bsp/irq.h>
17#include <bsp/VME.h>
18#include <bsp/openpic.h>
19#include <rtems/score/thread.h>
20#include <rtems/score/apiext.h>
21#include <libcpu/raw_exception.h>
22#include <libcpu/io.h>
23#include <bsp/vectors.h>
24
25#include <rtems/bspIo.h> /* for printk */
26#define RAVEN_INTR_ACK_REG 0xfeff0030
27
28/*
29 * pointer to the mask representing the additionnal irq vectors
30 * that must be disabled when a particular entry is activated.
31 * They will be dynamically computed from teh prioruty table given
32 * in BSP_rtems_irq_mngt_set();
33 * CAUTION : this table is accessed directly by interrupt routine
34 *           prologue.
35 */
36rtems_i8259_masks       irq_mask_or_tbl[BSP_IRQ_NUMBER];
37/*
38 * default handler connected on each irq after bsp initialization
39 */
40static rtems_irq_connect_data   default_rtems_entry;
41
42/*
43 * location used to store initial tables used for interrupt
44 * management.
45 */
46static rtems_irq_global_settings*       internal_config;
47static rtems_irq_connect_data*          rtems_hdl_tbl;
48
49/*
50 * Check if IRQ is an ISA IRQ
51 */
52static inline int is_isa_irq(const rtems_irq_symbolic_name irqLine)
53{
54  return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) &
55          ((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET)
56         );
57}
58
59/*
60 * Check if IRQ is an OPENPIC IRQ
61 */
62static inline int is_pci_irq(const rtems_irq_symbolic_name irqLine)
63{
64  return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) &
65          ((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET)
66         );
67}
68
69/*
70 * Check if IRQ is a Porcessor IRQ
71 */
72static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine)
73{
74  return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) &
75          ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
76         );
77}
78
79
80/*
81 * ------------------------ RTEMS Irq helper functions ----------------
82 */
83 
84/*
85 * Caution : this function assumes the variable "internal_config"
86 * is already set and that the tables it contains are still valid
87 * and accessible.
88 */
89static void compute_i8259_masks_from_prio ()
90{
91  int i;
92  int j;
93  /*
94   * Always mask at least current interrupt to prevent re-entrance
95   */
96  for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
97    * ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i);
98    for (j = BSP_ISA_IRQ_LOWEST_OFFSET; j < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; j++) {
99      /*
100       * Mask interrupts at i8259 level that have a lower priority
101       */
102      if (internal_config->irqPrioTbl [i] > internal_config->irqPrioTbl [j]) {
103        * ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j);
104      }
105    }
106  }
107}
108
109/*
110 * This function check that the value given for the irq line
111 * is valid.
112 */
113
114static int isValidInterrupt(int irq)
115{
116  if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET))
117    return 0;
118  return 1;
119}
120
121/*
122 * ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
123 */
124
125int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
126{
127    unsigned int level;
128 
129    if (!isValidInterrupt(irq->name)) {
130      printk("Invalid interrupt vector %i\n",irq->name);
131      return 0;
132    }
133    /*
134     * Check if default handler is actually connected. If not issue an error.
135     * You must first get the current handler via i386_get_current_idt_entry
136     * and then disconnect it using i386_delete_idt_entry.
137     * RATIONALE : to always have the same transition by forcing the user
138     * to get the previous handler before accepting to disconnect.
139     */
140    if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {
141      printk("IRQ vector %i already connected\n",irq->name);
142      return 0;
143    }
144    _CPU_ISR_Disable(level);
145
146    /*
147     * store the data provided by user
148     */
149    rtems_hdl_tbl[irq->name] = *irq;
150   
151    if (is_isa_irq(irq->name)) {
152      /*
153       * Enable interrupt at PIC level
154       */
155      BSP_irq_enable_at_i8259s (irq->name);
156    }
157   
158    if (is_pci_irq(irq->name)) {
159      /*
160       * Enable interrupt at OPENPIC level
161       */
162      openpic_enable_irq ((int) irq->name - BSP_PCI_IRQ_LOWEST_OFFSET);
163    }
164
165    if (is_processor_irq(irq->name)) {
166      /*
167       * Enable exception at processor level
168       */
169    }
170    /*
171     * Enable interrupt on device
172     */
173    irq->on(irq);
174   
175    _CPU_ISR_Enable(level);
176
177    return 1;
178}
179
180
181int BSP_get_current_rtems_irq_handler   (rtems_irq_connect_data* irq)
182{
183     if (!isValidInterrupt(irq->name)) {
184      return 0;
185     }
186     *irq = rtems_hdl_tbl[irq->name];
187     return 1;
188}
189
190int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
191{
192    unsigned int level;
193 
194    if (!isValidInterrupt(irq->name)) {
195      return 0;
196    }
197    /*
198     * Check if default handler is actually connected. If not issue an error.
199     * You must first get the current handler via i386_get_current_idt_entry
200     * and then disconnect it using i386_delete_idt_entry.
201     * RATIONALE : to always have the same transition by forcing the user
202     * to get the previous handler before accepting to disconnect.
203     */
204    if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
205      return 0;
206    }
207    _CPU_ISR_Disable(level);
208
209    if (is_isa_irq(irq->name)) {
210      /*
211       * disable interrupt at PIC level
212       */
213      BSP_irq_disable_at_i8259s (irq->name);
214    }
215    if (is_pci_irq(irq->name)) {
216      /*
217       * disable interrupt at OPENPIC level
218       */
219      openpic_disable_irq ((int) irq->name - BSP_PCI_IRQ_LOWEST_OFFSET);
220    }
221    if (is_processor_irq(irq->name)) {
222      /*
223       * disable exception at processor level
224       */
225    }   
226
227    /*
228     * Disable interrupt on device
229     */
230    irq->off(irq);
231
232    /*
233     * restore the default irq value
234     */
235    rtems_hdl_tbl[irq->name] = default_rtems_entry;
236
237    _CPU_ISR_Enable(level);
238
239    return 1;
240}
241
242/*
243 * ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------
244 */
245
246int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
247{
248    int i;
249    unsigned int level;
250   /*
251    * Store various code accelerators
252    */
253    internal_config             = config;
254    default_rtems_entry         = config->defaultEntry;
255    rtems_hdl_tbl               = config->irqHdlTbl;
256
257    _CPU_ISR_Disable(level);
258    /*
259     * set up internal tables used by rtems interrupt prologue
260     */
261    /*
262     * start with ISA IRQ
263     */
264    compute_i8259_masks_from_prio ();
265
266    for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
267      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
268        BSP_irq_enable_at_i8259s (i);
269        rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
270      }
271      else {
272        rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
273        BSP_irq_disable_at_i8259s (i);
274      }
275    }
276    /*
277     * must enable slave pic anyway
278     */
279    BSP_irq_enable_at_i8259s (2);
280    /*
281     * continue with PCI IRQ
282     */
283    for (i=BSP_PCI_IRQ_LOWEST_OFFSET; i < BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER ; i++) {
284      /*
285       * Note that openpic_set_priority() sets the TASK priority of the PIC
286       */
287      openpic_set_source_priority(i - BSP_PCI_IRQ_LOWEST_OFFSET,
288                                  internal_config->irqPrioTbl[i]);
289      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
290        openpic_enable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET);
291        rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
292      }
293      else {
294        rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
295        openpic_disable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET);
296      }
297    }
298    /*
299     * Must enable PCI/ISA bridge IRQ
300     */
301    openpic_enable_irq (0);
302    /*
303     * finish with Processor exceptions handled like IRQ
304     */
305    for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER; i++) {
306      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
307        rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
308      }
309      else {
310        rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
311      }
312    }
313    _CPU_ISR_Enable(level);
314    return 1;
315}
316
317int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)
318{
319    *config = internal_config;
320    return 0;
321}   
322
323int _BSP_vme_bridge_irq = -1;
324 
325unsigned spuriousIntr = 0;
326/*
327 * High level IRQ handler called from shared_raw_irq_code_entry
328 */
329void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
330{
331  register unsigned int irq;
332  register unsigned isaIntr;                  /* boolean */
333  register unsigned oldMask = 0;              /* old isa pic masks */
334  register unsigned newMask;                  /* new isa pic masks */
335  register unsigned msr;
336  register unsigned new_msr;
337
338
339  if (excNum == ASM_DEC_VECTOR) {
340    _CPU_MSR_GET(msr);
341    new_msr = msr | MSR_EE;
342    _CPU_MSR_SET(new_msr);
343   
344    rtems_hdl_tbl[BSP_DECREMENTER].hdl();
345
346    _CPU_MSR_SET(msr);
347    return;
348   
349  }
350  irq = openpic_irq(0);
351  if (irq == OPENPIC_VEC_SPURIOUS) {
352    ++BSP_spuriousIntr;
353    return;
354  }
355  isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ);
356  if (isaIntr)  {
357    /*
358     * Acknowledge and read 8259 vector
359     */
360    irq = (unsigned int) (*(unsigned char *) RAVEN_INTR_ACK_REG);
361    /*
362     * store current PIC mask
363     */
364    oldMask = i8259s_cache;
365    newMask = oldMask | irq_mask_or_tbl [irq];
366    i8259s_cache = newMask;
367    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
368    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
369    BSP_irq_ack_at_i8259s (irq);
370    openpic_eoi(0);
371  }
372  _CPU_MSR_GET(msr);
373  new_msr = msr | MSR_EE;
374  _CPU_MSR_SET(new_msr);
375   
376  rtems_hdl_tbl[irq].hdl();
377
378  _CPU_MSR_SET(msr);
379
380  if (isaIntr)  {
381    i8259s_cache = oldMask;
382    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
383    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
384  }
385  else {
386#ifdef BSP_PCI_VME_DRIVER_DOES_EOI
387        /* leave it to the VME bridge driver to do EOI, so
388     * it can re-enable the openpic while handling
389     * VME interrupts (-> VME priorities in software)
390         */
391        if (_BSP_vme_bridge_irq != irq)
392#endif
393                openpic_eoi(0);
394  }
395}
396   
397   
398 
399void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
400{
401  /*
402   * Process pending signals that have not already been
403   * processed by _Thread_Displatch. This happens quite
404   * unfrequently : the ISR must have posted an action
405   * to the current running thread.
406   */
407  if ( _Thread_Do_post_task_switch_extension ||
408       _Thread_Executing->do_post_task_switch_extension ) {
409    _Thread_Executing->do_post_task_switch_extension = FALSE;
410    _API_extensions_Run_postswitch();
411  }
412  /*
413   * I plan to process other thread related events here.
414   * This will include DEBUG session requested from keyboard...
415   */
416}
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