[acc25ee] | 1 | /* |
---|
| 2 | * |
---|
| 3 | * This file contains the implementation of the function described in irq.h |
---|
| 4 | * |
---|
| 5 | * Copyright (C) 1998, 1999 valette@crf.canon.fr |
---|
| 6 | * |
---|
| 7 | * The license and distribution terms for this file may be |
---|
| 8 | * found in found in the file LICENSE in this distribution or at |
---|
| 9 | * http://www.OARcorp.com/rtems/license.html. |
---|
| 10 | * |
---|
| 11 | * $Id$ |
---|
| 12 | */ |
---|
| 13 | |
---|
[cd35cf9] | 14 | #include <rtems/system.h> |
---|
[acc25ee] | 15 | #include <bsp.h> |
---|
| 16 | #include <bsp/irq.h> |
---|
[4f3e4f33] | 17 | #include <bsp/VME.h> |
---|
[acc25ee] | 18 | #include <bsp/openpic.h> |
---|
| 19 | #include <rtems/score/thread.h> |
---|
| 20 | #include <rtems/score/apiext.h> |
---|
| 21 | #include <libcpu/raw_exception.h> |
---|
| 22 | #include <bsp/vectors.h> |
---|
| 23 | |
---|
[69ed59f] | 24 | #include <rtems/bspIo.h> /* for printk */ |
---|
[acc25ee] | 25 | #define RAVEN_INTR_ACK_REG 0xfeff0030 |
---|
| 26 | |
---|
| 27 | /* |
---|
| 28 | * pointer to the mask representing the additionnal irq vectors |
---|
| 29 | * that must be disabled when a particular entry is activated. |
---|
| 30 | * They will be dynamically computed from teh prioruty table given |
---|
| 31 | * in BSP_rtems_irq_mngt_set(); |
---|
| 32 | * CAUTION : this table is accessed directly by interrupt routine |
---|
| 33 | * prologue. |
---|
| 34 | */ |
---|
| 35 | rtems_i8259_masks irq_mask_or_tbl[BSP_IRQ_NUMBER]; |
---|
| 36 | /* |
---|
| 37 | * default handler connected on each irq after bsp initialization |
---|
| 38 | */ |
---|
| 39 | static rtems_irq_connect_data default_rtems_entry; |
---|
| 40 | |
---|
| 41 | /* |
---|
| 42 | * location used to store initial tables used for interrupt |
---|
| 43 | * management. |
---|
| 44 | */ |
---|
| 45 | static rtems_irq_global_settings* internal_config; |
---|
| 46 | static rtems_irq_connect_data* rtems_hdl_tbl; |
---|
| 47 | |
---|
| 48 | /* |
---|
| 49 | * Check if IRQ is an ISA IRQ |
---|
| 50 | */ |
---|
| 51 | static inline int is_isa_irq(const rtems_irq_symbolic_name irqLine) |
---|
| 52 | { |
---|
| 53 | return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) & |
---|
| 54 | ((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET) |
---|
| 55 | ); |
---|
| 56 | } |
---|
| 57 | |
---|
| 58 | /* |
---|
| 59 | * Check if IRQ is an OPENPIC IRQ |
---|
| 60 | */ |
---|
| 61 | static inline int is_pci_irq(const rtems_irq_symbolic_name irqLine) |
---|
| 62 | { |
---|
| 63 | return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) & |
---|
| 64 | ((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET) |
---|
| 65 | ); |
---|
| 66 | } |
---|
| 67 | |
---|
| 68 | /* |
---|
| 69 | * Check if IRQ is a Porcessor IRQ |
---|
| 70 | */ |
---|
| 71 | static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine) |
---|
| 72 | { |
---|
| 73 | return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) & |
---|
| 74 | ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) |
---|
| 75 | ); |
---|
| 76 | } |
---|
| 77 | |
---|
| 78 | |
---|
| 79 | /* |
---|
| 80 | * ------------------------ RTEMS Irq helper functions ---------------- |
---|
| 81 | */ |
---|
| 82 | |
---|
| 83 | /* |
---|
| 84 | * Caution : this function assumes the variable "internal_config" |
---|
| 85 | * is already set and that the tables it contains are still valid |
---|
| 86 | * and accessible. |
---|
| 87 | */ |
---|
| 88 | static void compute_i8259_masks_from_prio () |
---|
| 89 | { |
---|
[4f3e4f33] | 90 | int i; |
---|
| 91 | int j; |
---|
[acc25ee] | 92 | /* |
---|
| 93 | * Always mask at least current interrupt to prevent re-entrance |
---|
| 94 | */ |
---|
[4f3e4f33] | 95 | for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) { |
---|
[acc25ee] | 96 | * ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i); |
---|
[4f3e4f33] | 97 | for (j = BSP_ISA_IRQ_LOWEST_OFFSET; j < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; j++) { |
---|
[acc25ee] | 98 | /* |
---|
| 99 | * Mask interrupts at i8259 level that have a lower priority |
---|
| 100 | */ |
---|
| 101 | if (internal_config->irqPrioTbl [i] > internal_config->irqPrioTbl [j]) { |
---|
| 102 | * ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j); |
---|
| 103 | } |
---|
| 104 | } |
---|
| 105 | } |
---|
| 106 | } |
---|
| 107 | |
---|
| 108 | /* |
---|
| 109 | * This function check that the value given for the irq line |
---|
| 110 | * is valid. |
---|
| 111 | */ |
---|
| 112 | |
---|
| 113 | static int isValidInterrupt(int irq) |
---|
| 114 | { |
---|
| 115 | if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET)) |
---|
| 116 | return 0; |
---|
| 117 | return 1; |
---|
| 118 | } |
---|
| 119 | |
---|
| 120 | /* |
---|
| 121 | * ------------------------ RTEMS Single Irq Handler Mngt Routines ---------------- |
---|
| 122 | */ |
---|
| 123 | |
---|
| 124 | int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) |
---|
| 125 | { |
---|
| 126 | unsigned int level; |
---|
| 127 | |
---|
| 128 | if (!isValidInterrupt(irq->name)) { |
---|
[69ed59f] | 129 | printk("Invalid interrupt vector %i\n",irq->name); |
---|
[acc25ee] | 130 | return 0; |
---|
| 131 | } |
---|
| 132 | /* |
---|
| 133 | * Check if default handler is actually connected. If not issue an error. |
---|
| 134 | * You must first get the current handler via i386_get_current_idt_entry |
---|
| 135 | * and then disconnect it using i386_delete_idt_entry. |
---|
| 136 | * RATIONALE : to always have the same transition by forcing the user |
---|
| 137 | * to get the previous handler before accepting to disconnect. |
---|
| 138 | */ |
---|
| 139 | if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) { |
---|
[69ed59f] | 140 | printk("IRQ vector %i already connected\n",irq->name); |
---|
[acc25ee] | 141 | return 0; |
---|
| 142 | } |
---|
| 143 | _CPU_ISR_Disable(level); |
---|
| 144 | |
---|
| 145 | /* |
---|
| 146 | * store the data provided by user |
---|
| 147 | */ |
---|
| 148 | rtems_hdl_tbl[irq->name] = *irq; |
---|
| 149 | |
---|
| 150 | if (is_isa_irq(irq->name)) { |
---|
| 151 | /* |
---|
| 152 | * Enable interrupt at PIC level |
---|
| 153 | */ |
---|
| 154 | BSP_irq_enable_at_i8259s (irq->name); |
---|
| 155 | } |
---|
| 156 | |
---|
| 157 | if (is_pci_irq(irq->name)) { |
---|
| 158 | /* |
---|
| 159 | * Enable interrupt at OPENPIC level |
---|
| 160 | */ |
---|
| 161 | openpic_enable_irq ((int) irq->name - BSP_PCI_IRQ_LOWEST_OFFSET); |
---|
| 162 | } |
---|
| 163 | |
---|
| 164 | if (is_processor_irq(irq->name)) { |
---|
| 165 | /* |
---|
| 166 | * Enable exception at processor level |
---|
| 167 | */ |
---|
| 168 | } |
---|
| 169 | /* |
---|
| 170 | * Enable interrupt on device |
---|
| 171 | */ |
---|
| 172 | irq->on(irq); |
---|
| 173 | |
---|
| 174 | _CPU_ISR_Enable(level); |
---|
| 175 | |
---|
| 176 | return 1; |
---|
| 177 | } |
---|
| 178 | |
---|
| 179 | |
---|
| 180 | int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) |
---|
| 181 | { |
---|
| 182 | if (!isValidInterrupt(irq->name)) { |
---|
| 183 | return 0; |
---|
| 184 | } |
---|
| 185 | *irq = rtems_hdl_tbl[irq->name]; |
---|
| 186 | return 1; |
---|
| 187 | } |
---|
| 188 | |
---|
| 189 | int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) |
---|
| 190 | { |
---|
| 191 | unsigned int level; |
---|
| 192 | |
---|
| 193 | if (!isValidInterrupt(irq->name)) { |
---|
| 194 | return 0; |
---|
| 195 | } |
---|
| 196 | /* |
---|
| 197 | * Check if default handler is actually connected. If not issue an error. |
---|
| 198 | * You must first get the current handler via i386_get_current_idt_entry |
---|
| 199 | * and then disconnect it using i386_delete_idt_entry. |
---|
| 200 | * RATIONALE : to always have the same transition by forcing the user |
---|
| 201 | * to get the previous handler before accepting to disconnect. |
---|
| 202 | */ |
---|
| 203 | if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) { |
---|
| 204 | return 0; |
---|
| 205 | } |
---|
| 206 | _CPU_ISR_Disable(level); |
---|
| 207 | |
---|
| 208 | if (is_isa_irq(irq->name)) { |
---|
| 209 | /* |
---|
| 210 | * disable interrupt at PIC level |
---|
| 211 | */ |
---|
| 212 | BSP_irq_disable_at_i8259s (irq->name); |
---|
| 213 | } |
---|
| 214 | if (is_pci_irq(irq->name)) { |
---|
| 215 | /* |
---|
| 216 | * disable interrupt at OPENPIC level |
---|
| 217 | */ |
---|
| 218 | openpic_disable_irq ((int) irq->name - BSP_PCI_IRQ_LOWEST_OFFSET); |
---|
| 219 | } |
---|
| 220 | if (is_processor_irq(irq->name)) { |
---|
| 221 | /* |
---|
| 222 | * disable exception at processor level |
---|
| 223 | */ |
---|
| 224 | } |
---|
| 225 | |
---|
| 226 | /* |
---|
| 227 | * Disable interrupt on device |
---|
| 228 | */ |
---|
| 229 | irq->off(irq); |
---|
| 230 | |
---|
| 231 | /* |
---|
| 232 | * restore the default irq value |
---|
| 233 | */ |
---|
| 234 | rtems_hdl_tbl[irq->name] = default_rtems_entry; |
---|
| 235 | |
---|
| 236 | _CPU_ISR_Enable(level); |
---|
| 237 | |
---|
| 238 | return 1; |
---|
| 239 | } |
---|
| 240 | |
---|
| 241 | /* |
---|
| 242 | * ------------------------ RTEMS Global Irq Handler Mngt Routines ---------------- |
---|
| 243 | */ |
---|
| 244 | |
---|
| 245 | int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) |
---|
| 246 | { |
---|
| 247 | int i; |
---|
| 248 | unsigned int level; |
---|
| 249 | /* |
---|
| 250 | * Store various code accelerators |
---|
| 251 | */ |
---|
| 252 | internal_config = config; |
---|
| 253 | default_rtems_entry = config->defaultEntry; |
---|
| 254 | rtems_hdl_tbl = config->irqHdlTbl; |
---|
| 255 | |
---|
| 256 | _CPU_ISR_Disable(level); |
---|
| 257 | /* |
---|
| 258 | * set up internal tables used by rtems interrupt prologue |
---|
| 259 | */ |
---|
| 260 | /* |
---|
| 261 | * start with ISA IRQ |
---|
| 262 | */ |
---|
| 263 | compute_i8259_masks_from_prio (); |
---|
| 264 | |
---|
[4f3e4f33] | 265 | for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) { |
---|
[acc25ee] | 266 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
---|
| 267 | BSP_irq_enable_at_i8259s (i); |
---|
| 268 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
---|
| 269 | } |
---|
| 270 | else { |
---|
| 271 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
---|
| 272 | BSP_irq_disable_at_i8259s (i); |
---|
| 273 | } |
---|
| 274 | } |
---|
| 275 | /* |
---|
| 276 | * must enable slave pic anyway |
---|
| 277 | */ |
---|
| 278 | BSP_irq_enable_at_i8259s (2); |
---|
| 279 | /* |
---|
| 280 | * continue with PCI IRQ |
---|
| 281 | */ |
---|
| 282 | for (i=BSP_PCI_IRQ_LOWEST_OFFSET; i < BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER ; i++) { |
---|
| 283 | openpic_set_priority(0, internal_config->irqPrioTbl [i]); |
---|
| 284 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
---|
| 285 | openpic_enable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET); |
---|
| 286 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
---|
| 287 | } |
---|
| 288 | else { |
---|
| 289 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
---|
| 290 | openpic_disable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET); |
---|
| 291 | } |
---|
| 292 | } |
---|
| 293 | /* |
---|
| 294 | * Must enable PCI/ISA bridge IRQ |
---|
| 295 | */ |
---|
| 296 | openpic_enable_irq (0); |
---|
| 297 | /* |
---|
| 298 | * finish with Processor exceptions handled like IRQ |
---|
| 299 | */ |
---|
| 300 | for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER; i++) { |
---|
| 301 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
---|
| 302 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
---|
| 303 | } |
---|
| 304 | else { |
---|
| 305 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
---|
| 306 | } |
---|
| 307 | } |
---|
| 308 | _CPU_ISR_Enable(level); |
---|
| 309 | return 1; |
---|
| 310 | } |
---|
| 311 | |
---|
| 312 | int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config) |
---|
| 313 | { |
---|
| 314 | *config = internal_config; |
---|
| 315 | return 0; |
---|
| 316 | } |
---|
| 317 | |
---|
[de22321] | 318 | int _BSP_vme_bridge_irq = -1; |
---|
| 319 | |
---|
[acc25ee] | 320 | static unsigned spuriousIntr = 0; |
---|
| 321 | /* |
---|
| 322 | * High level IRQ handler called from shared_raw_irq_code_entry |
---|
| 323 | */ |
---|
| 324 | void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) |
---|
| 325 | { |
---|
| 326 | register unsigned int irq; |
---|
| 327 | register unsigned isaIntr; /* boolean */ |
---|
[7657233d] | 328 | register unsigned oldMask = 0; /* old isa pic masks */ |
---|
[acc25ee] | 329 | register unsigned newMask; /* new isa pic masks */ |
---|
| 330 | register unsigned msr; |
---|
| 331 | register unsigned new_msr; |
---|
| 332 | |
---|
| 333 | |
---|
| 334 | if (excNum == ASM_DEC_VECTOR) { |
---|
| 335 | _CPU_MSR_GET(msr); |
---|
| 336 | new_msr = msr | MSR_EE; |
---|
| 337 | _CPU_MSR_SET(new_msr); |
---|
| 338 | |
---|
| 339 | rtems_hdl_tbl[BSP_DECREMENTER].hdl(); |
---|
| 340 | |
---|
| 341 | _CPU_MSR_SET(msr); |
---|
| 342 | return; |
---|
| 343 | |
---|
| 344 | } |
---|
| 345 | irq = openpic_irq(0); |
---|
| 346 | if (irq == OPENPIC_VEC_SPURIOUS) { |
---|
| 347 | ++spuriousIntr; |
---|
| 348 | return; |
---|
| 349 | } |
---|
| 350 | isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ); |
---|
| 351 | if (isaIntr) { |
---|
| 352 | /* |
---|
| 353 | * Acknowledge and read 8259 vector |
---|
| 354 | */ |
---|
| 355 | irq = (unsigned int) (*(unsigned char *) RAVEN_INTR_ACK_REG); |
---|
| 356 | /* |
---|
| 357 | * store current PIC mask |
---|
| 358 | */ |
---|
| 359 | oldMask = i8259s_cache; |
---|
| 360 | newMask = oldMask | irq_mask_or_tbl [irq]; |
---|
| 361 | i8259s_cache = newMask; |
---|
| 362 | outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); |
---|
| 363 | outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); |
---|
| 364 | BSP_irq_ack_at_i8259s (irq); |
---|
| 365 | openpic_eoi(0); |
---|
| 366 | } |
---|
| 367 | _CPU_MSR_GET(msr); |
---|
| 368 | new_msr = msr | MSR_EE; |
---|
| 369 | _CPU_MSR_SET(new_msr); |
---|
| 370 | |
---|
| 371 | rtems_hdl_tbl[irq].hdl(); |
---|
| 372 | |
---|
| 373 | _CPU_MSR_SET(msr); |
---|
| 374 | |
---|
| 375 | if (isaIntr) { |
---|
| 376 | i8259s_cache = oldMask; |
---|
| 377 | outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); |
---|
| 378 | outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); |
---|
| 379 | } |
---|
| 380 | else { |
---|
[4f3e4f33] | 381 | #ifdef BSP_PCI_VME_DRIVER_DOES_EOI |
---|
| 382 | /* leave it to the VME bridge driver to do EOI, so |
---|
| 383 | * it can re-enable the openpic while handling |
---|
| 384 | * VME interrupts (-> VME priorities in software) |
---|
[69ed59f] | 385 | */ |
---|
[de22321] | 386 | if (_BSP_vme_bridge_irq != irq) |
---|
[69ed59f] | 387 | #endif |
---|
| 388 | openpic_eoi(0); |
---|
[acc25ee] | 389 | } |
---|
| 390 | } |
---|
| 391 | |
---|
| 392 | |
---|
| 393 | |
---|
| 394 | void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx) |
---|
| 395 | { |
---|
| 396 | /* |
---|
| 397 | * Process pending signals that have not already been |
---|
| 398 | * processed by _Thread_Displatch. This happens quite |
---|
| 399 | * unfrequently : the ISR must have posted an action |
---|
| 400 | * to the current running thread. |
---|
| 401 | */ |
---|
| 402 | if ( _Thread_Do_post_task_switch_extension || |
---|
| 403 | _Thread_Executing->do_post_task_switch_extension ) { |
---|
| 404 | _Thread_Executing->do_post_task_switch_extension = FALSE; |
---|
| 405 | _API_extensions_Run_postswitch(); |
---|
| 406 | } |
---|
| 407 | /* |
---|
| 408 | * I plan to process other thread related events here. |
---|
| 409 | * This will include DEBUG session requested from keyboard... |
---|
| 410 | */ |
---|
| 411 | } |
---|