[acc25ee] | 1 | /* |
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| 2 | * |
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| 3 | * This file contains the implementation of the function described in irq.h |
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| 4 | * |
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| 5 | * Copyright (C) 1998, 1999 valette@crf.canon.fr |
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| 6 | * |
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| 7 | * The license and distribution terms for this file may be |
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| 8 | * found in found in the file LICENSE in this distribution or at |
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| 9 | * http://www.OARcorp.com/rtems/license.html. |
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| 10 | * |
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| 11 | * $Id$ |
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| 12 | */ |
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| 13 | |
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[cd35cf9] | 14 | #include <rtems/system.h> |
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[acc25ee] | 15 | #include <bsp.h> |
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| 16 | #include <bsp/irq.h> |
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[e7625fc6] | 17 | #include <bsp/VME.h> |
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[acc25ee] | 18 | #include <bsp/openpic.h> |
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| 19 | #include <rtems/score/thread.h> |
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| 20 | #include <rtems/score/apiext.h> |
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| 21 | #include <libcpu/raw_exception.h> |
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[2742cc3] | 22 | #include <libcpu/io.h> |
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[acc25ee] | 23 | #include <bsp/vectors.h> |
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| 24 | |
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[69ed59f] | 25 | #include <rtems/bspIo.h> /* for printk */ |
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[acc25ee] | 26 | #define RAVEN_INTR_ACK_REG 0xfeff0030 |
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| 27 | |
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| 28 | /* |
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| 29 | * pointer to the mask representing the additionnal irq vectors |
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| 30 | * that must be disabled when a particular entry is activated. |
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| 31 | * They will be dynamically computed from teh prioruty table given |
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| 32 | * in BSP_rtems_irq_mngt_set(); |
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| 33 | * CAUTION : this table is accessed directly by interrupt routine |
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| 34 | * prologue. |
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| 35 | */ |
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| 36 | rtems_i8259_masks irq_mask_or_tbl[BSP_IRQ_NUMBER]; |
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| 37 | /* |
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| 38 | * default handler connected on each irq after bsp initialization |
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| 39 | */ |
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| 40 | static rtems_irq_connect_data default_rtems_entry; |
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| 41 | |
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| 42 | /* |
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| 43 | * location used to store initial tables used for interrupt |
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| 44 | * management. |
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| 45 | */ |
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| 46 | static rtems_irq_global_settings* internal_config; |
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| 47 | static rtems_irq_connect_data* rtems_hdl_tbl; |
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| 48 | |
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| 49 | /* |
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| 50 | * Check if IRQ is an ISA IRQ |
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| 51 | */ |
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| 52 | static inline int is_isa_irq(const rtems_irq_symbolic_name irqLine) |
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| 53 | { |
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| 54 | return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) & |
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| 55 | ((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET) |
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| 56 | ); |
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| 57 | } |
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| 58 | |
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| 59 | /* |
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| 60 | * Check if IRQ is an OPENPIC IRQ |
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| 61 | */ |
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| 62 | static inline int is_pci_irq(const rtems_irq_symbolic_name irqLine) |
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| 63 | { |
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| 64 | return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) & |
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| 65 | ((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET) |
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| 66 | ); |
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| 67 | } |
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| 68 | |
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| 69 | /* |
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| 70 | * Check if IRQ is a Porcessor IRQ |
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| 71 | */ |
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| 72 | static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine) |
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| 73 | { |
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| 74 | return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) & |
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| 75 | ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) |
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| 76 | ); |
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| 77 | } |
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| 78 | |
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| 79 | |
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| 80 | /* |
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| 81 | * ------------------------ RTEMS Irq helper functions ---------------- |
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| 82 | */ |
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| 83 | |
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| 84 | /* |
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| 85 | * Caution : this function assumes the variable "internal_config" |
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| 86 | * is already set and that the tables it contains are still valid |
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| 87 | * and accessible. |
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| 88 | */ |
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| 89 | static void compute_i8259_masks_from_prio () |
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| 90 | { |
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[e7625fc6] | 91 | int i; |
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| 92 | int j; |
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[acc25ee] | 93 | /* |
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| 94 | * Always mask at least current interrupt to prevent re-entrance |
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| 95 | */ |
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[e7625fc6] | 96 | for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) { |
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[acc25ee] | 97 | * ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i); |
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[e7625fc6] | 98 | for (j = BSP_ISA_IRQ_LOWEST_OFFSET; j < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; j++) { |
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[acc25ee] | 99 | /* |
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| 100 | * Mask interrupts at i8259 level that have a lower priority |
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| 101 | */ |
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| 102 | if (internal_config->irqPrioTbl [i] > internal_config->irqPrioTbl [j]) { |
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| 103 | * ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j); |
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| 104 | } |
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| 105 | } |
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| 106 | } |
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| 107 | } |
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| 108 | |
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| 109 | /* |
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| 110 | * This function check that the value given for the irq line |
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| 111 | * is valid. |
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| 112 | */ |
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| 113 | |
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| 114 | static int isValidInterrupt(int irq) |
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| 115 | { |
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| 116 | if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET)) |
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| 117 | return 0; |
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| 118 | return 1; |
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| 119 | } |
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| 120 | |
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[12838559] | 121 | |
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| 122 | /* |
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| 123 | * ------------------------ RTEMS Shared Irq Handler Mngt Routines ---------------- |
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| 124 | */ |
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| 125 | int BSP_install_rtems_shared_irq_handler (const rtems_irq_connect_data* irq) |
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| 126 | { |
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| 127 | unsigned int level; |
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| 128 | rtems_irq_connect_data* vchain; |
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| 129 | |
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| 130 | if (!isValidInterrupt(irq->name)) { |
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[3605c4e] | 131 | printk("Invalid interrupt vector %d\n",irq->name); |
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[12838559] | 132 | return 0; |
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| 133 | } |
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| 134 | if ( (int)rtems_hdl_tbl[irq->name].next_handler == -1 ) { |
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[3605c4e] | 135 | printk("IRQ vector %d already connected to an unshared handler\n",irq->name); |
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[12838559] | 136 | return 0; |
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| 137 | } |
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| 138 | _CPU_ISR_Disable(level); |
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| 139 | |
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| 140 | |
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| 141 | vchain = (rtems_irq_connect_data*)malloc(sizeof(rtems_irq_connect_data)); |
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| 142 | |
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| 143 | /* save off topmost handler */ |
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| 144 | vchain[0]= rtems_hdl_tbl[irq->name]; |
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| 145 | |
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| 146 | /* |
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| 147 | * store the data provided by user |
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| 148 | */ |
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| 149 | rtems_hdl_tbl[irq->name] = *irq; |
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| 150 | |
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| 151 | /* link chain to new topmost handler */ |
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| 152 | rtems_hdl_tbl[irq->name].next_handler = (void *)vchain; |
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| 153 | |
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| 154 | |
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| 155 | if (is_isa_irq(irq->name)) { |
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| 156 | /* |
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| 157 | * Enable interrupt at PIC level |
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| 158 | */ |
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| 159 | BSP_irq_enable_at_i8259s (irq->name); |
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| 160 | } |
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| 161 | |
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| 162 | if (is_pci_irq(irq->name)) { |
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| 163 | /* |
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| 164 | * Enable interrupt at OPENPIC level |
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| 165 | */ |
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| 166 | openpic_enable_irq ((int) irq->name - BSP_PCI_IRQ_LOWEST_OFFSET); |
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| 167 | } |
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| 168 | |
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| 169 | if (is_processor_irq(irq->name)) { |
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| 170 | /* |
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| 171 | * Enable exception at processor level |
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| 172 | */ |
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| 173 | } |
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| 174 | /* |
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| 175 | * Enable interrupt on device |
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| 176 | */ |
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| 177 | irq->on(irq); |
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| 178 | |
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| 179 | _CPU_ISR_Enable(level); |
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| 180 | |
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| 181 | return 1; |
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| 182 | } |
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| 183 | |
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| 184 | |
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[acc25ee] | 185 | /* |
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| 186 | * ------------------------ RTEMS Single Irq Handler Mngt Routines ---------------- |
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| 187 | */ |
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| 188 | |
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| 189 | int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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| 190 | { |
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| 191 | unsigned int level; |
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| 192 | |
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| 193 | if (!isValidInterrupt(irq->name)) { |
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[3605c4e] | 194 | printk("Invalid interrupt vector %d\n",irq->name); |
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[acc25ee] | 195 | return 0; |
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| 196 | } |
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| 197 | /* |
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| 198 | * Check if default handler is actually connected. If not issue an error. |
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| 199 | * You must first get the current handler via i386_get_current_idt_entry |
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| 200 | * and then disconnect it using i386_delete_idt_entry. |
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| 201 | * RATIONALE : to always have the same transition by forcing the user |
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| 202 | * to get the previous handler before accepting to disconnect. |
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| 203 | */ |
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| 204 | if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) { |
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[3605c4e] | 205 | printk("IRQ vector %d already connected\n",irq->name); |
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[acc25ee] | 206 | return 0; |
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| 207 | } |
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| 208 | _CPU_ISR_Disable(level); |
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| 209 | |
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| 210 | /* |
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| 211 | * store the data provided by user |
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| 212 | */ |
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| 213 | rtems_hdl_tbl[irq->name] = *irq; |
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[12838559] | 214 | rtems_hdl_tbl[irq->name].next_handler = (void *)-1; |
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[acc25ee] | 215 | |
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| 216 | if (is_isa_irq(irq->name)) { |
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| 217 | /* |
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| 218 | * Enable interrupt at PIC level |
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| 219 | */ |
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| 220 | BSP_irq_enable_at_i8259s (irq->name); |
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| 221 | } |
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| 222 | |
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| 223 | if (is_pci_irq(irq->name)) { |
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| 224 | /* |
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| 225 | * Enable interrupt at OPENPIC level |
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| 226 | */ |
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| 227 | openpic_enable_irq ((int) irq->name - BSP_PCI_IRQ_LOWEST_OFFSET); |
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| 228 | } |
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| 229 | |
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| 230 | if (is_processor_irq(irq->name)) { |
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| 231 | /* |
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| 232 | * Enable exception at processor level |
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| 233 | */ |
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| 234 | } |
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| 235 | /* |
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| 236 | * Enable interrupt on device |
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| 237 | */ |
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| 238 | irq->on(irq); |
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| 239 | |
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| 240 | _CPU_ISR_Enable(level); |
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| 241 | |
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| 242 | return 1; |
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| 243 | } |
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| 244 | |
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| 245 | |
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| 246 | int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) |
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| 247 | { |
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| 248 | if (!isValidInterrupt(irq->name)) { |
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| 249 | return 0; |
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| 250 | } |
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| 251 | *irq = rtems_hdl_tbl[irq->name]; |
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| 252 | return 1; |
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| 253 | } |
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| 254 | |
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| 255 | int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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| 256 | { |
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[12838559] | 257 | rtems_irq_connect_data *pchain= NULL, *vchain = NULL; |
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[acc25ee] | 258 | unsigned int level; |
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| 259 | |
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| 260 | if (!isValidInterrupt(irq->name)) { |
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| 261 | return 0; |
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| 262 | } |
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| 263 | /* |
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| 264 | * Check if default handler is actually connected. If not issue an error. |
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| 265 | * You must first get the current handler via i386_get_current_idt_entry |
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| 266 | * and then disconnect it using i386_delete_idt_entry. |
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| 267 | * RATIONALE : to always have the same transition by forcing the user |
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| 268 | * to get the previous handler before accepting to disconnect. |
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| 269 | */ |
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| 270 | if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) { |
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| 271 | return 0; |
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| 272 | } |
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| 273 | _CPU_ISR_Disable(level); |
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| 274 | |
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[12838559] | 275 | if( (int)rtems_hdl_tbl[irq->name].next_handler != -1 ) |
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| 276 | { |
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| 277 | int found = 0; |
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| 278 | |
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| 279 | for( (pchain= NULL, vchain = &rtems_hdl_tbl[irq->name]); |
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| 280 | (vchain->hdl != default_rtems_entry.hdl); |
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| 281 | (pchain= vchain, vchain = (rtems_irq_connect_data*)vchain->next_handler) ) |
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| 282 | { |
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| 283 | if( vchain->hdl == irq->hdl ) |
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| 284 | { |
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| 285 | found= -1; break; |
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| 286 | } |
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| 287 | } |
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| 288 | |
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| 289 | if( !found ) |
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| 290 | { |
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| 291 | _CPU_ISR_Enable(level); |
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| 292 | return 0; |
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| 293 | } |
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| 294 | } |
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| 295 | else |
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| 296 | { |
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| 297 | if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) |
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| 298 | { |
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| 299 | _CPU_ISR_Enable(level); |
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| 300 | return 0; |
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| 301 | } |
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| 302 | } |
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| 303 | |
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[acc25ee] | 304 | if (is_isa_irq(irq->name)) { |
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| 305 | /* |
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| 306 | * disable interrupt at PIC level |
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| 307 | */ |
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| 308 | BSP_irq_disable_at_i8259s (irq->name); |
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| 309 | } |
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| 310 | if (is_pci_irq(irq->name)) { |
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| 311 | /* |
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| 312 | * disable interrupt at OPENPIC level |
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| 313 | */ |
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| 314 | openpic_disable_irq ((int) irq->name - BSP_PCI_IRQ_LOWEST_OFFSET); |
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| 315 | } |
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| 316 | if (is_processor_irq(irq->name)) { |
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| 317 | /* |
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| 318 | * disable exception at processor level |
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| 319 | */ |
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| 320 | } |
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| 321 | |
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| 322 | /* |
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| 323 | * Disable interrupt on device |
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| 324 | */ |
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| 325 | irq->off(irq); |
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| 326 | |
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| 327 | /* |
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| 328 | * restore the default irq value |
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| 329 | */ |
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[12838559] | 330 | if( !vchain ) |
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| 331 | { |
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| 332 | /* single handler vector... */ |
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| 333 | rtems_hdl_tbl[irq->name] = default_rtems_entry; |
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| 334 | } |
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| 335 | else |
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| 336 | { |
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| 337 | if( pchain ) |
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| 338 | { |
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| 339 | /* non-first handler being removed */ |
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| 340 | pchain->next_handler = vchain->next_handler; |
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| 341 | } |
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| 342 | else |
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| 343 | { |
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| 344 | /* first handler isn't malloc'ed, so just overwrite it. Since |
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| 345 | the contents of vchain are being struct copied, vchain itself |
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| 346 | goes away */ |
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| 347 | rtems_hdl_tbl[irq->name]= *vchain; |
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| 348 | } |
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| 349 | free(vchain); |
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| 350 | } |
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[acc25ee] | 351 | |
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| 352 | _CPU_ISR_Enable(level); |
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| 353 | |
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| 354 | return 1; |
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| 355 | } |
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| 356 | |
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| 357 | /* |
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| 358 | * ------------------------ RTEMS Global Irq Handler Mngt Routines ---------------- |
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| 359 | */ |
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| 360 | |
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| 361 | int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) |
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| 362 | { |
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| 363 | int i; |
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| 364 | unsigned int level; |
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| 365 | /* |
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| 366 | * Store various code accelerators |
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| 367 | */ |
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| 368 | internal_config = config; |
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| 369 | default_rtems_entry = config->defaultEntry; |
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| 370 | rtems_hdl_tbl = config->irqHdlTbl; |
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| 371 | |
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| 372 | _CPU_ISR_Disable(level); |
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| 373 | /* |
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| 374 | * set up internal tables used by rtems interrupt prologue |
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| 375 | */ |
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| 376 | /* |
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| 377 | * start with ISA IRQ |
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| 378 | */ |
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| 379 | compute_i8259_masks_from_prio (); |
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| 380 | |
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[e7625fc6] | 381 | for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) { |
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[acc25ee] | 382 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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[12838559] | 383 | BSP_irq_enable_at_i8259s (i); |
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| 384 | |
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| 385 | /* rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); */ |
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| 386 | { |
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| 387 | rtems_irq_connect_data* vchain; |
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| 388 | for( vchain = &rtems_hdl_tbl[i]; |
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| 389 | ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); |
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| 390 | vchain = (rtems_irq_connect_data*)vchain->next_handler ) |
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| 391 | { |
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| 392 | vchain->on(vchain); |
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| 393 | } |
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| 394 | } |
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[acc25ee] | 395 | } |
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| 396 | else { |
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[12838559] | 397 | /* rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); */ |
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| 398 | { |
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| 399 | rtems_irq_connect_data* vchain; |
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| 400 | for( vchain = &rtems_hdl_tbl[i]; |
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| 401 | ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); |
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| 402 | vchain = (rtems_irq_connect_data*)vchain->next_handler ) |
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| 403 | { |
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| 404 | vchain->off(vchain); |
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| 405 | } |
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| 406 | } |
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| 407 | BSP_irq_disable_at_i8259s (i); |
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[acc25ee] | 408 | } |
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| 409 | } |
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| 410 | /* |
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| 411 | * must enable slave pic anyway |
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| 412 | */ |
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| 413 | BSP_irq_enable_at_i8259s (2); |
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| 414 | /* |
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| 415 | * continue with PCI IRQ |
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| 416 | */ |
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| 417 | for (i=BSP_PCI_IRQ_LOWEST_OFFSET; i < BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER ; i++) { |
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[2742cc3] | 418 | /* |
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| 419 | * Note that openpic_set_priority() sets the TASK priority of the PIC |
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| 420 | */ |
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| 421 | openpic_set_source_priority(i - BSP_PCI_IRQ_LOWEST_OFFSET, |
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| 422 | internal_config->irqPrioTbl[i]); |
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[acc25ee] | 423 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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[12838559] | 424 | openpic_enable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET); |
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| 425 | /* rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); */ |
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| 426 | { |
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| 427 | rtems_irq_connect_data* vchain; |
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| 428 | for( vchain = &rtems_hdl_tbl[i]; |
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| 429 | ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); |
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| 430 | vchain = (rtems_irq_connect_data*)vchain->next_handler ) |
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| 431 | { |
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| 432 | vchain->on(vchain); |
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| 433 | } |
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| 434 | } |
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| 435 | |
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[acc25ee] | 436 | } |
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| 437 | else { |
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[12838559] | 438 | /* rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); */ |
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| 439 | { |
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| 440 | rtems_irq_connect_data* vchain; |
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| 441 | for( vchain = &rtems_hdl_tbl[i]; |
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| 442 | ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); |
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| 443 | vchain = (rtems_irq_connect_data*)vchain->next_handler ) |
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| 444 | { |
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| 445 | vchain->off(vchain); |
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| 446 | } |
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| 447 | } |
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| 448 | |
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| 449 | openpic_disable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET); |
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[acc25ee] | 450 | } |
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| 451 | } |
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| 452 | /* |
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| 453 | * Must enable PCI/ISA bridge IRQ |
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| 454 | */ |
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| 455 | openpic_enable_irq (0); |
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| 456 | /* |
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| 457 | * finish with Processor exceptions handled like IRQ |
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| 458 | */ |
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| 459 | for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER; i++) { |
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| 460 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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[12838559] | 461 | /* rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); */ |
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| 462 | { |
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| 463 | rtems_irq_connect_data* vchain; |
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| 464 | for( vchain = &rtems_hdl_tbl[i]; |
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| 465 | ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); |
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| 466 | vchain = (rtems_irq_connect_data*)vchain->next_handler ) |
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| 467 | { |
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| 468 | vchain->on(vchain); |
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| 469 | } |
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| 470 | } |
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| 471 | |
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[acc25ee] | 472 | } |
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| 473 | else { |
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[12838559] | 474 | /* rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); */ |
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| 475 | { |
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| 476 | rtems_irq_connect_data* vchain; |
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| 477 | for( vchain = &rtems_hdl_tbl[i]; |
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| 478 | ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); |
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| 479 | vchain = (rtems_irq_connect_data*)vchain->next_handler ) |
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| 480 | { |
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| 481 | vchain->off(vchain); |
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| 482 | } |
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| 483 | } |
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| 484 | |
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[acc25ee] | 485 | } |
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| 486 | } |
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| 487 | _CPU_ISR_Enable(level); |
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| 488 | return 1; |
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| 489 | } |
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| 490 | |
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| 491 | int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config) |
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| 492 | { |
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| 493 | *config = internal_config; |
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| 494 | return 0; |
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| 495 | } |
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| 496 | |
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[a3ef256] | 497 | int _BSP_vme_bridge_irq = -1; |
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| 498 | |
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[2d8eddea] | 499 | unsigned BSP_spuriousIntr = 0; |
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[acc25ee] | 500 | /* |
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| 501 | * High level IRQ handler called from shared_raw_irq_code_entry |
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| 502 | */ |
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| 503 | void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) |
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| 504 | { |
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| 505 | register unsigned int irq; |
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| 506 | register unsigned isaIntr; /* boolean */ |
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[7657233d] | 507 | register unsigned oldMask = 0; /* old isa pic masks */ |
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[acc25ee] | 508 | register unsigned newMask; /* new isa pic masks */ |
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| 509 | register unsigned msr; |
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| 510 | register unsigned new_msr; |
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| 511 | |
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| 512 | |
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| 513 | if (excNum == ASM_DEC_VECTOR) { |
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| 514 | _CPU_MSR_GET(msr); |
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| 515 | new_msr = msr | MSR_EE; |
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| 516 | _CPU_MSR_SET(new_msr); |
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| 517 | |
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| 518 | rtems_hdl_tbl[BSP_DECREMENTER].hdl(); |
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| 519 | |
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| 520 | _CPU_MSR_SET(msr); |
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| 521 | return; |
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| 522 | |
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| 523 | } |
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| 524 | irq = openpic_irq(0); |
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| 525 | if (irq == OPENPIC_VEC_SPURIOUS) { |
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[2742cc3] | 526 | ++BSP_spuriousIntr; |
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[acc25ee] | 527 | return; |
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| 528 | } |
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| 529 | isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ); |
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| 530 | if (isaIntr) { |
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| 531 | /* |
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| 532 | * Acknowledge and read 8259 vector |
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| 533 | */ |
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| 534 | irq = (unsigned int) (*(unsigned char *) RAVEN_INTR_ACK_REG); |
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| 535 | /* |
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| 536 | * store current PIC mask |
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| 537 | */ |
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| 538 | oldMask = i8259s_cache; |
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| 539 | newMask = oldMask | irq_mask_or_tbl [irq]; |
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| 540 | i8259s_cache = newMask; |
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| 541 | outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); |
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| 542 | outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); |
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| 543 | BSP_irq_ack_at_i8259s (irq); |
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| 544 | openpic_eoi(0); |
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| 545 | } |
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| 546 | _CPU_MSR_GET(msr); |
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| 547 | new_msr = msr | MSR_EE; |
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| 548 | _CPU_MSR_SET(new_msr); |
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| 549 | |
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[12838559] | 550 | /* rtems_hdl_tbl[irq].hdl(); */ |
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| 551 | { |
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| 552 | rtems_irq_connect_data* vchain; |
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| 553 | for( vchain = &rtems_hdl_tbl[irq]; |
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| 554 | ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); |
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| 555 | vchain = (rtems_irq_connect_data*)vchain->next_handler ) |
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| 556 | { |
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| 557 | vchain->hdl(); |
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| 558 | } |
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| 559 | } |
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| 560 | |
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[acc25ee] | 561 | |
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| 562 | _CPU_MSR_SET(msr); |
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| 563 | |
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| 564 | if (isaIntr) { |
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| 565 | i8259s_cache = oldMask; |
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| 566 | outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); |
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| 567 | outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); |
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| 568 | } |
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| 569 | else { |
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[e7625fc6] | 570 | #ifdef BSP_PCI_VME_DRIVER_DOES_EOI |
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| 571 | /* leave it to the VME bridge driver to do EOI, so |
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| 572 | * it can re-enable the openpic while handling |
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| 573 | * VME interrupts (-> VME priorities in software) |
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[69ed59f] | 574 | */ |
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[a3ef256] | 575 | if (_BSP_vme_bridge_irq != irq) |
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[69ed59f] | 576 | #endif |
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| 577 | openpic_eoi(0); |
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[acc25ee] | 578 | } |
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| 579 | } |
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| 580 | |
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| 581 | |
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| 582 | |
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| 583 | void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx) |
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| 584 | { |
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| 585 | /* |
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| 586 | * Process pending signals that have not already been |
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| 587 | * processed by _Thread_Displatch. This happens quite |
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| 588 | * unfrequently : the ISR must have posted an action |
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| 589 | * to the current running thread. |
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| 590 | */ |
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| 591 | if ( _Thread_Do_post_task_switch_extension || |
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| 592 | _Thread_Executing->do_post_task_switch_extension ) { |
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| 593 | _Thread_Executing->do_post_task_switch_extension = FALSE; |
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| 594 | _API_extensions_Run_postswitch(); |
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| 595 | } |
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| 596 | /* |
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| 597 | * I plan to process other thread related events here. |
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| 598 | * This will include DEBUG session requested from keyboard... |
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| 599 | */ |
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| 600 | } |
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