source: rtems/c/src/lib/libbsp/powerpc/shared/irq/i8259.c @ a77cd066

4.104.114.84.95
Last change on this file since a77cd066 was e831de8, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 4, 2003 at 6:52:38 PM

2003-09-04 Joel Sherrill <joel@…>

  • bootloader/bootldr.h, bootloader/em86.c, bootloader/em86real.S, bootloader/exception.S, bootloader/head.S, bootloader/lib.c, bootloader/misc.c, bootloader/mm.c, bootloader/pci.c, clock/p_clock.c, console/console.c, console/consoleIo.h, console/inch.c, console/keyboard.h, console/polled_io.c, include/bsp.h, irq/i8259.c, irq/irq.c, irq/irq.h, irq/irq_asm.S, irq/irq_init.c, motorola/motorola.c, motorola/motorola.h, openpic/openpic.c, openpic/openpic.h, pci/pci.c, residual/residual.c, start/start.S, startup/bspstart.c, vectors/vectors.h, vectors/vectors_init.c: URL for license changed.
  • Property mode set to 100644
File size: 4.5 KB
Line 
1
2/*
3 *  This file contains the implementation of the function described in irq.h
4 *  related to Intel 8259 Programmable Interrupt controller.
5 *
6 *  Copyright (C) 1998, 1999 valette@crf.canon.fr
7 *
8 *  The license and distribution terms for this file may be
9 *  found in found in the file LICENSE in this distribution or at
10 *  http://www.rtems.com/license/LICENSE.
11 *
12 *  $Id$
13 */
14 
15#include <bsp.h>
16#include <bsp/irq.h>
17
18/*-------------------------------------------------------------------------+
19| Cache for 1st and 2nd PIC IRQ line's status (enabled or disabled) register.
20+--------------------------------------------------------------------------*/
21/*
22 * lower byte is interrupt mask on the master PIC.
23 * while upper bits are interrupt on the slave PIC.
24 */
25volatile rtems_i8259_masks i8259s_cache = 0xfffb;
26
27/*-------------------------------------------------------------------------+
28|         Function:  BSP_irq_disable_at_i8259s
29|      Description: Mask IRQ line in appropriate PIC chip.
30| Global Variables: i8259s_cache
31|        Arguments: vector_offset - number of IRQ line to mask.
32|          Returns: Nothing.
33+--------------------------------------------------------------------------*/
34int BSP_irq_disable_at_i8259s    (const rtems_irq_symbolic_name irqLine)
35{
36  unsigned short mask;
37  unsigned int  level;
38
39  if ( ((int)irqLine < BSP_ISA_IRQ_LOWEST_OFFSET) ||
40       ((int)irqLine > BSP_ISA_IRQ_MAX_OFFSET)
41       )
42    return 1;
43 
44  _CPU_ISR_Disable(level);
45 
46  mask = 1 << irqLine;
47  i8259s_cache |= mask;
48 
49  if (irqLine < 8)
50  {
51    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
52  }
53  else
54  {
55    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
56  }
57  _CPU_ISR_Enable (level);
58
59  return 0;
60} 
61
62/*-------------------------------------------------------------------------+
63|         Function:  BSP_irq_enable_at_i8259s
64|      Description: Unmask IRQ line in appropriate PIC chip.
65| Global Variables: i8259s_cache
66|        Arguments: irqLine - number of IRQ line to mask.
67|          Returns: Nothing.
68+--------------------------------------------------------------------------*/
69int BSP_irq_enable_at_i8259s    (const rtems_irq_symbolic_name irqLine)
70{
71  unsigned short mask;
72  unsigned int  level;
73
74  if ( ((int)irqLine < BSP_ISA_IRQ_LOWEST_OFFSET) ||
75       ((int)irqLine > BSP_ISA_IRQ_MAX_OFFSET )
76       )
77    return 1;
78
79  _CPU_ISR_Disable(level);
80 
81  mask = ~(1 << irqLine);
82  i8259s_cache &= mask;
83 
84  if (irqLine < 8)
85  {
86    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
87  }
88  else
89  {
90    outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
91  }
92  _CPU_ISR_Enable (level);
93
94  return 0;
95} /* mask_irq */
96
97int BSP_irq_enabled_at_i8259s           (const rtems_irq_symbolic_name irqLine)
98{
99  unsigned short mask;
100
101  if ( ((int)irqLine < BSP_ISA_IRQ_LOWEST_OFFSET) ||
102       ((int)irqLine > BSP_ISA_IRQ_MAX_OFFSET)
103     )
104    return 1;
105
106  mask = (1 << irqLine);
107  return  (~(i8259s_cache & mask));
108}
109 
110
111/*-------------------------------------------------------------------------+
112|         Function: BSP_irq_ack_at_i8259s
113|      Description: Signal generic End Of Interrupt (EOI) to appropriate PIC.
114| Global Variables: None.
115|        Arguments: irqLine - number of IRQ line to acknowledge.
116|          Returns: Nothing.
117+--------------------------------------------------------------------------*/
118int BSP_irq_ack_at_i8259s       (const rtems_irq_symbolic_name irqLine)
119{
120  if (irqLine >= 8) {
121    outport_byte(PIC_MASTER_COMMAND_IO_PORT, SLAVE_PIC_EOSI);
122    outport_byte(PIC_SLAVE_COMMAND_IO_PORT, (PIC_EOSI | (irqLine - 8)));
123  }
124  else {
125    outport_byte(PIC_MASTER_COMMAND_IO_PORT, (PIC_EOSI | irqLine));
126  }
127
128  return 0;
129
130} /* ackIRQ */
131
132void BSP_i8259s_init(void)
133{
134  /*
135   * init master 8259 interrupt controller
136   */
137  outport_byte(PIC_MASTER_COMMAND_IO_PORT, 0x11); /* Start init sequence */
138  outport_byte(PIC_MASTER_IMR_IO_PORT, 0x00);/* Vector base  = 0 */
139  outport_byte(PIC_MASTER_IMR_IO_PORT, 0x04);/* edge tiggered, Cascade (slave) on IRQ2 */
140  outport_byte(PIC_MASTER_IMR_IO_PORT, 0x01);/* Select 8086 mode */
141  outport_byte(PIC_MASTER_IMR_IO_PORT, 0xFB); /* Mask all except cascade */
142  /*
143   * init slave  interrupt controller
144   */
145  outport_byte(PIC_SLAVE_COMMAND_IO_PORT, 0x11); /* Start init sequence */
146  outport_byte(PIC_SLAVE_IMR_IO_PORT, 0x08);/* Vector base  = 8 */
147  outport_byte(PIC_SLAVE_IMR_IO_PORT, 0x02);/* edge triggered, Cascade (slave) on IRQ2 */
148  outport_byte(PIC_SLAVE_IMR_IO_PORT, 0x01); /* Select 8086 mode */
149  outport_byte(PIC_SLAVE_IMR_IO_PORT, 0xFF); /* Mask all */
150 
151}
152
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