[acc25ee] | 1 | |
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| 2 | /* |
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| 3 | * This file contains the implementation of the function described in irq.h |
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| 4 | * related to Intel 8259 Programmable Interrupt controller. |
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| 5 | * |
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| 6 | * Copyright (C) 1998, 1999 valette@crf.canon.fr |
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| 7 | * |
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| 8 | * The license and distribution terms for this file may be |
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| 9 | * found in found in the file LICENSE in this distribution or at |
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[e831de8] | 10 | * http://www.rtems.com/license/LICENSE. |
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[acc25ee] | 11 | * |
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| 12 | * $Id$ |
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| 13 | */ |
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[6128a4a] | 14 | |
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[acc25ee] | 15 | #include <bsp.h> |
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| 16 | #include <bsp/irq.h> |
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| 17 | |
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| 18 | /*-------------------------------------------------------------------------+ |
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| 19 | | Cache for 1st and 2nd PIC IRQ line's status (enabled or disabled) register. |
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| 20 | +--------------------------------------------------------------------------*/ |
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| 21 | /* |
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| 22 | * lower byte is interrupt mask on the master PIC. |
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| 23 | * while upper bits are interrupt on the slave PIC. |
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| 24 | */ |
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| 25 | volatile rtems_i8259_masks i8259s_cache = 0xfffb; |
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| 26 | |
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| 27 | /*-------------------------------------------------------------------------+ |
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| 28 | | Function: BSP_irq_disable_at_i8259s |
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| 29 | | Description: Mask IRQ line in appropriate PIC chip. |
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| 30 | | Global Variables: i8259s_cache |
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| 31 | | Arguments: vector_offset - number of IRQ line to mask. |
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[6128a4a] | 32 | | Returns: Nothing. |
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[acc25ee] | 33 | +--------------------------------------------------------------------------*/ |
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[d8999b7] | 34 | int BSP_irq_disable_at_i8259s (const rtems_irq_number irqLine) |
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[acc25ee] | 35 | { |
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| 36 | unsigned short mask; |
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| 37 | unsigned int level; |
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| 38 | |
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| 39 | if ( ((int)irqLine < BSP_ISA_IRQ_LOWEST_OFFSET) || |
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| 40 | ((int)irqLine > BSP_ISA_IRQ_MAX_OFFSET) |
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| 41 | ) |
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| 42 | return 1; |
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[6128a4a] | 43 | |
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[acc25ee] | 44 | _CPU_ISR_Disable(level); |
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[6128a4a] | 45 | |
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[acc25ee] | 46 | mask = 1 << irqLine; |
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| 47 | i8259s_cache |= mask; |
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[6128a4a] | 48 | |
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[acc25ee] | 49 | if (irqLine < 8) |
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| 50 | { |
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| 51 | outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); |
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| 52 | } |
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| 53 | else |
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| 54 | { |
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| 55 | outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); |
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| 56 | } |
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| 57 | _CPU_ISR_Enable (level); |
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| 58 | |
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| 59 | return 0; |
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[6128a4a] | 60 | } |
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[acc25ee] | 61 | |
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| 62 | /*-------------------------------------------------------------------------+ |
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| 63 | | Function: BSP_irq_enable_at_i8259s |
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| 64 | | Description: Unmask IRQ line in appropriate PIC chip. |
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| 65 | | Global Variables: i8259s_cache |
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| 66 | | Arguments: irqLine - number of IRQ line to mask. |
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[6128a4a] | 67 | | Returns: Nothing. |
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[acc25ee] | 68 | +--------------------------------------------------------------------------*/ |
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[d8999b7] | 69 | int BSP_irq_enable_at_i8259s (const rtems_irq_number irqLine) |
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[acc25ee] | 70 | { |
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| 71 | unsigned short mask; |
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| 72 | unsigned int level; |
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| 73 | |
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| 74 | if ( ((int)irqLine < BSP_ISA_IRQ_LOWEST_OFFSET) || |
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| 75 | ((int)irqLine > BSP_ISA_IRQ_MAX_OFFSET ) |
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| 76 | ) |
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| 77 | return 1; |
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| 78 | |
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| 79 | _CPU_ISR_Disable(level); |
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[6128a4a] | 80 | |
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[acc25ee] | 81 | mask = ~(1 << irqLine); |
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| 82 | i8259s_cache &= mask; |
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[6128a4a] | 83 | |
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[acc25ee] | 84 | if (irqLine < 8) |
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| 85 | { |
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| 86 | outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); |
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| 87 | } |
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| 88 | else |
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| 89 | { |
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| 90 | outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); |
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| 91 | } |
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| 92 | _CPU_ISR_Enable (level); |
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| 93 | |
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| 94 | return 0; |
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| 95 | } /* mask_irq */ |
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| 96 | |
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[d8999b7] | 97 | int BSP_irq_enabled_at_i8259s (const rtems_irq_number irqLine) |
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[acc25ee] | 98 | { |
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| 99 | unsigned short mask; |
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| 100 | |
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| 101 | if ( ((int)irqLine < BSP_ISA_IRQ_LOWEST_OFFSET) || |
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| 102 | ((int)irqLine > BSP_ISA_IRQ_MAX_OFFSET) |
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| 103 | ) |
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| 104 | return 1; |
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| 105 | |
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| 106 | mask = (1 << irqLine); |
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| 107 | return (~(i8259s_cache & mask)); |
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| 108 | } |
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[6128a4a] | 109 | |
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[acc25ee] | 110 | /*-------------------------------------------------------------------------+ |
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| 111 | | Function: BSP_irq_ack_at_i8259s |
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| 112 | | Description: Signal generic End Of Interrupt (EOI) to appropriate PIC. |
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| 113 | | Global Variables: None. |
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| 114 | | Arguments: irqLine - number of IRQ line to acknowledge. |
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[6128a4a] | 115 | | Returns: Nothing. |
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[acc25ee] | 116 | +--------------------------------------------------------------------------*/ |
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[d8999b7] | 117 | int BSP_irq_ack_at_i8259s (const rtems_irq_number irqLine) |
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[acc25ee] | 118 | { |
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| 119 | if (irqLine >= 8) { |
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| 120 | outport_byte(PIC_MASTER_COMMAND_IO_PORT, SLAVE_PIC_EOSI); |
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| 121 | outport_byte(PIC_SLAVE_COMMAND_IO_PORT, (PIC_EOSI | (irqLine - 8))); |
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| 122 | } |
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| 123 | else { |
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| 124 | outport_byte(PIC_MASTER_COMMAND_IO_PORT, (PIC_EOSI | irqLine)); |
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| 125 | } |
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| 126 | |
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| 127 | return 0; |
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| 128 | |
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| 129 | } /* ackIRQ */ |
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| 130 | |
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| 131 | void BSP_i8259s_init(void) |
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| 132 | { |
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| 133 | /* |
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| 134 | * init master 8259 interrupt controller |
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| 135 | */ |
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| 136 | outport_byte(PIC_MASTER_COMMAND_IO_PORT, 0x11); /* Start init sequence */ |
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| 137 | outport_byte(PIC_MASTER_IMR_IO_PORT, 0x00);/* Vector base = 0 */ |
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| 138 | outport_byte(PIC_MASTER_IMR_IO_PORT, 0x04);/* edge tiggered, Cascade (slave) on IRQ2 */ |
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| 139 | outport_byte(PIC_MASTER_IMR_IO_PORT, 0x01);/* Select 8086 mode */ |
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| 140 | outport_byte(PIC_MASTER_IMR_IO_PORT, 0xFB); /* Mask all except cascade */ |
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| 141 | /* |
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| 142 | * init slave interrupt controller |
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| 143 | */ |
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| 144 | outport_byte(PIC_SLAVE_COMMAND_IO_PORT, 0x11); /* Start init sequence */ |
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| 145 | outport_byte(PIC_SLAVE_IMR_IO_PORT, 0x08);/* Vector base = 8 */ |
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| 146 | outport_byte(PIC_SLAVE_IMR_IO_PORT, 0x02);/* edge triggered, Cascade (slave) on IRQ2 */ |
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| 147 | outport_byte(PIC_SLAVE_IMR_IO_PORT, 0x01); /* Select 8086 mode */ |
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| 148 | outport_byte(PIC_SLAVE_IMR_IO_PORT, 0xFF); /* Mask all */ |
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[6128a4a] | 149 | |
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[acc25ee] | 150 | } |
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