source: rtems/c/src/lib/libbsp/powerpc/shared/console/uart.h @ 969de1f3

4.104.114.84.95
Last change on this file since 969de1f3 was acc25ee, checked in by Joel Sherrill <joel.sherrill@…>, on Dec 2, 1999 at 2:31:19 PM

Merged of mcp750 and mvme2307 BSP by Eric Valette <valette@…>.
As part of this effort, the mpc750 libcpu code is now shared with the
ppc6xx.

  • Property mode set to 100644
File size: 5.5 KB
Line 
1
2
3/*
4 * This software is Copyright (C) 1998 by T.sqware - all rights limited
5 * It is provided in to the public domain "as is", can be freely modified
6 * as far as this copyight notice is kept unchanged, but does not imply
7 * an endorsement by T.sqware of the product in which it is included.
8 */
9
10#ifndef _BSPUART_H
11#define _BSPUART_H
12
13void BSP_uart_init(int uart, int baud, int hwFlow);
14void BSP_uart_set_baud(int aurt, int baud);
15void BSP_uart_intr_ctrl(int uart, int cmd);
16void BSP_uart_throttle(int uart);
17void BSP_uart_unthrottle(int uart);
18int  BSP_uart_polled_status(int uart);
19void BSP_uart_polled_write(int uart, int val);
20int  BSP_uart_polled_read(int uart);
21void BSP_uart_termios_set(int uart, void *ttyp);
22int  BSP_uart_termios_write_com1(int minor, const char *buf, int len);
23int  BSP_uart_termios_write_com2(int minor, const char *buf, int len);
24void BSP_uart_termios_isr_com1();
25void BSP_uart_termios_isr_com2();
26void BSP_uart_dbgisr_com1(void);
27void BSP_uart_dbgisr_com2(void);
28extern unsigned BSP_poll_char_via_serial(void);
29extern void BSP_output_char_via_serial(int val);
30extern int BSPConsolePort;
31extern int BSPBaseBaud;
32/*
33 * Command values for BSP_uart_intr_ctrl(),
34 * values are strange in order to catch errors
35 * with assert
36 */
37#define BSP_UART_INTR_CTRL_DISABLE  (0)
38#define BSP_UART_INTR_CTRL_GDB      (0xaa) /* RX only */
39#define BSP_UART_INTR_CTRL_ENABLE   (0xbb) /* Normal operations */
40#define BSP_UART_INTR_CTRL_TERMIOS  (0xcc) /* RX & line status */
41
42/* Return values for uart_polled_status() */
43#define BSP_UART_STATUS_ERROR    (-1) /* No character */
44#define BSP_UART_STATUS_NOCHAR   (0)  /* No character */
45#define BSP_UART_STATUS_CHAR     (1)  /* Character present */
46#define BSP_UART_STATUS_BREAK    (2)  /* Break point is detected */
47
48/* PC UART definitions */
49#define BSP_UART_COM1            (0)
50#define BSP_UART_COM2            (1)
51
52/*
53 * Base IO for UART
54 */
55
56#define COM1_BASE_IO    0x3F8
57#define COM2_BASE_IO    0x2F8
58
59/*
60 * Offsets from base
61 */
62
63/* DLAB 0 */
64#define RBR  (0)    /* Rx Buffer Register (read) */
65#define THR  (0)    /* Tx Buffer Register (write) */
66#define IER  (1)    /* Interrupt Enable Register */
67
68/* DLAB X */
69#define IIR  (2)    /* Interrupt Ident Register (read) */
70#define FCR  (2)    /* FIFO Control Register (write) */
71#define LCR  (3)    /* Line Control Register */
72#define MCR  (4)    /* Modem Control Register */
73#define LSR  (5)    /* Line Status Register */
74#define MSR  (6)    /* Modem Status  Register */
75#define SCR  (7)    /* Scratch register */
76
77/* DLAB 1 */
78#define DLL  (0)    /* Divisor Latch, LSB */
79#define DLM  (1)    /* Divisor Latch, MSB */
80#define AFR  (2)    /* Alternate Function register */
81
82/*
83 * Interrupt source definition via IIR
84 */
85#define MODEM_STATUS                            0
86#define NO_MORE_INTR                            1
87#define TRANSMITTER_HODING_REGISTER_EMPTY       2
88#define RECEIVER_DATA_AVAIL                     4
89#define RECEIVER_ERROR                          6
90#define CHARACTER_TIMEOUT_INDICATION            12
91
92/*
93 * Bits definition of IER
94 */
95#define RECEIVE_ENABLE          0x1
96#define TRANSMIT_ENABLE         0x2
97#define RECEIVER_LINE_ST_ENABLE 0x4
98#define MODEM_ENABLE            0x8
99#define INTERRUPT_DISABLE       0x0
100
101/*
102 * Bits definition of the Line Status Register (LSR)
103 */
104#define DR      0x01    /* Data Ready */
105#define OE      0x02    /* Overrun Error */
106#define PE      0x04    /* Parity Error */
107#define FE      0x08    /* Framing Error */
108#define BI      0x10    /* Break Interrupt */
109#define THRE    0x20    /* Transmitter Holding Register Empty */
110#define TEMT    0x40    /* Transmitter Empty */
111#define ERFIFO  0x80    /* Error receive Fifo */
112
113/*
114 * Bits definition of the MODEM Control Register (MCR)
115 */
116#define DTR     0x01    /* Data Terminal Ready */
117#define RTS     0x02    /* Request To Send */
118#define OUT_1   0x04    /* Output 1, (reserved on COMPAQ I/O Board) */
119#define OUT_2   0x08    /* Output 2, Enable Asynchronous Port Interrupts */
120#define LB      0x10    /* Enable Internal Loop Back */
121
122/*
123 * Bits definition of the Line Control Register (LCR)
124 */
125#define CHR_5_BITS 0
126#define CHR_6_BITS 1
127#define CHR_7_BITS 2
128#define CHR_8_BITS 3
129
130#define WL      0x03    /* Word length mask */
131#define STB     0x04    /* 1 Stop Bit, otherwise 2 Stop Bits */
132#define PEN     0x08    /* Parity Enabled */
133#define EPS     0x10    /* Even Parity Select, otherwise Odd */
134#define SP      0x20    /* Stick Parity */
135#define BCB     0x40    /* Break Control Bit */
136#define DLAB    0x80    /* Enable Divisor Latch Access */
137
138/*
139 * Bits definition of the MODEM Status Register (MSR)
140 */
141#define DCTS    0x01    /* Delta Clear To Send */
142#define DDSR    0x02    /* Delta Data Set Ready */
143#define TERI    0x04    /* Trailing Edge Ring Indicator */
144#define DDCD    0x08    /* Delta Carrier Detect Indicator */
145#define CTS     0x10    /* Clear To Send (when loop back is active) */
146#define DSR     0x20    /* Data Set Ready (when loop back is active) */
147#define RI      0x40    /* Ring Indicator (when loop back is active) */
148#define DCD     0x80    /* Data Carrier Detect (when loop back is active) */
149
150/*
151 * Bits definition of the FIFO Control Register : WD16C552 or NS16550
152 */
153
154#define FIFO_CTRL   0x01    /* Set to 1 permit access to other bits */
155#define FIFO_EN     0x01    /* Enable the FIFO */
156#define XMIT_RESET  0x02    /* Transmit FIFO Reset */
157#define RCV_RESET   0x04    /* Receive FIFO Reset */
158#define FCR3        0x08    /* do not understand manual! */
159
160#define RECEIVE_FIFO_TRIGGER1   0x0  /* trigger recieve interrupt after 1 byte  */
161#define RECEIVE_FIFO_TRIGGER4   0x40 /* trigger recieve interrupt after 4 byte  */
162#define RECEIVE_FIFO_TRIGGER8   0x80 /* trigger recieve interrupt after 8 byte  */
163#define RECEIVE_FIFO_TRIGGER12  0xc0 /* trigger recieve interrupt after 12 byte */
164#define TRIG_LEVEL              0xc0 /* Mask for the trigger level              */
165
166#endif /* _BSPUART_H */
167
168
169
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