source: rtems/c/src/lib/libbsp/powerpc/shared/console/uart.h @ 69ed59f

4.104.114.84.95
Last change on this file since 69ed59f was 69ed59f, checked in by Joel Sherrill <joel.sherrill@…>, on May 14, 2002 at 5:10:17 PM

2001-05-14 Till Straumann <strauman@…>

  • bootloader/misc.c, console/Makefile.am, console/console.c, console/consoleIo.h, console/inch.c, console/polled_io.c, console/uart.c, console/uart.h, include/bsp.h, irq/Makefile.am, irq/irq.c, irq/irq.h, irq/irq_init.c, openpic/openpic.c, openpic/openpic.h, pci/Makefile.am, pci/pci.c, pci/pci.h, residual/Makefile.am, start/start.S, startup/bspstart.c, vectors/vectors.S, vectors/vectors.h, vectors/vectors_init.c: Per PR216, "libbsp/powerpc/shared" BSP has been modified considerably with the goal to make it more flexible and reusable by other BSPs. The main strategies were:
    • eliminate hardcoded base addresses; devices use offsets and a BSP defined base address.
    • separate functionality into different files (e.g. reboot from inch.c to reboot.c) which can be overridden by a 'derived' BSP.
    • separate initialization code into separate files (e.g. PCI bridge detection/initialization was separated from the more generic PCI access routines), also to make it easier for 'derived' BSPs to substitute their own initialization code.

There are also a couple of enhancements and fixes:

  • IRQ handling code now has a hook for attaching a VME bridge.
  • OpenPIC is now explicitely initialized (polarities, senses). Eliminated the implicit assumption on the presence of an ISA PIC.
  • UART and console driver now supports more than 1 port. The current maximum of 2 can easily be extended by enlarging a table (it would even be easier if the ISR API was not broken by design).
  • fixed polled_io.c so it correctly supports console on COM2
  • fixed TLB invalidation code (start.S).
  • exception handler prints a stack backtrace.
  • added BSP_pciFindDevice() to scan the pci bus for a particular vendor/device/instance.
  • Property mode set to 100644
File size: 5.5 KB
Line 
1
2
3/*
4 * This software is Copyright (C) 1998 by T.sqware - all rights limited
5 * It is provided in to the public domain "as is", can be freely modified
6 * as far as this copyight notice is kept unchanged, but does not imply
7 * an endorsement by T.sqware of the product in which it is included.
8 */
9
10#ifndef _BSPUART_H
11#define _BSPUART_H
12
13#include <bsp/irq.h>
14
15void BSP_uart_init(int uart, int baud, int hwFlow);
16void BSP_uart_set_baud(int aurt, int baud);
17void BSP_uart_intr_ctrl(int uart, int cmd);
18void BSP_uart_throttle(int uart);
19void BSP_uart_unthrottle(int uart);
20int  BSP_uart_polled_status(int uart);
21void BSP_uart_polled_write(int uart, int val);
22int  BSP_uart_polled_read(int uart);
23void BSP_uart_termios_set(int uart, void *ttyp);
24int  BSP_uart_termios_write_com(int minor, const char *buf, int len);
25void BSP_uart_termios_isr_com1();
26void BSP_uart_termios_isr_com2();
27void BSP_uart_dbgisr_com1(void);
28void BSP_uart_dbgisr_com2(void);
29int  BSP_uart_install_isr(int uart, rtems_irq_hdl handler);
30int  BSP_uart_remove_isr(int uart, rtems_irq_hdl handler);
31
32extern unsigned BSP_poll_char_via_serial(void);
33extern void BSP_output_char_via_serial(int val);
34extern int BSPConsolePort;
35extern int BSPBaseBaud;
36/*
37 * Command values for BSP_uart_intr_ctrl(),
38 * values are strange in order to catch errors
39 * with assert
40 */
41#define BSP_UART_INTR_CTRL_DISABLE  (0)
42#define BSP_UART_INTR_CTRL_GDB      (0xaa) /* RX only */
43#define BSP_UART_INTR_CTRL_ENABLE   (0xbb) /* Normal operations */
44#define BSP_UART_INTR_CTRL_TERMIOS  (0xcc) /* RX & line status */
45
46/* Return values for uart_polled_status() */
47#define BSP_UART_STATUS_ERROR    (-1) /* No character */
48#define BSP_UART_STATUS_NOCHAR   (0)  /* No character */
49#define BSP_UART_STATUS_CHAR     (1)  /* Character present */
50#define BSP_UART_STATUS_BREAK    (2)  /* Break point is detected */
51
52/* PC UART definitions */
53#define BSP_UART_COM1            (0)
54#define BSP_UART_COM2            (1)
55
56/*
57 * Offsets from base
58 */
59
60/* DLAB 0 */
61#define RBR  (0)    /* Rx Buffer Register (read) */
62#define THR  (0)    /* Tx Buffer Register (write) */
63#define IER  (1)    /* Interrupt Enable Register */
64
65/* DLAB X */
66#define IIR  (2)    /* Interrupt Ident Register (read) */
67#define FCR  (2)    /* FIFO Control Register (write) */
68#define LCR  (3)    /* Line Control Register */
69#define MCR  (4)    /* Modem Control Register */
70#define LSR  (5)    /* Line Status Register */
71#define MSR  (6)    /* Modem Status  Register */
72#define SCR  (7)    /* Scratch register */
73
74/* DLAB 1 */
75#define DLL  (0)    /* Divisor Latch, LSB */
76#define DLM  (1)    /* Divisor Latch, MSB */
77#define AFR  (2)    /* Alternate Function register */
78
79/*
80 * Interrupt source definition via IIR
81 */
82#define MODEM_STATUS                            0
83#define NO_MORE_INTR                            1
84#define TRANSMITTER_HODING_REGISTER_EMPTY       2
85#define RECEIVER_DATA_AVAIL                     4
86#define RECEIVER_ERROR                          6
87#define CHARACTER_TIMEOUT_INDICATION            12
88
89/*
90 * Bits definition of IER
91 */
92#define RECEIVE_ENABLE          0x1
93#define TRANSMIT_ENABLE         0x2
94#define RECEIVER_LINE_ST_ENABLE 0x4
95#define MODEM_ENABLE            0x8
96#define INTERRUPT_DISABLE       0x0
97
98/*
99 * Bits definition of the Line Status Register (LSR)
100 */
101#define DR      0x01    /* Data Ready */
102#define OE      0x02    /* Overrun Error */
103#define PE      0x04    /* Parity Error */
104#define FE      0x08    /* Framing Error */
105#define BI      0x10    /* Break Interrupt */
106#define THRE    0x20    /* Transmitter Holding Register Empty */
107#define TEMT    0x40    /* Transmitter Empty */
108#define ERFIFO  0x80    /* Error receive Fifo */
109
110/*
111 * Bits definition of the MODEM Control Register (MCR)
112 */
113#define DTR     0x01    /* Data Terminal Ready */
114#define RTS     0x02    /* Request To Send */
115#define OUT_1   0x04    /* Output 1, (reserved on COMPAQ I/O Board) */
116#define OUT_2   0x08    /* Output 2, Enable Asynchronous Port Interrupts */
117#define LB      0x10    /* Enable Internal Loop Back */
118
119/*
120 * Bits definition of the Line Control Register (LCR)
121 */
122#define CHR_5_BITS 0
123#define CHR_6_BITS 1
124#define CHR_7_BITS 2
125#define CHR_8_BITS 3
126
127#define WL      0x03    /* Word length mask */
128#define STB     0x04    /* 1 Stop Bit, otherwise 2 Stop Bits */
129#define PEN     0x08    /* Parity Enabled */
130#define EPS     0x10    /* Even Parity Select, otherwise Odd */
131#define SP      0x20    /* Stick Parity */
132#define BCB     0x40    /* Break Control Bit */
133#define DLAB    0x80    /* Enable Divisor Latch Access */
134
135/*
136 * Bits definition of the MODEM Status Register (MSR)
137 */
138#define DCTS    0x01    /* Delta Clear To Send */
139#define DDSR    0x02    /* Delta Data Set Ready */
140#define TERI    0x04    /* Trailing Edge Ring Indicator */
141#define DDCD    0x08    /* Delta Carrier Detect Indicator */
142#define CTS     0x10    /* Clear To Send (when loop back is active) */
143#define DSR     0x20    /* Data Set Ready (when loop back is active) */
144#define RI      0x40    /* Ring Indicator (when loop back is active) */
145#define DCD     0x80    /* Data Carrier Detect (when loop back is active) */
146
147/*
148 * Bits definition of the FIFO Control Register : WD16C552 or NS16550
149 */
150
151#define FIFO_CTRL   0x01    /* Set to 1 permit access to other bits */
152#define FIFO_EN     0x01    /* Enable the FIFO */
153#define XMIT_RESET  0x02    /* Transmit FIFO Reset */
154#define RCV_RESET   0x04    /* Receive FIFO Reset */
155#define FCR3        0x08    /* do not understand manual! */
156
157#define RECEIVE_FIFO_TRIGGER1   0x0  /* trigger recieve interrupt after 1 byte  */
158#define RECEIVE_FIFO_TRIGGER4   0x40 /* trigger recieve interrupt after 4 byte  */
159#define RECEIVE_FIFO_TRIGGER8   0x80 /* trigger recieve interrupt after 8 byte  */
160#define RECEIVE_FIFO_TRIGGER12  0xc0 /* trigger recieve interrupt after 12 byte */
161#define TRIG_LEVEL              0xc0 /* Mask for the trigger level              */
162
163#endif /* _BSPUART_H */
164
165
166
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