source: rtems/c/src/lib/libbsp/powerpc/shared/console/uart.h @ 4f3e4f33

4.104.114.84.95
Last change on this file since 4f3e4f33 was 4f3e4f33, checked in by Joel Sherrill <joel.sherrill@…>, on Feb 20, 2003 at 9:32:07 PM

2003-02-20 Till Straumann <strauman@…>

PR 349/bsps

  • console/console.c, console/uart.c, console/uart.h: implement IOCTLs for the serial (UART) console to install/retrieve a BREAK-IRQ callback. The callback routine (if installed) is invoked from the UART ISR when a BREAK interrupt is detected. This can be used e.g. to enforce a "hotkey" reboot a la vxWorks Ctrl-X (although we use the serial line break condition) NOTE: The callback runs in ISR context.
  • Property mode set to 100644
File size: 6.3 KB
Line 
1
2
3/*
4 * This software is Copyright (C) 1998 by T.sqware - all rights limited
5 * It is provided in to the public domain "as is", can be freely modified
6 * as far as this copyight notice is kept unchanged, but does not imply
7 * an endorsement by T.sqware of the product in which it is included.
8 */
9
10#ifndef _BSPUART_H
11#define _BSPUART_H
12
13#include <bsp/irq.h>
14
15#include <sys/ioctl.h>
16#include <rtems/libio.h>
17
18void BSP_uart_init(int uart, int baud, int hwFlow);
19void BSP_uart_set_baud(int aurt, int baud);
20void BSP_uart_intr_ctrl(int uart, int cmd);
21void BSP_uart_throttle(int uart);
22void BSP_uart_unthrottle(int uart);
23int  BSP_uart_polled_status(int uart);
24void BSP_uart_polled_write(int uart, int val);
25int  BSP_uart_polled_read(int uart);
26void BSP_uart_termios_set(int uart, void *ttyp);
27int  BSP_uart_termios_write_com(int minor, const char *buf, int len);
28void BSP_uart_termios_isr_com1();
29void BSP_uart_termios_isr_com2();
30void BSP_uart_dbgisr_com1(void);
31void BSP_uart_dbgisr_com2(void);
32int  BSP_uart_install_isr(int uart, rtems_irq_hdl handler);
33int  BSP_uart_remove_isr(int uart, rtems_irq_hdl handler);
34int  BSP_uart_get_break_cb(int uart, rtems_libio_ioctl_args_t *arg);
35int  BSP_uart_set_break_cb(int uart, rtems_libio_ioctl_args_t *arg);
36
37extern unsigned BSP_poll_char_via_serial(void);
38extern void BSP_output_char_via_serial(int val);
39extern int BSPConsolePort;
40extern int BSPBaseBaud;
41
42/* Special IOCTLS to install a lowlevel 'BREAK' handler */
43
44/* pass a BSP_UartBreakCb pointer to ioctl when retrieving
45 * or installing break callback
46 */
47typedef void (*BSP_UartBreakCbProc)(int                 uartMinor,
48                                                                        unsigned        uartRBRLSRStatus,
49                                                                        void            *termiosPrivatePtr,
50                                                                        void            *private);
51
52typedef struct BSP_UartBreakCbRec_ {
53                BSP_UartBreakCbProc             handler;        /* NOTE NOTE this handler runs in INTERRUPT CONTEXT */
54                void                                    *private;       /* closure pointer which is passed to the callback  */
55} BSP_UartBreakCbRec, *BSP_UartBreakCb;
56
57#define BIOCGETBREAKCB  _IOR('b',1,sizeof(BSP_UartBreakCbRec))
58#define BIOCSETBREAKCB  _IOW('b',2,sizeof(BSP_UartBreakCbRec))
59
60/*
61 * Command values for BSP_uart_intr_ctrl(),
62 * values are strange in order to catch errors
63 * with assert
64 */
65#define BSP_UART_INTR_CTRL_DISABLE  (0)
66#define BSP_UART_INTR_CTRL_GDB      (0xaa) /* RX only */
67#define BSP_UART_INTR_CTRL_ENABLE   (0xbb) /* Normal operations */
68#define BSP_UART_INTR_CTRL_TERMIOS  (0xcc) /* RX & line status */
69
70/* Return values for uart_polled_status() */
71#define BSP_UART_STATUS_ERROR    (-1) /* No character */
72#define BSP_UART_STATUS_NOCHAR   (0)  /* No character */
73#define BSP_UART_STATUS_CHAR     (1)  /* Character present */
74#define BSP_UART_STATUS_BREAK    (2)  /* Break point is detected */
75
76/* PC UART definitions */
77#define BSP_UART_COM1            (0)
78#define BSP_UART_COM2            (1)
79
80/*
81 * Offsets from base
82 */
83
84/* DLAB 0 */
85#define RBR  (0)    /* Rx Buffer Register (read) */
86#define THR  (0)    /* Tx Buffer Register (write) */
87#define IER  (1)    /* Interrupt Enable Register */
88
89/* DLAB X */
90#define IIR  (2)    /* Interrupt Ident Register (read) */
91#define FCR  (2)    /* FIFO Control Register (write) */
92#define LCR  (3)    /* Line Control Register */
93#define MCR  (4)    /* Modem Control Register */
94#define LSR  (5)    /* Line Status Register */
95#define MSR  (6)    /* Modem Status  Register */
96#define SCR  (7)    /* Scratch register */
97
98/* DLAB 1 */
99#define DLL  (0)    /* Divisor Latch, LSB */
100#define DLM  (1)    /* Divisor Latch, MSB */
101#define AFR  (2)    /* Alternate Function register */
102
103/*
104 * Interrupt source definition via IIR
105 */
106#define MODEM_STATUS                            0
107#define NO_MORE_INTR                            1
108#define TRANSMITTER_HODING_REGISTER_EMPTY       2
109#define RECEIVER_DATA_AVAIL                     4
110#define RECEIVER_ERROR                          6
111#define CHARACTER_TIMEOUT_INDICATION            12
112
113/*
114 * Bits definition of IER
115 */
116#define RECEIVE_ENABLE          0x1
117#define TRANSMIT_ENABLE         0x2
118#define RECEIVER_LINE_ST_ENABLE 0x4
119#define MODEM_ENABLE            0x8
120#define INTERRUPT_DISABLE       0x0
121
122/*
123 * Bits definition of the Line Status Register (LSR)
124 */
125#define DR      0x01    /* Data Ready */
126#define OE      0x02    /* Overrun Error */
127#define PE      0x04    /* Parity Error */
128#define FE      0x08    /* Framing Error */
129#define BI      0x10    /* Break Interrupt */
130#define THRE    0x20    /* Transmitter Holding Register Empty */
131#define TEMT    0x40    /* Transmitter Empty */
132#define ERFIFO  0x80    /* Error receive Fifo */
133
134/*
135 * Bits definition of the MODEM Control Register (MCR)
136 */
137#define DTR     0x01    /* Data Terminal Ready */
138#define RTS     0x02    /* Request To Send */
139#define OUT_1   0x04    /* Output 1, (reserved on COMPAQ I/O Board) */
140#define OUT_2   0x08    /* Output 2, Enable Asynchronous Port Interrupts */
141#define LB      0x10    /* Enable Internal Loop Back */
142
143/*
144 * Bits definition of the Line Control Register (LCR)
145 */
146#define CHR_5_BITS 0
147#define CHR_6_BITS 1
148#define CHR_7_BITS 2
149#define CHR_8_BITS 3
150
151#define WL      0x03    /* Word length mask */
152#define STB     0x04    /* 1 Stop Bit, otherwise 2 Stop Bits */
153#define PEN     0x08    /* Parity Enabled */
154#define EPS     0x10    /* Even Parity Select, otherwise Odd */
155#define SP      0x20    /* Stick Parity */
156#define BCB     0x40    /* Break Control Bit */
157#define DLAB    0x80    /* Enable Divisor Latch Access */
158
159/*
160 * Bits definition of the MODEM Status Register (MSR)
161 */
162#define DCTS    0x01    /* Delta Clear To Send */
163#define DDSR    0x02    /* Delta Data Set Ready */
164#define TERI    0x04    /* Trailing Edge Ring Indicator */
165#define DDCD    0x08    /* Delta Carrier Detect Indicator */
166#define CTS     0x10    /* Clear To Send (when loop back is active) */
167#define DSR     0x20    /* Data Set Ready (when loop back is active) */
168#define RI      0x40    /* Ring Indicator (when loop back is active) */
169#define DCD     0x80    /* Data Carrier Detect (when loop back is active) */
170
171/*
172 * Bits definition of the FIFO Control Register : WD16C552 or NS16550
173 */
174
175#define FIFO_CTRL   0x01    /* Set to 1 permit access to other bits */
176#define FIFO_EN     0x01    /* Enable the FIFO */
177#define XMIT_RESET  0x02    /* Transmit FIFO Reset */
178#define RCV_RESET   0x04    /* Receive FIFO Reset */
179#define FCR3        0x08    /* do not understand manual! */
180
181#define RECEIVE_FIFO_TRIGGER1   0x0  /* trigger recieve interrupt after 1 byte  */
182#define RECEIVE_FIFO_TRIGGER4   0x40 /* trigger recieve interrupt after 4 byte  */
183#define RECEIVE_FIFO_TRIGGER8   0x80 /* trigger recieve interrupt after 8 byte  */
184#define RECEIVE_FIFO_TRIGGER12  0xc0 /* trigger recieve interrupt after 12 byte */
185#define TRIG_LEVEL              0xc0 /* Mask for the trigger level              */
186
187#endif /* _BSPUART_H */
188
189
190
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