source: rtems/c/src/lib/libbsp/powerpc/shared/console/uart.h @ 2d0d029

4.104.114.84.9
Last change on this file since 2d0d029 was 2d0d029, checked in by Jennifer Averett <Jennifer.Averett@…>, on Apr 15, 2005 at 5:52:46 PM

2005-04-15 Jennifer Averett <jennifer.averett@…>

PR 779/bsp

  • clock/p_clock.c, console/console.c, console/uart.c, console/uart.h, irq/irq.c, irq/irq.h, irq/irq_init.c: powerpc: add parameter to new exception interrupt handlers
  • Property mode set to 100644
File size: 6.4 KB
Line 
1
2
3/*
4 * This software is Copyright (C) 1998 by T.sqware - all rights limited
5 * It is provided in to the public domain "as is", can be freely modified
6 * as far as this copyight notice is kept unchanged, but does not imply
7 * an endorsement by T.sqware of the product in which it is included.
8 */
9
10#ifndef _BSPUART_H
11#define _BSPUART_H
12
13#include <bsp/irq.h>
14
15#include <sys/ioctl.h>
16#include <rtems/libio.h>
17
18void BSP_uart_init(int uart, int baud, int hwFlow);
19void BSP_uart_set_baud(int uart, int baud);
20void BSP_uart_intr_ctrl(int uart, int cmd);
21void BSP_uart_throttle(int uart);
22void BSP_uart_unthrottle(int uart);
23int  BSP_uart_polled_status(int uart);
24void BSP_uart_polled_write(int uart, int val);
25int  BSP_uart_polled_read(int uart);
26void BSP_uart_termios_set(int uart, void *ttyp);
27int  BSP_uart_termios_write_com(int minor, const char *buf, int len);
28void BSP_uart_termios_isr_com1(void *unused);
29void BSP_uart_termios_isr_com2(void *unused);
30void BSP_uart_dbgisr_com1(void);
31void BSP_uart_dbgisr_com2(void);
32int  BSP_uart_install_isr(int uart, rtems_irq_hdl handler);
33int  BSP_uart_remove_isr(int uart, rtems_irq_hdl handler);
34int  BSP_uart_termios_write_polled(int minor, const char *buf, int len);
35int  BSP_uart_get_break_cb(int uart, rtems_libio_ioctl_args_t *arg);
36int  BSP_uart_set_break_cb(int uart, rtems_libio_ioctl_args_t *arg);
37
38extern unsigned BSP_poll_char_via_serial(void);
39extern void BSP_output_char_via_serial(const char val);
40extern int BSPConsolePort;
41extern int BSPBaseBaud;
42
43/* Special IOCTLS to install a lowlevel 'BREAK' handler */
44
45/* pass a BSP_UartBreakCb pointer to ioctl when retrieving
46 * or installing break callback
47 */
48typedef void (*BSP_UartBreakCbProc)(int                 uartMinor,
49                                                                        unsigned        uartRBRLSRStatus,
50                                                                        void            *termiosPrivatePtr,
51                                                                        void            *private);
52
53typedef struct BSP_UartBreakCbRec_ {
54                BSP_UartBreakCbProc             handler;        /* NOTE NOTE this handler runs in INTERRUPT CONTEXT */
55                void                                    *private;       /* closure pointer which is passed to the callback  */
56} BSP_UartBreakCbRec, *BSP_UartBreakCb;
57
58#define BIOCGETBREAKCB  _IOR('b',1,sizeof(BSP_UartBreakCbRec))
59#define BIOCSETBREAKCB  _IOW('b',2,sizeof(BSP_UartBreakCbRec))
60
61/*
62 * Command values for BSP_uart_intr_ctrl(),
63 * values are strange in order to catch errors
64 * with assert
65 */
66#define BSP_UART_INTR_CTRL_DISABLE  (0)
67#define BSP_UART_INTR_CTRL_GDB      (0xaa) /* RX only */
68#define BSP_UART_INTR_CTRL_ENABLE   (0xbb) /* Normal operations */
69#define BSP_UART_INTR_CTRL_TERMIOS  (0xcc) /* RX & line status */
70
71/* Return values for uart_polled_status() */
72#define BSP_UART_STATUS_ERROR    (-1) /* No character */
73#define BSP_UART_STATUS_NOCHAR   (0)  /* No character */
74#define BSP_UART_STATUS_CHAR     (1)  /* Character present */
75#define BSP_UART_STATUS_BREAK    (2)  /* Break point is detected */
76
77/* PC UART definitions */
78#define BSP_UART_COM1            (0)
79#define BSP_UART_COM2            (1)
80
81/*
82 * Offsets from base
83 */
84
85/* DLAB 0 */
86#define RBR  (0)    /* Rx Buffer Register (read) */
87#define THR  (0)    /* Tx Buffer Register (write) */
88#define IER  (1)    /* Interrupt Enable Register */
89
90/* DLAB X */
91#define IIR  (2)    /* Interrupt Ident Register (read) */
92#define FCR  (2)    /* FIFO Control Register (write) */
93#define LCR  (3)    /* Line Control Register */
94#define MCR  (4)    /* Modem Control Register */
95#define LSR  (5)    /* Line Status Register */
96#define MSR  (6)    /* Modem Status  Register */
97#define SCR  (7)    /* Scratch register */
98
99/* DLAB 1 */
100#define DLL  (0)    /* Divisor Latch, LSB */
101#define DLM  (1)    /* Divisor Latch, MSB */
102#define AFR  (2)    /* Alternate Function register */
103
104/*
105 * Interrupt source definition via IIR
106 */
107#define MODEM_STATUS                            0
108#define NO_MORE_INTR                            1
109#define TRANSMITTER_HODING_REGISTER_EMPTY       2
110#define RECEIVER_DATA_AVAIL                     4
111#define RECEIVER_ERROR                          6
112#define CHARACTER_TIMEOUT_INDICATION            12
113
114/*
115 * Bits definition of IER
116 */
117#define RECEIVE_ENABLE          0x1
118#define TRANSMIT_ENABLE         0x2
119#define RECEIVER_LINE_ST_ENABLE 0x4
120#define MODEM_ENABLE            0x8
121#define INTERRUPT_DISABLE       0x0
122
123/*
124 * Bits definition of the Line Status Register (LSR)
125 */
126#define DR      0x01    /* Data Ready */
127#define OE      0x02    /* Overrun Error */
128#define PE      0x04    /* Parity Error */
129#define FE      0x08    /* Framing Error */
130#define BI      0x10    /* Break Interrupt */
131#define THRE    0x20    /* Transmitter Holding Register Empty */
132#define TEMT    0x40    /* Transmitter Empty */
133#define ERFIFO  0x80    /* Error receive Fifo */
134
135/*
136 * Bits definition of the MODEM Control Register (MCR)
137 */
138#define DTR     0x01    /* Data Terminal Ready */
139#define RTS     0x02    /* Request To Send */
140#define OUT_1   0x04    /* Output 1, (reserved on COMPAQ I/O Board) */
141#define OUT_2   0x08    /* Output 2, Enable Asynchronous Port Interrupts */
142#define LB      0x10    /* Enable Internal Loop Back */
143
144/*
145 * Bits definition of the Line Control Register (LCR)
146 */
147#define CHR_5_BITS 0
148#define CHR_6_BITS 1
149#define CHR_7_BITS 2
150#define CHR_8_BITS 3
151
152#define WL      0x03    /* Word length mask */
153#define STB     0x04    /* 1 Stop Bit, otherwise 2 Stop Bits */
154#define PEN     0x08    /* Parity Enabled */
155#define EPS     0x10    /* Even Parity Select, otherwise Odd */
156#define SP      0x20    /* Stick Parity */
157#define BCB     0x40    /* Break Control Bit */
158#define DLAB    0x80    /* Enable Divisor Latch Access */
159
160/*
161 * Bits definition of the MODEM Status Register (MSR)
162 */
163#define DCTS    0x01    /* Delta Clear To Send */
164#define DDSR    0x02    /* Delta Data Set Ready */
165#define TERI    0x04    /* Trailing Edge Ring Indicator */
166#define DDCD    0x08    /* Delta Carrier Detect Indicator */
167#define CTS     0x10    /* Clear To Send (when loop back is active) */
168#define DSR     0x20    /* Data Set Ready (when loop back is active) */
169#define RI      0x40    /* Ring Indicator (when loop back is active) */
170#define DCD     0x80    /* Data Carrier Detect (when loop back is active) */
171
172/*
173 * Bits definition of the FIFO Control Register : WD16C552 or NS16550
174 */
175
176#define FIFO_CTRL   0x01    /* Set to 1 permit access to other bits */
177#define FIFO_EN     0x01    /* Enable the FIFO */
178#define XMIT_RESET  0x02    /* Transmit FIFO Reset */
179#define RCV_RESET   0x04    /* Receive FIFO Reset */
180#define FCR3        0x08    /* do not understand manual! */
181
182#define RECEIVE_FIFO_TRIGGER1   0x0  /* trigger recieve interrupt after 1 byte  */
183#define RECEIVE_FIFO_TRIGGER4   0x40 /* trigger recieve interrupt after 4 byte  */
184#define RECEIVE_FIFO_TRIGGER8   0x80 /* trigger recieve interrupt after 8 byte  */
185#define RECEIVE_FIFO_TRIGGER12  0xc0 /* trigger recieve interrupt after 12 byte */
186#define TRIG_LEVEL              0xc0 /* Mask for the trigger level              */
187
188#endif /* _BSPUART_H */
Note: See TracBrowser for help on using the repository browser.