[acc25ee] | 1 | |
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| 2 | |
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| 3 | /* |
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| 4 | * This software is Copyright (C) 1998 by T.sqware - all rights limited |
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| 5 | * It is provided in to the public domain "as is", can be freely modified |
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| 6 | * as far as this copyight notice is kept unchanged, but does not imply |
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| 7 | * an endorsement by T.sqware of the product in which it is included. |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef _BSPUART_H |
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| 11 | #define _BSPUART_H |
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| 12 | |
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[69ed59f] | 13 | #include <bsp/irq.h> |
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| 14 | |
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[4f3e4f33] | 15 | #include <sys/ioctl.h> |
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| 16 | #include <rtems/libio.h> |
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| 17 | |
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[acc25ee] | 18 | void BSP_uart_init(int uart, int baud, int hwFlow); |
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| 19 | void BSP_uart_set_baud(int aurt, int baud); |
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| 20 | void BSP_uart_intr_ctrl(int uart, int cmd); |
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| 21 | void BSP_uart_throttle(int uart); |
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| 22 | void BSP_uart_unthrottle(int uart); |
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| 23 | int BSP_uart_polled_status(int uart); |
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| 24 | void BSP_uart_polled_write(int uart, int val); |
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| 25 | int BSP_uart_polled_read(int uart); |
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| 26 | void BSP_uart_termios_set(int uart, void *ttyp); |
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[69ed59f] | 27 | int BSP_uart_termios_write_com(int minor, const char *buf, int len); |
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[acc25ee] | 28 | void BSP_uart_termios_isr_com1(); |
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| 29 | void BSP_uart_termios_isr_com2(); |
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| 30 | void BSP_uart_dbgisr_com1(void); |
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| 31 | void BSP_uart_dbgisr_com2(void); |
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[69ed59f] | 32 | int BSP_uart_install_isr(int uart, rtems_irq_hdl handler); |
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| 33 | int BSP_uart_remove_isr(int uart, rtems_irq_hdl handler); |
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[4f3e4f33] | 34 | int BSP_uart_get_break_cb(int uart, rtems_libio_ioctl_args_t *arg); |
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| 35 | int BSP_uart_set_break_cb(int uart, rtems_libio_ioctl_args_t *arg); |
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[69ed59f] | 36 | |
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[acc25ee] | 37 | extern unsigned BSP_poll_char_via_serial(void); |
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| 38 | extern void BSP_output_char_via_serial(int val); |
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| 39 | extern int BSPConsolePort; |
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| 40 | extern int BSPBaseBaud; |
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[4f3e4f33] | 41 | |
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| 42 | /* Special IOCTLS to install a lowlevel 'BREAK' handler */ |
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| 43 | |
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| 44 | /* pass a BSP_UartBreakCb pointer to ioctl when retrieving |
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| 45 | * or installing break callback |
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| 46 | */ |
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| 47 | typedef void (*BSP_UartBreakCbProc)(int uartMinor, |
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| 48 | unsigned uartRBRLSRStatus, |
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| 49 | void *termiosPrivatePtr, |
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| 50 | void *private); |
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| 51 | |
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| 52 | typedef struct BSP_UartBreakCbRec_ { |
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| 53 | BSP_UartBreakCbProc handler; /* NOTE NOTE this handler runs in INTERRUPT CONTEXT */ |
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| 54 | void *private; /* closure pointer which is passed to the callback */ |
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| 55 | } BSP_UartBreakCbRec, *BSP_UartBreakCb; |
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| 56 | |
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| 57 | #define BIOCGETBREAKCB _IOR('b',1,sizeof(BSP_UartBreakCbRec)) |
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| 58 | #define BIOCSETBREAKCB _IOW('b',2,sizeof(BSP_UartBreakCbRec)) |
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| 59 | |
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[acc25ee] | 60 | /* |
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| 61 | * Command values for BSP_uart_intr_ctrl(), |
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| 62 | * values are strange in order to catch errors |
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| 63 | * with assert |
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| 64 | */ |
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| 65 | #define BSP_UART_INTR_CTRL_DISABLE (0) |
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| 66 | #define BSP_UART_INTR_CTRL_GDB (0xaa) /* RX only */ |
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| 67 | #define BSP_UART_INTR_CTRL_ENABLE (0xbb) /* Normal operations */ |
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| 68 | #define BSP_UART_INTR_CTRL_TERMIOS (0xcc) /* RX & line status */ |
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| 69 | |
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| 70 | /* Return values for uart_polled_status() */ |
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| 71 | #define BSP_UART_STATUS_ERROR (-1) /* No character */ |
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| 72 | #define BSP_UART_STATUS_NOCHAR (0) /* No character */ |
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| 73 | #define BSP_UART_STATUS_CHAR (1) /* Character present */ |
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| 74 | #define BSP_UART_STATUS_BREAK (2) /* Break point is detected */ |
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| 75 | |
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| 76 | /* PC UART definitions */ |
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| 77 | #define BSP_UART_COM1 (0) |
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| 78 | #define BSP_UART_COM2 (1) |
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| 79 | |
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| 80 | /* |
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| 81 | * Offsets from base |
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| 82 | */ |
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| 83 | |
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| 84 | /* DLAB 0 */ |
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| 85 | #define RBR (0) /* Rx Buffer Register (read) */ |
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| 86 | #define THR (0) /* Tx Buffer Register (write) */ |
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| 87 | #define IER (1) /* Interrupt Enable Register */ |
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| 88 | |
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| 89 | /* DLAB X */ |
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| 90 | #define IIR (2) /* Interrupt Ident Register (read) */ |
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| 91 | #define FCR (2) /* FIFO Control Register (write) */ |
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| 92 | #define LCR (3) /* Line Control Register */ |
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| 93 | #define MCR (4) /* Modem Control Register */ |
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| 94 | #define LSR (5) /* Line Status Register */ |
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| 95 | #define MSR (6) /* Modem Status Register */ |
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| 96 | #define SCR (7) /* Scratch register */ |
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| 97 | |
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| 98 | /* DLAB 1 */ |
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| 99 | #define DLL (0) /* Divisor Latch, LSB */ |
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| 100 | #define DLM (1) /* Divisor Latch, MSB */ |
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| 101 | #define AFR (2) /* Alternate Function register */ |
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| 102 | |
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| 103 | /* |
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| 104 | * Interrupt source definition via IIR |
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| 105 | */ |
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| 106 | #define MODEM_STATUS 0 |
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| 107 | #define NO_MORE_INTR 1 |
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| 108 | #define TRANSMITTER_HODING_REGISTER_EMPTY 2 |
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| 109 | #define RECEIVER_DATA_AVAIL 4 |
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| 110 | #define RECEIVER_ERROR 6 |
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| 111 | #define CHARACTER_TIMEOUT_INDICATION 12 |
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| 112 | |
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| 113 | /* |
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| 114 | * Bits definition of IER |
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| 115 | */ |
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| 116 | #define RECEIVE_ENABLE 0x1 |
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| 117 | #define TRANSMIT_ENABLE 0x2 |
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| 118 | #define RECEIVER_LINE_ST_ENABLE 0x4 |
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| 119 | #define MODEM_ENABLE 0x8 |
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| 120 | #define INTERRUPT_DISABLE 0x0 |
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| 121 | |
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| 122 | /* |
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| 123 | * Bits definition of the Line Status Register (LSR) |
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| 124 | */ |
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| 125 | #define DR 0x01 /* Data Ready */ |
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| 126 | #define OE 0x02 /* Overrun Error */ |
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| 127 | #define PE 0x04 /* Parity Error */ |
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| 128 | #define FE 0x08 /* Framing Error */ |
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| 129 | #define BI 0x10 /* Break Interrupt */ |
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| 130 | #define THRE 0x20 /* Transmitter Holding Register Empty */ |
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| 131 | #define TEMT 0x40 /* Transmitter Empty */ |
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| 132 | #define ERFIFO 0x80 /* Error receive Fifo */ |
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| 133 | |
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| 134 | /* |
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| 135 | * Bits definition of the MODEM Control Register (MCR) |
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| 136 | */ |
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| 137 | #define DTR 0x01 /* Data Terminal Ready */ |
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| 138 | #define RTS 0x02 /* Request To Send */ |
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| 139 | #define OUT_1 0x04 /* Output 1, (reserved on COMPAQ I/O Board) */ |
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| 140 | #define OUT_2 0x08 /* Output 2, Enable Asynchronous Port Interrupts */ |
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| 141 | #define LB 0x10 /* Enable Internal Loop Back */ |
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| 142 | |
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| 143 | /* |
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| 144 | * Bits definition of the Line Control Register (LCR) |
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| 145 | */ |
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| 146 | #define CHR_5_BITS 0 |
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| 147 | #define CHR_6_BITS 1 |
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| 148 | #define CHR_7_BITS 2 |
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| 149 | #define CHR_8_BITS 3 |
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| 150 | |
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| 151 | #define WL 0x03 /* Word length mask */ |
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| 152 | #define STB 0x04 /* 1 Stop Bit, otherwise 2 Stop Bits */ |
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| 153 | #define PEN 0x08 /* Parity Enabled */ |
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| 154 | #define EPS 0x10 /* Even Parity Select, otherwise Odd */ |
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| 155 | #define SP 0x20 /* Stick Parity */ |
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| 156 | #define BCB 0x40 /* Break Control Bit */ |
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| 157 | #define DLAB 0x80 /* Enable Divisor Latch Access */ |
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| 158 | |
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| 159 | /* |
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| 160 | * Bits definition of the MODEM Status Register (MSR) |
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| 161 | */ |
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| 162 | #define DCTS 0x01 /* Delta Clear To Send */ |
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| 163 | #define DDSR 0x02 /* Delta Data Set Ready */ |
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| 164 | #define TERI 0x04 /* Trailing Edge Ring Indicator */ |
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| 165 | #define DDCD 0x08 /* Delta Carrier Detect Indicator */ |
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| 166 | #define CTS 0x10 /* Clear To Send (when loop back is active) */ |
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| 167 | #define DSR 0x20 /* Data Set Ready (when loop back is active) */ |
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| 168 | #define RI 0x40 /* Ring Indicator (when loop back is active) */ |
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| 169 | #define DCD 0x80 /* Data Carrier Detect (when loop back is active) */ |
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| 170 | |
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| 171 | /* |
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| 172 | * Bits definition of the FIFO Control Register : WD16C552 or NS16550 |
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| 173 | */ |
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| 174 | |
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| 175 | #define FIFO_CTRL 0x01 /* Set to 1 permit access to other bits */ |
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| 176 | #define FIFO_EN 0x01 /* Enable the FIFO */ |
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| 177 | #define XMIT_RESET 0x02 /* Transmit FIFO Reset */ |
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| 178 | #define RCV_RESET 0x04 /* Receive FIFO Reset */ |
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| 179 | #define FCR3 0x08 /* do not understand manual! */ |
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| 180 | |
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| 181 | #define RECEIVE_FIFO_TRIGGER1 0x0 /* trigger recieve interrupt after 1 byte */ |
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| 182 | #define RECEIVE_FIFO_TRIGGER4 0x40 /* trigger recieve interrupt after 4 byte */ |
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| 183 | #define RECEIVE_FIFO_TRIGGER8 0x80 /* trigger recieve interrupt after 8 byte */ |
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| 184 | #define RECEIVE_FIFO_TRIGGER12 0xc0 /* trigger recieve interrupt after 12 byte */ |
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| 185 | #define TRIG_LEVEL 0xc0 /* Mask for the trigger level */ |
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| 186 | |
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| 187 | #endif /* _BSPUART_H */ |
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| 188 | |
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| 189 | |
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| 190 | |
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