1 | /* |
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2 | * This software is Copyright (C) 1998 by T.sqware - all rights limited |
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3 | * It is provided in to the public domain "as is", can be freely modified |
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4 | * as far as this copyight notice is kept unchanged, but does not imply |
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5 | * an endorsement by T.sqware of the product in which it is included. |
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6 | * |
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7 | * $Id$ |
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8 | */ |
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9 | |
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10 | #include <bsp.h> |
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11 | #include <bsp/irq.h> |
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12 | #include <bsp/uart.h> |
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13 | #include <rtems/libio.h> |
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14 | #include <assert.h> |
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15 | |
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16 | /* |
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17 | * Basic 16552 driver |
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18 | */ |
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19 | |
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20 | struct uart_data |
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21 | { |
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22 | int hwFlow; |
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23 | int baud; |
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24 | }; |
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25 | |
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26 | static struct uart_data uart_data[2]; |
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27 | |
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28 | /* |
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29 | * Macros to read/wirte register of uart, if configuration is |
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30 | * different just rewrite these macros |
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31 | */ |
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32 | |
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33 | static inline unsigned char |
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34 | uread(int uart, unsigned int reg) |
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35 | { |
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36 | register unsigned char val; |
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37 | |
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38 | if(uart == 0) |
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39 | { |
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40 | inport_byte(COM1_BASE_IO+reg, val); |
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41 | } |
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42 | else |
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43 | { |
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44 | inport_byte(COM2_BASE_IO+reg, val); |
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45 | } |
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46 | |
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47 | return val; |
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48 | } |
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49 | |
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50 | static inline void |
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51 | uwrite(int uart, int reg, unsigned int val) |
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52 | { |
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53 | if(uart == 0) |
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54 | { |
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55 | outport_byte(COM1_BASE_IO+reg, val); |
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56 | } |
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57 | else |
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58 | { |
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59 | outport_byte(COM2_BASE_IO+reg, val); |
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60 | } |
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61 | } |
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62 | |
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63 | #ifdef UARTDEBUG |
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64 | static void |
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65 | uartError(int uart) |
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66 | { |
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67 | unsigned char uartStatus, dummy; |
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68 | |
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69 | uartStatus = uread(uart, LSR); |
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70 | dummy = uread(uart, RBR); |
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71 | |
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72 | if (uartStatus & OE) |
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73 | printk("********* Over run Error **********\n"); |
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74 | if (uartStatus & PE) |
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75 | printk("********* Parity Error **********\n"); |
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76 | if (uartStatus & FE) |
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77 | printk("********* Framing Error **********\n"); |
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78 | if (uartStatus & BI) |
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79 | printk("********* Parity Error **********\n"); |
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80 | if (uartStatus & ERFIFO) |
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81 | printk("********* Error receive Fifo **********\n"); |
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82 | |
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83 | } |
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84 | #else |
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85 | inline void uartError(int uart) |
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86 | { |
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87 | unsigned char uartStatus; |
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88 | |
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89 | uartStatus = uread(uart, LSR); |
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90 | uartStatus = uread(uart, RBR); |
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91 | } |
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92 | #endif |
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93 | |
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94 | /* |
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95 | * Uart initialization, it is hardcoded to 8 bit, no parity, |
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96 | * one stop bit, FIFO, things to be changed |
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97 | * are baud rate and nad hw flow control, |
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98 | * and longest rx fifo setting |
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99 | */ |
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100 | void |
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101 | BSP_uart_init(int uart, int baud, int hwFlow) |
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102 | { |
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103 | unsigned char tmp; |
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104 | |
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105 | /* Sanity check */ |
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106 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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107 | |
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108 | switch(baud) |
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109 | { |
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110 | case 50: |
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111 | case 75: |
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112 | case 110: |
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113 | case 134: |
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114 | case 300: |
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115 | case 600: |
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116 | case 1200: |
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117 | case 2400: |
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118 | case 9600: |
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119 | case 19200: |
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120 | case 38400: |
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121 | case 57600: |
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122 | case 115200: |
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123 | break; |
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124 | default: |
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125 | assert(0); |
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126 | return; |
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127 | } |
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128 | |
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129 | /* Set DLAB bit to 1 */ |
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130 | uwrite(uart, LCR, DLAB); |
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131 | |
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132 | /* Set baud rate */ |
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133 | uwrite(uart, DLL, (BSPBaseBaud/baud) & 0xff); |
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134 | uwrite(uart, DLM, ((BSPBaseBaud/baud) >> 8) & 0xff); |
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135 | |
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136 | /* 8-bit, no parity , 1 stop */ |
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137 | uwrite(uart, LCR, CHR_8_BITS); |
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138 | |
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139 | |
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140 | /* Set DTR, RTS and OUT2 high */ |
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141 | uwrite(uart, MCR, DTR | RTS | OUT_2); |
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142 | |
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143 | /* Enable FIFO */ |
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144 | uwrite(uart, FCR, FIFO_EN | XMIT_RESET | RCV_RESET | RECEIVE_FIFO_TRIGGER12); |
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145 | |
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146 | /* Disable Interrupts */ |
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147 | uwrite(uart, IER, 0); |
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148 | |
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149 | /* Read status to clear them */ |
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150 | tmp = uread(uart, LSR); |
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151 | tmp = uread(uart, RBR); |
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152 | tmp = uread(uart, MSR); |
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153 | |
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154 | /* Remember state */ |
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155 | uart_data[uart].hwFlow = hwFlow; |
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156 | uart_data[uart].baud = baud; |
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157 | return; |
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158 | } |
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159 | |
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160 | /* |
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161 | * Set baud |
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162 | */ |
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163 | void |
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164 | BSP_uart_set_baud(int uart, int baud) |
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165 | { |
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166 | unsigned char mcr, ier; |
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167 | |
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168 | /* Sanity check */ |
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169 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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170 | |
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171 | /* |
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172 | * This function may be called whenever TERMIOS parameters |
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173 | * are changed, so we have to make sire that baud change is |
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174 | * indeed required |
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175 | */ |
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176 | |
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177 | if(baud == uart_data[uart].baud) |
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178 | { |
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179 | return; |
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180 | } |
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181 | |
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182 | mcr = uread(uart, MCR); |
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183 | ier = uread(uart, IER); |
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184 | |
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185 | BSP_uart_init(uart, baud, uart_data[uart].hwFlow); |
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186 | |
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187 | uwrite(uart, MCR, mcr); |
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188 | uwrite(uart, IER, ier); |
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189 | |
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190 | return; |
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191 | } |
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192 | |
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193 | /* |
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194 | * Enable/disable interrupts |
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195 | */ |
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196 | void |
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197 | BSP_uart_intr_ctrl(int uart, int cmd) |
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198 | { |
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199 | |
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200 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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201 | |
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202 | switch(cmd) |
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203 | { |
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204 | case BSP_UART_INTR_CTRL_DISABLE: |
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205 | uwrite(uart, IER, INTERRUPT_DISABLE); |
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206 | break; |
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207 | case BSP_UART_INTR_CTRL_ENABLE: |
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208 | if(uart_data[uart].hwFlow) |
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209 | { |
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210 | uwrite(uart, IER, |
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211 | (RECEIVE_ENABLE | |
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212 | TRANSMIT_ENABLE | |
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213 | RECEIVER_LINE_ST_ENABLE | |
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214 | MODEM_ENABLE |
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215 | ) |
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216 | ); |
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217 | } |
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218 | else |
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219 | { |
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220 | uwrite(uart, IER, |
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221 | (RECEIVE_ENABLE | |
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222 | TRANSMIT_ENABLE | |
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223 | RECEIVER_LINE_ST_ENABLE |
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224 | ) |
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225 | ); |
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226 | } |
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227 | break; |
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228 | case BSP_UART_INTR_CTRL_TERMIOS: |
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229 | if(uart_data[uart].hwFlow) |
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230 | { |
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231 | uwrite(uart, IER, |
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232 | (RECEIVE_ENABLE | |
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233 | RECEIVER_LINE_ST_ENABLE | |
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234 | MODEM_ENABLE |
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235 | ) |
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236 | ); |
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237 | } |
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238 | else |
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239 | { |
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240 | uwrite(uart, IER, |
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241 | (RECEIVE_ENABLE | |
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242 | RECEIVER_LINE_ST_ENABLE |
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243 | ) |
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244 | ); |
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245 | } |
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246 | break; |
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247 | case BSP_UART_INTR_CTRL_GDB: |
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248 | uwrite(uart, IER, RECEIVE_ENABLE); |
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249 | break; |
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250 | default: |
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251 | assert(0); |
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252 | break; |
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253 | } |
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254 | |
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255 | return; |
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256 | } |
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257 | |
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258 | void |
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259 | BSP_uart_throttle(int uart) |
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260 | { |
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261 | unsigned int mcr; |
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262 | |
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263 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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264 | |
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265 | if(!uart_data[uart].hwFlow) |
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266 | { |
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267 | /* Should not happen */ |
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268 | assert(0); |
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269 | return; |
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270 | } |
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271 | mcr = uread (uart, MCR); |
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272 | /* RTS down */ |
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273 | mcr &= ~RTS; |
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274 | uwrite(uart, MCR, mcr); |
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275 | |
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276 | return; |
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277 | } |
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278 | |
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279 | void |
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280 | BSP_uart_unthrottle(int uart) |
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281 | { |
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282 | unsigned int mcr; |
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283 | |
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284 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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285 | |
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286 | if(!uart_data[uart].hwFlow) |
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287 | { |
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288 | /* Should not happen */ |
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289 | assert(0); |
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290 | return; |
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291 | } |
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292 | mcr = uread (uart, MCR); |
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293 | /* RTS up */ |
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294 | mcr |= RTS; |
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295 | uwrite(uart, MCR, mcr); |
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296 | |
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297 | return; |
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298 | } |
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299 | |
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300 | /* |
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301 | * Status function, -1 if error |
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302 | * detected, 0 if no received chars available, |
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303 | * 1 if received char available, 2 if break |
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304 | * is detected, it will eat break and error |
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305 | * chars. It ignores overruns - we cannot do |
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306 | * anything about - it execpt count statistics |
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307 | * and we are not counting it. |
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308 | */ |
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309 | int |
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310 | BSP_uart_polled_status(int uart) |
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311 | { |
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312 | unsigned char val; |
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313 | |
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314 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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315 | |
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316 | val = uread(uart, LSR); |
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317 | |
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318 | if(val & BI) |
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319 | { |
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320 | /* BREAK found, eat character */ |
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321 | uread(uart, RBR); |
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322 | return BSP_UART_STATUS_BREAK; |
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323 | } |
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324 | |
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325 | if((val & (DR | OE | FE)) == 1) |
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326 | { |
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327 | /* No error, character present */ |
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328 | return BSP_UART_STATUS_CHAR; |
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329 | } |
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330 | |
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331 | if((val & (DR | OE | FE)) == 0) |
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332 | { |
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333 | /* Nothing */ |
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334 | return BSP_UART_STATUS_NOCHAR; |
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335 | } |
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336 | |
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337 | /* |
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338 | * Framing or parity error |
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339 | * eat character |
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340 | */ |
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341 | uread(uart, RBR); |
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342 | |
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343 | return BSP_UART_STATUS_ERROR; |
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344 | } |
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345 | |
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346 | |
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347 | /* |
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348 | * Polled mode write function |
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349 | */ |
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350 | void |
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351 | BSP_uart_polled_write(int uart, int val) |
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352 | { |
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353 | unsigned char val1; |
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354 | |
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355 | /* Sanity check */ |
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356 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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357 | |
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358 | for(;;) |
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359 | { |
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360 | if((val1=uread(uart, LSR)) & THRE) |
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361 | { |
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362 | break; |
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363 | } |
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364 | } |
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365 | |
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366 | if(uart_data[uart].hwFlow) |
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367 | { |
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368 | for(;;) |
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369 | { |
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370 | if(uread(uart, MSR) & CTS) |
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371 | { |
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372 | break; |
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373 | } |
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374 | } |
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375 | } |
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376 | |
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377 | uwrite(uart, THR, val & 0xff); |
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378 | |
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379 | return; |
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380 | } |
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381 | |
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382 | void |
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383 | BSP_output_char_via_serial(int val) |
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384 | { |
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385 | BSP_uart_polled_write(BSPConsolePort, val); |
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386 | if (val == '\n') BSP_uart_polled_write(BSPConsolePort,'\r'); |
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387 | } |
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388 | |
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389 | /* |
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390 | * Polled mode read function |
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391 | */ |
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392 | int |
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393 | BSP_uart_polled_read(int uart) |
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394 | { |
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395 | unsigned char val; |
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396 | |
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397 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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398 | |
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399 | for(;;) |
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400 | { |
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401 | if(uread(uart, LSR) & DR) |
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402 | { |
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403 | break; |
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404 | } |
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405 | } |
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406 | |
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407 | val = uread(uart, RBR); |
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408 | |
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409 | return (int)(val & 0xff); |
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410 | } |
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411 | |
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412 | unsigned |
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413 | BSP_poll_char_via_serial() |
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414 | { |
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415 | return BSP_uart_polled_read(BSPConsolePort); |
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416 | } |
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417 | |
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418 | |
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419 | /* ================ Termios support =================*/ |
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420 | |
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421 | static volatile int termios_stopped_com1 = 0; |
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422 | static volatile int termios_tx_active_com1 = 0; |
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423 | static void* termios_ttyp_com1 = NULL; |
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424 | static char termios_tx_hold_com1 = 0; |
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425 | static volatile char termios_tx_hold_valid_com1 = 0; |
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426 | |
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427 | static volatile int termios_stopped_com2 = 0; |
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428 | static volatile int termios_tx_active_com2 = 0; |
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429 | static void* termios_ttyp_com2 = NULL; |
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430 | static char termios_tx_hold_com2 = 0; |
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431 | static volatile char termios_tx_hold_valid_com2 = 0; |
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432 | |
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433 | /* |
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434 | * Set channel parameters |
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435 | */ |
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436 | void |
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437 | BSP_uart_termios_set(int uart, void *ttyp) |
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438 | { |
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439 | unsigned char val; |
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440 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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441 | |
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442 | if(uart == BSP_UART_COM1) |
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443 | { |
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444 | if(uart_data[uart].hwFlow) |
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445 | { |
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446 | val = uread(uart, MSR); |
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447 | |
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448 | termios_stopped_com1 = (val & CTS) ? 0 : 1; |
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449 | } |
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450 | else |
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451 | { |
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452 | termios_stopped_com1 = 0; |
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453 | } |
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454 | termios_tx_active_com1 = 0; |
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455 | termios_ttyp_com1 = ttyp; |
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456 | termios_tx_hold_com1 = 0; |
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457 | termios_tx_hold_valid_com1 = 0; |
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458 | } |
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459 | else |
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460 | { |
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461 | if(uart_data[uart].hwFlow) |
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462 | { |
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463 | val = uread(uart, MSR); |
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464 | |
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465 | termios_stopped_com2 = (val & CTS) ? 0 : 1; |
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466 | } |
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467 | else |
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468 | { |
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469 | termios_stopped_com2 = 0; |
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470 | } |
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471 | termios_tx_active_com2 = 0; |
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472 | termios_ttyp_com2 = ttyp; |
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473 | termios_tx_hold_com2 = 0; |
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474 | termios_tx_hold_valid_com2 = 0; |
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475 | } |
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476 | |
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477 | return; |
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478 | } |
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479 | |
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480 | int |
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481 | BSP_uart_termios_write_com1(int minor, const char *buf, int len) |
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482 | { |
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483 | assert(buf != NULL); |
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484 | |
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485 | if(len <= 0) |
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486 | { |
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487 | return 0; |
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488 | } |
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489 | |
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490 | /* If there TX buffer is busy - something is royally screwed up */ |
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491 | /* assert((uread(BSP_UART_COM1, LSR) & THRE) != 0); */ |
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492 | |
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493 | |
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494 | if(termios_stopped_com1) |
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495 | { |
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496 | /* CTS low */ |
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497 | termios_tx_hold_com1 = *buf; |
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498 | termios_tx_hold_valid_com1 = 1; |
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499 | return 0; |
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500 | } |
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501 | |
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502 | /* Write character */ |
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503 | uwrite(BSP_UART_COM1, THR, *buf & 0xff); |
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504 | |
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505 | /* Enable interrupts if necessary */ |
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506 | if(!termios_tx_active_com1 && uart_data[BSP_UART_COM1].hwFlow) |
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507 | { |
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508 | termios_tx_active_com1 = 1; |
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509 | uwrite(BSP_UART_COM1, IER, |
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510 | (RECEIVE_ENABLE | |
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511 | TRANSMIT_ENABLE | |
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512 | RECEIVER_LINE_ST_ENABLE | |
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513 | MODEM_ENABLE |
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514 | ) |
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515 | ); |
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516 | } |
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517 | else if(!termios_tx_active_com1) |
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518 | { |
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519 | termios_tx_active_com1 = 1; |
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520 | uwrite(BSP_UART_COM1, IER, |
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521 | (RECEIVE_ENABLE | |
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522 | TRANSMIT_ENABLE | |
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523 | RECEIVER_LINE_ST_ENABLE |
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524 | ) |
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525 | ); |
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526 | } |
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527 | |
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528 | return 0; |
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529 | } |
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530 | |
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531 | int |
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532 | BSP_uart_termios_write_com2(int minor, const char *buf, int len) |
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533 | { |
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534 | assert(buf != NULL); |
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535 | |
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536 | if(len <= 0) |
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537 | { |
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538 | return 0; |
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539 | } |
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540 | |
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541 | |
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542 | /* If there TX buffer is busy - something is royally screwed up */ |
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543 | assert((uread(BSP_UART_COM2, LSR) & THRE) != 0); |
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544 | |
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545 | if(termios_stopped_com2) |
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546 | { |
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547 | /* CTS low */ |
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548 | termios_tx_hold_com2 = *buf; |
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549 | termios_tx_hold_valid_com2 = 1; |
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550 | return 0; |
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551 | } |
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552 | |
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553 | /* Write character */ |
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554 | |
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555 | uwrite(BSP_UART_COM2, THR, *buf & 0xff); |
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556 | |
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557 | /* Enable interrupts if necessary */ |
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558 | if(!termios_tx_active_com2 && uart_data[BSP_UART_COM2].hwFlow) |
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559 | { |
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560 | termios_tx_active_com2 = 1; |
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561 | uwrite(BSP_UART_COM2, IER, |
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562 | (RECEIVE_ENABLE | |
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563 | TRANSMIT_ENABLE | |
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564 | RECEIVER_LINE_ST_ENABLE | |
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565 | MODEM_ENABLE |
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566 | ) |
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567 | ); |
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568 | } |
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569 | else if(!termios_tx_active_com2) |
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570 | { |
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571 | termios_tx_active_com2 = 1; |
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572 | uwrite(BSP_UART_COM2, IER, |
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573 | (RECEIVE_ENABLE | |
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574 | TRANSMIT_ENABLE | |
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575 | RECEIVER_LINE_ST_ENABLE |
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576 | ) |
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577 | ); |
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578 | } |
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579 | |
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580 | return 0; |
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581 | } |
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582 | |
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583 | |
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584 | void |
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585 | BSP_uart_termios_isr_com1(void) |
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586 | { |
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587 | unsigned char buf[40]; |
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588 | unsigned char val; |
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589 | int off, ret, vect; |
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590 | |
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591 | off = 0; |
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592 | |
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593 | for(;;) |
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594 | { |
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595 | vect = uread(BSP_UART_COM1, IIR) & 0xf; |
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596 | |
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597 | switch(vect) |
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598 | { |
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599 | case MODEM_STATUS : |
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600 | val = uread(BSP_UART_COM1, MSR); |
---|
601 | if(uart_data[BSP_UART_COM1].hwFlow) |
---|
602 | { |
---|
603 | if(val & CTS) |
---|
604 | { |
---|
605 | /* CTS high */ |
---|
606 | termios_stopped_com1 = 0; |
---|
607 | if(termios_tx_hold_valid_com1) |
---|
608 | { |
---|
609 | termios_tx_hold_valid_com1 = 0; |
---|
610 | BSP_uart_termios_write_com1(0, &termios_tx_hold_com1, |
---|
611 | 1); |
---|
612 | } |
---|
613 | } |
---|
614 | else |
---|
615 | { |
---|
616 | /* CTS low */ |
---|
617 | termios_stopped_com1 = 1; |
---|
618 | } |
---|
619 | } |
---|
620 | break; |
---|
621 | case NO_MORE_INTR : |
---|
622 | /* No more interrupts */ |
---|
623 | if(off != 0) |
---|
624 | { |
---|
625 | /* Update rx buffer */ |
---|
626 | rtems_termios_enqueue_raw_characters(termios_ttyp_com1, |
---|
627 | (char *)buf, |
---|
628 | off); |
---|
629 | } |
---|
630 | return; |
---|
631 | case TRANSMITTER_HODING_REGISTER_EMPTY : |
---|
632 | /* |
---|
633 | * TX holding empty: we have to disable these interrupts |
---|
634 | * if there is nothing more to send. |
---|
635 | */ |
---|
636 | |
---|
637 | ret = rtems_termios_dequeue_characters(termios_ttyp_com1, 1); |
---|
638 | |
---|
639 | /* If nothing else to send disable interrupts */ |
---|
640 | if(ret == 0 && uart_data[BSP_UART_COM1].hwFlow) |
---|
641 | { |
---|
642 | uwrite(BSP_UART_COM1, IER, |
---|
643 | (RECEIVE_ENABLE | |
---|
644 | RECEIVER_LINE_ST_ENABLE | |
---|
645 | MODEM_ENABLE |
---|
646 | ) |
---|
647 | ); |
---|
648 | termios_tx_active_com1 = 0; |
---|
649 | } |
---|
650 | else if(ret == 0) |
---|
651 | { |
---|
652 | uwrite(BSP_UART_COM1, IER, |
---|
653 | (RECEIVE_ENABLE | |
---|
654 | RECEIVER_LINE_ST_ENABLE |
---|
655 | ) |
---|
656 | ); |
---|
657 | termios_tx_active_com1 = 0; |
---|
658 | } |
---|
659 | break; |
---|
660 | case RECEIVER_DATA_AVAIL : |
---|
661 | case CHARACTER_TIMEOUT_INDICATION: |
---|
662 | /* RX data ready */ |
---|
663 | assert(off < sizeof(buf)); |
---|
664 | buf[off++] = uread(BSP_UART_COM1, RBR); |
---|
665 | break; |
---|
666 | case RECEIVER_ERROR: |
---|
667 | /* RX error: eat character */ |
---|
668 | uartError(BSP_UART_COM1); |
---|
669 | break; |
---|
670 | default: |
---|
671 | /* Should not happen */ |
---|
672 | assert(0); |
---|
673 | return; |
---|
674 | } |
---|
675 | } |
---|
676 | } |
---|
677 | |
---|
678 | void |
---|
679 | BSP_uart_termios_isr_com2() |
---|
680 | { |
---|
681 | unsigned char buf[40]; |
---|
682 | unsigned char val; |
---|
683 | int off, ret, vect; |
---|
684 | |
---|
685 | off = 0; |
---|
686 | |
---|
687 | for(;;) |
---|
688 | { |
---|
689 | vect = uread(BSP_UART_COM2, IIR) & 0xf; |
---|
690 | |
---|
691 | switch(vect) |
---|
692 | { |
---|
693 | case MODEM_STATUS : |
---|
694 | val = uread(BSP_UART_COM2, MSR); |
---|
695 | if(uart_data[BSP_UART_COM2].hwFlow) |
---|
696 | { |
---|
697 | if(val & CTS) |
---|
698 | { |
---|
699 | /* CTS high */ |
---|
700 | termios_stopped_com2 = 0; |
---|
701 | if(termios_tx_hold_valid_com2) |
---|
702 | { |
---|
703 | termios_tx_hold_valid_com2 = 0; |
---|
704 | BSP_uart_termios_write_com2(0, &termios_tx_hold_com2, |
---|
705 | 1); |
---|
706 | } |
---|
707 | } |
---|
708 | else |
---|
709 | { |
---|
710 | /* CTS low */ |
---|
711 | termios_stopped_com2 = 1; |
---|
712 | } |
---|
713 | } |
---|
714 | break; |
---|
715 | case NO_MORE_INTR : |
---|
716 | /* No more interrupts */ |
---|
717 | if(off != 0) |
---|
718 | { |
---|
719 | /* Update rx buffer */ |
---|
720 | rtems_termios_enqueue_raw_characters(termios_ttyp_com2, |
---|
721 | (char *)buf, |
---|
722 | off); |
---|
723 | } |
---|
724 | return; |
---|
725 | case TRANSMITTER_HODING_REGISTER_EMPTY : |
---|
726 | /* |
---|
727 | * TX holding empty: we have to disable these interrupts |
---|
728 | * if there is nothing more to send. |
---|
729 | */ |
---|
730 | |
---|
731 | ret = rtems_termios_dequeue_characters(termios_ttyp_com2, 1); |
---|
732 | |
---|
733 | /* If nothing else to send disable interrupts */ |
---|
734 | if(ret == 0 && uart_data[BSP_UART_COM2].hwFlow) |
---|
735 | { |
---|
736 | uwrite(BSP_UART_COM2, IER, |
---|
737 | (RECEIVE_ENABLE | |
---|
738 | RECEIVER_LINE_ST_ENABLE | |
---|
739 | MODEM_ENABLE |
---|
740 | ) |
---|
741 | ); |
---|
742 | termios_tx_active_com2 = 0; |
---|
743 | } |
---|
744 | else if(ret == 0) |
---|
745 | { |
---|
746 | uwrite(BSP_UART_COM2, IER, |
---|
747 | (RECEIVE_ENABLE | |
---|
748 | RECEIVER_LINE_ST_ENABLE |
---|
749 | ) |
---|
750 | ); |
---|
751 | termios_tx_active_com2 = 0; |
---|
752 | } |
---|
753 | break; |
---|
754 | case RECEIVER_DATA_AVAIL : |
---|
755 | case CHARACTER_TIMEOUT_INDICATION: |
---|
756 | /* RX data ready */ |
---|
757 | assert(off < sizeof(buf)); |
---|
758 | buf[off++] = uread(BSP_UART_COM2, RBR); |
---|
759 | break; |
---|
760 | case RECEIVER_ERROR: |
---|
761 | /* RX error: eat character */ |
---|
762 | uartError(BSP_UART_COM2); |
---|
763 | break; |
---|
764 | default: |
---|
765 | /* Should not happen */ |
---|
766 | assert(0); |
---|
767 | return; |
---|
768 | } |
---|
769 | } |
---|
770 | } |
---|
771 | |
---|
772 | |
---|
773 | |
---|
774 | |
---|
775 | |
---|
776 | |
---|
777 | |
---|
778 | |
---|