1 | /* |
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2 | * This software is Copyright (C) 1998 by T.sqware - all rights limited |
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3 | * It is provided in to the public domain "as is", can be freely modified |
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4 | * as far as this copyight notice is kept unchanged, but does not imply |
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5 | * an endorsement by T.sqware of the product in which it is included. |
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6 | * |
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7 | * $Id$ |
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8 | */ |
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9 | |
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10 | #include <bsp.h> |
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11 | #include <bsp/irq.h> |
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12 | #include <bsp/uart.h> |
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13 | #include <rtems/libio.h> |
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14 | #include <rtems/bspIo.h> |
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15 | #include <assert.h> |
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16 | |
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17 | /* |
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18 | * Basic 16552 driver |
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19 | */ |
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20 | |
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21 | struct uart_data |
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22 | { |
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23 | unsigned long ioBase; |
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24 | int hwFlow; |
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25 | int baud; |
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26 | BSP_UartBreakCbRec breakCallback; |
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27 | }; |
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28 | |
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29 | /* |
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30 | * Initialization of BSP specific data. |
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31 | * The constants are pulled in from a BSP |
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32 | * specific file, whereas all of the code |
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33 | * in this file is generic and makes no |
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34 | * assumptions about addresses, irq vectors |
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35 | * etc... |
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36 | */ |
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37 | |
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38 | #define UART_UNSUPP ((unsigned long)(-1)) |
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39 | |
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40 | static struct uart_data uart_data[2] = { |
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41 | { |
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42 | #ifdef BSP_UART_IOBASE_COM1 |
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43 | BSP_UART_IOBASE_COM1, |
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44 | #else |
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45 | UART_UNSUPP, |
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46 | #endif |
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47 | }, |
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48 | { |
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49 | #ifdef BSP_UART_IOBASE_COM2 |
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50 | BSP_UART_IOBASE_COM2, |
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51 | #else |
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52 | UART_UNSUPP, |
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53 | #endif |
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54 | }, |
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55 | }; |
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56 | |
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57 | #define MAX_UARTS (sizeof(uart_data)/sizeof(uart_data[0])) |
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58 | #define SANITY_CHECK(uart) \ |
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59 | assert( MAX_UARTS > (unsigned)(uart) && uart_data[(uart)].ioBase != UART_UNSUPP ) |
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60 | /* |
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61 | * Macros to read/wirte register of uart, if configuration is |
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62 | * different just rewrite these macros |
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63 | */ |
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64 | |
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65 | static inline unsigned char |
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66 | uread(int uart, unsigned int reg) |
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67 | { |
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68 | |
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69 | return in_8((unsigned char*)(uart_data[uart].ioBase + reg)); |
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70 | |
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71 | } |
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72 | |
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73 | static inline void |
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74 | uwrite(int uart, int reg, unsigned int val) |
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75 | { |
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76 | out_8((unsigned char*)(uart_data[uart].ioBase + reg), val); |
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77 | } |
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78 | |
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79 | #define UARTDEBUG |
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80 | #ifdef UARTDEBUG |
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81 | static void |
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82 | uartError(int uart, void *termiosPrivate) |
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83 | { |
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84 | unsigned char uartStatus, dummy; |
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85 | BSP_UartBreakCbProc h; |
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86 | |
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87 | uartStatus = uread(uart, LSR); |
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88 | dummy = uread(uart, RBR); |
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89 | |
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90 | if (uartStatus & OE) |
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91 | printk("********* Over run Error **********\n"); |
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92 | if (uartStatus & PE) |
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93 | printk("********* Parity Error **********\n"); |
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94 | if (uartStatus & FE) |
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95 | printk("********* Framing Error **********\n"); |
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96 | if (uartStatus & BI) { |
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97 | printk("********* BREAK INTERRUPT *********\n"); |
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98 | if ((h=uart_data[uart].breakCallback.handler)) |
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99 | h(uart, |
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100 | (dummy<<8)|uartStatus, |
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101 | termiosPrivate, |
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102 | uart_data[uart].breakCallback.private); |
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103 | |
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104 | } |
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105 | if (uartStatus & ERFIFO) |
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106 | printk("********* Error receive Fifo **********\n"); |
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107 | |
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108 | } |
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109 | #else |
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110 | inline void uartError(int uart, void *termiosPrivate) |
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111 | { |
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112 | unsigned char uartStatus,dummy; |
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113 | BSP_UartBreakCbProc h; |
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114 | |
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115 | uartStatus = uread(uart, LSR); |
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116 | dummy = uread(uart, RBR); |
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117 | if ((uartStatus & BI) && (h=uart_data[uart].breakCallback.handler)) |
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118 | h(uart, |
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119 | (dummy<<8)|uartStatus, |
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120 | termiosPrivate, |
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121 | uart_data[uart].breakCallback.private); |
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122 | } |
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123 | #endif |
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124 | |
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125 | /* |
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126 | * Uart initialization, it is hardcoded to 8 bit, no parity, |
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127 | * one stop bit, FIFO, things to be changed |
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128 | * are baud rate and nad hw flow control, |
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129 | * and longest rx fifo setting |
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130 | */ |
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131 | void |
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132 | BSP_uart_init(int uart, int baud, int hwFlow) |
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133 | { |
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134 | unsigned char tmp; |
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135 | |
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136 | /* Sanity check */ |
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137 | SANITY_CHECK(uart); |
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138 | |
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139 | switch(baud) |
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140 | { |
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141 | case 50: |
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142 | case 75: |
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143 | case 110: |
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144 | case 134: |
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145 | case 300: |
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146 | case 600: |
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147 | case 1200: |
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148 | case 2400: |
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149 | case 9600: |
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150 | case 19200: |
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151 | case 38400: |
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152 | case 57600: |
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153 | case 115200: |
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154 | break; |
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155 | default: |
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156 | assert(0); |
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157 | return; |
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158 | } |
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159 | |
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160 | /* Set DLAB bit to 1 */ |
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161 | uwrite(uart, LCR, DLAB); |
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162 | |
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163 | /* Set baud rate */ |
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164 | uwrite(uart, DLL, (BSPBaseBaud/baud) & 0xff); |
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165 | uwrite(uart, DLM, ((BSPBaseBaud/baud) >> 8) & 0xff); |
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166 | |
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167 | /* 8-bit, no parity , 1 stop */ |
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168 | uwrite(uart, LCR, CHR_8_BITS); |
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169 | |
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170 | |
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171 | /* Set DTR, RTS and OUT2 high */ |
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172 | uwrite(uart, MCR, DTR | RTS | OUT_2); |
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173 | |
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174 | /* Enable FIFO */ |
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175 | uwrite(uart, FCR, FIFO_EN | XMIT_RESET | RCV_RESET | RECEIVE_FIFO_TRIGGER12); |
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176 | |
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177 | /* Disable Interrupts */ |
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178 | uwrite(uart, IER, 0); |
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179 | |
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180 | /* Read status to clear them */ |
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181 | tmp = uread(uart, LSR); |
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182 | tmp = uread(uart, RBR); |
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183 | tmp = uread(uart, MSR); |
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184 | |
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185 | /* Remember state */ |
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186 | uart_data[uart].hwFlow = hwFlow; |
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187 | uart_data[uart].baud = baud; |
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188 | return; |
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189 | } |
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190 | |
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191 | /* |
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192 | * Set baud |
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193 | */ |
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194 | void |
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195 | BSP_uart_set_baud(int uart, int baud) |
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196 | { |
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197 | unsigned char mcr, ier; |
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198 | |
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199 | /* Sanity check */ |
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200 | SANITY_CHECK(uart); |
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201 | |
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202 | /* |
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203 | * This function may be called whenever TERMIOS parameters |
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204 | * are changed, so we have to make sire that baud change is |
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205 | * indeed required |
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206 | */ |
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207 | |
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208 | if(baud == uart_data[uart].baud) |
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209 | { |
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210 | return; |
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211 | } |
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212 | |
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213 | mcr = uread(uart, MCR); |
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214 | ier = uread(uart, IER); |
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215 | |
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216 | BSP_uart_init(uart, baud, uart_data[uart].hwFlow); |
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217 | |
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218 | uwrite(uart, MCR, mcr); |
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219 | uwrite(uart, IER, ier); |
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220 | |
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221 | return; |
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222 | } |
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223 | |
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224 | /* |
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225 | * Enable/disable interrupts |
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226 | */ |
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227 | void |
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228 | BSP_uart_intr_ctrl(int uart, int cmd) |
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229 | { |
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230 | |
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231 | SANITY_CHECK(uart); |
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232 | |
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233 | switch(cmd) |
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234 | { |
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235 | case BSP_UART_INTR_CTRL_DISABLE: |
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236 | uwrite(uart, IER, INTERRUPT_DISABLE); |
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237 | break; |
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238 | case BSP_UART_INTR_CTRL_ENABLE: |
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239 | if(uart_data[uart].hwFlow) |
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240 | { |
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241 | uwrite(uart, IER, |
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242 | (RECEIVE_ENABLE | |
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243 | TRANSMIT_ENABLE | |
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244 | RECEIVER_LINE_ST_ENABLE | |
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245 | MODEM_ENABLE |
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246 | ) |
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247 | ); |
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248 | } |
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249 | else |
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250 | { |
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251 | uwrite(uart, IER, |
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252 | (RECEIVE_ENABLE | |
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253 | TRANSMIT_ENABLE | |
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254 | RECEIVER_LINE_ST_ENABLE |
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255 | ) |
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256 | ); |
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257 | } |
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258 | break; |
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259 | case BSP_UART_INTR_CTRL_TERMIOS: |
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260 | if(uart_data[uart].hwFlow) |
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261 | { |
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262 | uwrite(uart, IER, |
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263 | (RECEIVE_ENABLE | |
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264 | RECEIVER_LINE_ST_ENABLE | |
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265 | MODEM_ENABLE |
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266 | ) |
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267 | ); |
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268 | } |
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269 | else |
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270 | { |
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271 | uwrite(uart, IER, |
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272 | (RECEIVE_ENABLE | |
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273 | RECEIVER_LINE_ST_ENABLE |
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274 | ) |
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275 | ); |
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276 | } |
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277 | break; |
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278 | case BSP_UART_INTR_CTRL_GDB: |
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279 | uwrite(uart, IER, RECEIVE_ENABLE); |
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280 | break; |
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281 | default: |
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282 | assert(0); |
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283 | break; |
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284 | } |
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285 | |
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286 | return; |
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287 | } |
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288 | |
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289 | void |
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290 | BSP_uart_throttle(int uart) |
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291 | { |
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292 | unsigned int mcr; |
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293 | |
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294 | SANITY_CHECK(uart); |
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295 | |
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296 | if(!uart_data[uart].hwFlow) |
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297 | { |
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298 | /* Should not happen */ |
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299 | assert(0); |
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300 | return; |
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301 | } |
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302 | mcr = uread (uart, MCR); |
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303 | /* RTS down */ |
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304 | mcr &= ~RTS; |
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305 | uwrite(uart, MCR, mcr); |
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306 | |
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307 | return; |
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308 | } |
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309 | |
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310 | void |
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311 | BSP_uart_unthrottle(int uart) |
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312 | { |
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313 | unsigned int mcr; |
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314 | |
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315 | SANITY_CHECK(uart); |
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316 | |
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317 | if(!uart_data[uart].hwFlow) |
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318 | { |
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319 | /* Should not happen */ |
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320 | assert(0); |
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321 | return; |
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322 | } |
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323 | mcr = uread (uart, MCR); |
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324 | /* RTS up */ |
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325 | mcr |= RTS; |
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326 | uwrite(uart, MCR, mcr); |
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327 | |
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328 | return; |
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329 | } |
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330 | |
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331 | /* |
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332 | * Status function, -1 if error |
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333 | * detected, 0 if no received chars available, |
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334 | * 1 if received char available, 2 if break |
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335 | * is detected, it will eat break and error |
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336 | * chars. It ignores overruns - we cannot do |
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337 | * anything about - it execpt count statistics |
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338 | * and we are not counting it. |
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339 | */ |
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340 | int |
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341 | BSP_uart_polled_status(int uart) |
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342 | { |
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343 | unsigned char val; |
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344 | |
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345 | SANITY_CHECK(uart); |
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346 | |
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347 | val = uread(uart, LSR); |
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348 | |
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349 | if(val & BI) |
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350 | { |
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351 | /* BREAK found, eat character */ |
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352 | uread(uart, RBR); |
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353 | return BSP_UART_STATUS_BREAK; |
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354 | } |
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355 | |
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356 | if((val & (DR | OE | FE)) == 1) |
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357 | { |
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358 | /* No error, character present */ |
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359 | return BSP_UART_STATUS_CHAR; |
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360 | } |
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361 | |
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362 | if((val & (DR | OE | FE)) == 0) |
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363 | { |
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364 | /* Nothing */ |
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365 | return BSP_UART_STATUS_NOCHAR; |
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366 | } |
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367 | |
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368 | /* |
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369 | * Framing or parity error |
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370 | * eat character |
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371 | */ |
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372 | uread(uart, RBR); |
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373 | |
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374 | return BSP_UART_STATUS_ERROR; |
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375 | } |
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376 | |
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377 | |
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378 | /* |
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379 | * Polled mode write function |
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380 | */ |
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381 | void |
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382 | BSP_uart_polled_write(int uart, int val) |
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383 | { |
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384 | unsigned char val1; |
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385 | |
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386 | /* Sanity check */ |
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387 | SANITY_CHECK(uart); |
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388 | |
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389 | for(;;) |
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390 | { |
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391 | if((val1=uread(uart, LSR)) & THRE) |
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392 | { |
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393 | break; |
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394 | } |
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395 | } |
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396 | |
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397 | if(uart_data[uart].hwFlow) |
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398 | { |
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399 | for(;;) |
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400 | { |
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401 | if(uread(uart, MSR) & CTS) |
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402 | { |
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403 | break; |
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404 | } |
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405 | } |
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406 | } |
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407 | |
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408 | uwrite(uart, THR, val & 0xff); |
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409 | |
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410 | return; |
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411 | } |
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412 | |
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413 | void |
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414 | BSP_output_char_via_serial(const char val) |
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415 | { |
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416 | BSP_uart_polled_write(BSPConsolePort, val); |
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417 | if (val == '\n') BSP_uart_polled_write(BSPConsolePort,'\r'); |
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418 | } |
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419 | |
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420 | /* |
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421 | * Polled mode read function |
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422 | */ |
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423 | int |
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424 | BSP_uart_polled_read(int uart) |
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425 | { |
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426 | unsigned char val; |
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427 | |
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428 | SANITY_CHECK(uart); |
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429 | |
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430 | for(;;) |
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431 | { |
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432 | if(uread(uart, LSR) & DR) |
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433 | { |
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434 | break; |
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435 | } |
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436 | } |
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437 | |
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438 | val = uread(uart, RBR); |
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439 | |
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440 | return (int)(val & 0xff); |
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441 | } |
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442 | |
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443 | unsigned |
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444 | BSP_poll_char_via_serial() |
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445 | { |
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446 | return BSP_uart_polled_read(BSPConsolePort); |
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447 | } |
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448 | |
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449 | static void |
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450 | uart_noop(const rtems_irq_connect_data *unused) |
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451 | { |
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452 | return; |
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453 | } |
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454 | |
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455 | /* note that the IRQ names contain _ISA_ for legacy |
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456 | * reasons. They can be any interrupt, depending |
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457 | * on the particular BSP... |
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458 | */ |
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459 | |
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460 | static int |
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461 | uart_isr_is_on(const rtems_irq_connect_data *irq) |
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462 | { |
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463 | int uart = (irq->name == BSP_ISA_UART_COM1_IRQ) ? |
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464 | BSP_UART_COM1 : BSP_UART_COM2; |
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465 | return uread(uart,IER); |
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466 | } |
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467 | |
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468 | static int |
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469 | doit(int uart, rtems_irq_hdl handler, int (*p)(const rtems_irq_connect_data*)) |
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470 | { |
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471 | rtems_irq_connect_data d={0}; |
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472 | d.name = (uart == BSP_UART_COM1) ? |
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473 | BSP_ISA_UART_COM1_IRQ : BSP_ISA_UART_COM2_IRQ; |
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474 | d.off = d.on = uart_noop; |
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475 | d.isOn = uart_isr_is_on; |
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476 | d.hdl = handler; |
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477 | return p(&d); |
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478 | } |
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479 | |
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480 | int |
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481 | BSP_uart_install_isr(int uart, rtems_irq_hdl handler) |
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482 | { |
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483 | return doit(uart, handler, BSP_install_rtems_irq_handler); |
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484 | } |
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485 | |
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486 | int |
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487 | BSP_uart_remove_isr(int uart, rtems_irq_hdl handler) |
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488 | { |
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489 | return doit(uart, handler, BSP_remove_rtems_irq_handler); |
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490 | } |
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491 | |
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492 | |
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493 | /* ================ Termios support =================*/ |
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494 | |
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495 | static volatile int termios_stopped_com[2] = {0,0}; |
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496 | static volatile int termios_tx_active_com[2] = {0,0}; |
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497 | static void* termios_ttyp_com[2] = {NULL,NULL}; |
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498 | static char termios_tx_hold_com[2] = {0,0}; |
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499 | static volatile char termios_tx_hold_valid_com[2] = {0,0}; |
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500 | |
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501 | /* |
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502 | * Set channel parameters |
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503 | */ |
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504 | void |
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505 | BSP_uart_termios_set(int uart, void *ttyp) |
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506 | { |
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507 | unsigned char val; |
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508 | SANITY_CHECK(uart); |
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509 | |
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510 | if(uart_data[uart].hwFlow) |
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511 | { |
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512 | val = uread(uart, MSR); |
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513 | |
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514 | termios_stopped_com[uart] = (val & CTS) ? 0 : 1; |
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515 | } |
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516 | else |
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517 | { |
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518 | termios_stopped_com[uart] = 0; |
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519 | } |
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520 | termios_tx_active_com[uart] = 0; |
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521 | termios_ttyp_com[uart] = ttyp; |
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522 | termios_tx_hold_com[uart] = 0; |
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523 | termios_tx_hold_valid_com[uart] = 0; |
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524 | |
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525 | return; |
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526 | } |
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527 | |
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528 | int |
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529 | BSP_uart_termios_write_com(int minor, const char *buf, int len) |
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530 | { |
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531 | int uart=minor; /* could differ, theoretically */ |
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532 | assert(buf != NULL); |
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533 | |
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534 | if(len <= 0) |
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535 | { |
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536 | return 0; |
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537 | } |
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538 | |
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539 | /* If there TX buffer is busy - something is royally screwed up */ |
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540 | /* assert((uread(BSP_UART_COM1, LSR) & THRE) != 0); */ |
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541 | |
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542 | |
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543 | if(termios_stopped_com[uart]) |
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544 | { |
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545 | /* CTS low */ |
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546 | termios_tx_hold_com[uart] = *buf; |
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547 | termios_tx_hold_valid_com[uart] = 1; |
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548 | return 0; |
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549 | } |
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550 | |
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551 | /* Write character */ |
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552 | uwrite(uart, THR, *buf & 0xff); |
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553 | |
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554 | /* Enable interrupts if necessary */ |
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555 | if(!termios_tx_active_com[uart] && uart_data[uart].hwFlow) |
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556 | { |
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557 | termios_tx_active_com[uart] = 1; |
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558 | uwrite(uart, IER, |
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559 | (RECEIVE_ENABLE | |
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560 | TRANSMIT_ENABLE | |
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561 | RECEIVER_LINE_ST_ENABLE | |
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562 | MODEM_ENABLE |
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563 | ) |
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564 | ); |
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565 | } |
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566 | else if(!termios_tx_active_com[uart]) |
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567 | { |
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568 | termios_tx_active_com[uart] = 1; |
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569 | uwrite(uart, IER, |
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570 | (RECEIVE_ENABLE | |
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571 | TRANSMIT_ENABLE | |
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572 | RECEIVER_LINE_ST_ENABLE |
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573 | ) |
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574 | ); |
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575 | } |
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576 | |
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577 | return 0; |
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578 | } |
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579 | |
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580 | static void |
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581 | BSP_uart_termios_isr_com(int uart) |
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582 | { |
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583 | unsigned char buf[40]; |
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584 | unsigned char val; |
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585 | int off, ret, vect; |
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586 | |
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587 | off = 0; |
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588 | |
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589 | for(;;) |
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590 | { |
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591 | vect = uread(uart, IIR) & 0xf; |
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592 | |
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593 | switch(vect) |
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594 | { |
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595 | case MODEM_STATUS : |
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596 | val = uread(uart, MSR); |
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597 | if(uart_data[uart].hwFlow) |
---|
598 | { |
---|
599 | if(val & CTS) |
---|
600 | { |
---|
601 | /* CTS high */ |
---|
602 | termios_stopped_com[uart] = 0; |
---|
603 | if(termios_tx_hold_valid_com[uart]) |
---|
604 | { |
---|
605 | termios_tx_hold_valid_com[uart] = 0; |
---|
606 | BSP_uart_termios_write_com(uart, &termios_tx_hold_com[uart], |
---|
607 | 1); |
---|
608 | } |
---|
609 | } |
---|
610 | else |
---|
611 | { |
---|
612 | /* CTS low */ |
---|
613 | termios_stopped_com[uart] = 1; |
---|
614 | } |
---|
615 | } |
---|
616 | break; |
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617 | case NO_MORE_INTR : |
---|
618 | /* No more interrupts */ |
---|
619 | if(off != 0) |
---|
620 | { |
---|
621 | /* Update rx buffer */ |
---|
622 | rtems_termios_enqueue_raw_characters(termios_ttyp_com[uart], |
---|
623 | (char *)buf, |
---|
624 | off); |
---|
625 | } |
---|
626 | return; |
---|
627 | case TRANSMITTER_HODING_REGISTER_EMPTY : |
---|
628 | /* |
---|
629 | * TX holding empty: we have to disable these interrupts |
---|
630 | * if there is nothing more to send. |
---|
631 | */ |
---|
632 | |
---|
633 | ret = rtems_termios_dequeue_characters(termios_ttyp_com[uart], 1); |
---|
634 | |
---|
635 | /* If nothing else to send disable interrupts */ |
---|
636 | if(ret == 0 && uart_data[uart].hwFlow) |
---|
637 | { |
---|
638 | uwrite(uart, IER, |
---|
639 | (RECEIVE_ENABLE | |
---|
640 | RECEIVER_LINE_ST_ENABLE | |
---|
641 | MODEM_ENABLE |
---|
642 | ) |
---|
643 | ); |
---|
644 | termios_tx_active_com[uart] = 0; |
---|
645 | } |
---|
646 | else if(ret == 0) |
---|
647 | { |
---|
648 | uwrite(uart, IER, |
---|
649 | (RECEIVE_ENABLE | |
---|
650 | RECEIVER_LINE_ST_ENABLE |
---|
651 | ) |
---|
652 | ); |
---|
653 | termios_tx_active_com[uart] = 0; |
---|
654 | } |
---|
655 | break; |
---|
656 | case RECEIVER_DATA_AVAIL : |
---|
657 | case CHARACTER_TIMEOUT_INDICATION: |
---|
658 | /* RX data ready */ |
---|
659 | assert(off < sizeof(buf)); |
---|
660 | buf[off++] = uread(uart, RBR); |
---|
661 | break; |
---|
662 | case RECEIVER_ERROR: |
---|
663 | /* RX error: eat character */ |
---|
664 | uartError(uart, termios_ttyp_com[uart]); |
---|
665 | break; |
---|
666 | default: |
---|
667 | /* Should not happen */ |
---|
668 | assert(0); |
---|
669 | return; |
---|
670 | } |
---|
671 | } |
---|
672 | } |
---|
673 | |
---|
674 | void |
---|
675 | BSP_uart_termios_isr_com1(void) |
---|
676 | { |
---|
677 | BSP_uart_termios_isr_com(BSP_UART_COM1); |
---|
678 | } |
---|
679 | |
---|
680 | void |
---|
681 | BSP_uart_termios_isr_com2(void) |
---|
682 | { |
---|
683 | BSP_uart_termios_isr_com(BSP_UART_COM2); |
---|
684 | } |
---|
685 | |
---|
686 | /* retrieve 'break' handler info */ |
---|
687 | int |
---|
688 | BSP_uart_get_break_cb(int uart, rtems_libio_ioctl_args_t *arg) |
---|
689 | { |
---|
690 | BSP_UartBreakCb cb=arg->buffer; |
---|
691 | unsigned long flags; |
---|
692 | SANITY_CHECK(uart); |
---|
693 | rtems_interrupt_disable(flags); |
---|
694 | *cb = uart_data[uart].breakCallback; |
---|
695 | rtems_interrupt_enable(flags); |
---|
696 | arg->ioctl_return=0; |
---|
697 | return RTEMS_SUCCESSFUL; |
---|
698 | } |
---|
699 | |
---|
700 | /* install 'break' handler */ |
---|
701 | int |
---|
702 | BSP_uart_set_break_cb(int uart, rtems_libio_ioctl_args_t *arg) |
---|
703 | { |
---|
704 | BSP_UartBreakCb cb=arg->buffer; |
---|
705 | unsigned long flags; |
---|
706 | SANITY_CHECK(uart); |
---|
707 | rtems_interrupt_disable(flags); |
---|
708 | uart_data[uart].breakCallback = *cb; |
---|
709 | rtems_interrupt_enable(flags); |
---|
710 | arg->ioctl_return=0; |
---|
711 | return RTEMS_SUCCESSFUL; |
---|
712 | } |
---|