source: rtems/c/src/lib/libbsp/powerpc/shared/bootloader/pci.c @ 513b6c4b

4.104.114.84.95
Last change on this file since 513b6c4b was 513b6c4b, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 27, 2004 at 9:44:10 PM

2003-11-01 Greg Menke <gregory.menke@…>

PR 606/bsps

  • bootloader/pci.c: Fixed IO remapping so buses >= 1 are remapped. Reduced PCI space to match bat2. Fixed incorrect region size calculation in pci_read_bases. Set PCI latency timers to known sane values. Changed bridge PCI settings to minimum sane instead of whatever sounded neat in the PCI spec. Force pf regions to memory mapped to preserve byte access.
  • Property mode set to 100644
File size: 41.1 KB
Line 
1/*
2 *  pci.c -- Crude pci handling for early boot.
3 *
4 *  Copyright (C) 1998, 1999 Gabriel Paubert, paubert@iram.es
5 *
6 *  Modified to compile in RTEMS development environment
7 *  by Eric Valette
8 *
9 *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
10 *
11 *  The license and distribution terms for this file may be
12 *  found in found in the file LICENSE in this distribution or at
13 *  http://www.rtems.com/license/LICENSE.
14 *
15 * $Id$
16 */
17
18#include <sys/types.h>
19#include <rtems/bspIo.h>
20#include <libcpu/spr.h>
21#include "bootldr.h"
22#include "pci.h"
23#include <libcpu/io.h>
24#include <libcpu/page.h>
25#include <bsp/consoleIo.h>
26
27#include <string.h>
28
29typedef unsigned int u32;
30
31
32
33/*
34#define DEBUG
35#define PCI_DEBUG
36*/
37
38/* Used to reorganize PCI space on stupid machines which spread resources
39 * across a wide address space. This is bad when P2P bridges are present
40 * or when it limits the mappings that a resource hog like a PCI<->VME
41 * bridge can use.
42 */
43
44typedef struct _pci_resource {
45      struct _pci_resource *next;
46      struct pci_dev *dev;
47      u_long base;    /* will be 64 bits on 64 bits machines */
48      u_long size;
49      u_char type;      /* 1 is I/O else low order 4 bits of the memory type */
50      u_char reg;       /* Register # in conf space header */
51      u_short cmd;    /* Original cmd byte */
52} pci_resource;
53
54typedef struct _pci_area {
55      struct _pci_area *next;
56      u_long start;
57      u_long end;
58      struct pci_bus *bus;
59      u_int flags;
60} pci_area;
61
62typedef struct _pci_area_head {
63      pci_area *head;
64      u_long mask;
65      int high; /* To allocate from top */
66} pci_area_head;
67
68#define PCI_AREA_PREFETCHABLE 0
69#define PCI_AREA_MEMORY 1
70#define PCI_AREA_IO 2
71
72struct _pci_private {
73      volatile u_int * config_addr;
74      volatile u_char * config_data;
75      struct pci_dev **last_dev_p;
76      struct pci_bus pci_root;
77      pci_resource *resources;
78      pci_area_head io, mem;
79
80} pci_private = {
81   config_addr: NULL,
82   config_data: (volatile u_char *) 0x80800000,
83   last_dev_p: NULL,
84   resources: NULL,
85   io: {NULL, 0xfff, 0},
86   mem: {NULL, 0xfffff, 0}
87};
88
89#define pci ((struct _pci_private *)(bd->pci_private))
90#define pci_root pci->pci_root
91
92#if !defined(DEBUG)
93#undef PCI_DEBUG
94/*
95  #else
96  #define PCI_DEBUG
97*/
98#endif
99
100#if defined(PCI_DEBUG)
101static void
102print_pci_resources(const char *s) {
103   pci_resource *p;
104   printk("%s", s);
105   for (p=pci->resources; p; p=p->next) {
106/*
107      printk("  %p:%p %06x %08lx %08lx %d\n",
108             p, p->next,
109             (p->dev->devfn<<8)+(p->dev->bus->number<<16)
110             +0x10+p->reg*4,
111             p->base,
112             p->size,
113             p->type);
114*/
115
116      printk("  %p:%p %d:%02x (%04x:%04x) %08lx %08lx %d\n",
117             p, p->next,
118             p->dev->bus->number, PCI_SLOT(p->dev->devfn),
119             p->dev->vendor, p->dev->device,
120             p->base,
121             p->size,
122             p->type);
123
124   }
125}
126
127static void
128print_pci_area(pci_area *p) {
129   for (; p; p=p->next) {
130      printk("    %p:%p %p %08lx %08lx\n",
131             p, p->next, p->bus, p->start, p->end);
132   }
133}
134
135static void
136print_pci_areas(const char *s) {
137   printk("%s  PCI I/O areas:\n",s);
138   print_pci_area(pci->io.head);
139   printk("  PCI memory areas:\n");
140   print_pci_area(pci->mem.head);
141}
142#else
143#define print_pci_areas(x)
144#define print_pci_resources(x)
145#endif
146
147/* Maybe there are some devices who use a size different
148 * from the alignment. For now we assume both are the same.
149 * The blacklist might be used for other weird things in the future too,
150 * since weird non PCI complying devices seem to proliferate these days.
151 */
152
153struct blacklist_entry {
154      u_short vendor, device;
155      u_char reg;
156      u_long actual_size;
157};
158
159#define BLACKLIST(vid, did, breg, actual_size) \
160        {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##vid##_##did, breg, actual_size}
161
162static struct blacklist_entry blacklist[] = {
163   BLACKLIST(S3, TRIO, 0, 0x04000000),
164   {0xffff, 0, 0, 0}
165};
166
167/* This function filters resources and then inserts them into a list of
168 * configurable pci resources.
169 */
170
171#define AREA(r) \
172(((r->type&PCI_BASE_ADDRESS_SPACE)==PCI_BASE_ADDRESS_SPACE_IO) ? PCI_AREA_IO :\
173          ((r->type&PCI_BASE_ADDRESS_MEM_PREFETCH) ? PCI_AREA_PREFETCHABLE :\
174           PCI_AREA_MEMORY))
175
176static int insert_before(pci_resource *e, pci_resource *t) {
177   if (e->dev->bus->number != t->dev->bus->number)
178      return e->dev->bus->number > t->dev->bus->number;
179   if (AREA(e) != AREA(t)) return AREA(e)<AREA(t);
180   return (e->size > t->size);
181}
182
183static void insert_resource(pci_resource *r) {
184   struct blacklist_entry *b;
185   pci_resource *p;
186   if (!r) return;
187
188   /* First fixup in case we have a blacklist entry. Note that this
189    * may temporarily leave a resource in an inconsistent state: with
190    * (base & (size-1)) !=0. This is harmless.
191    */
192   for (b=blacklist; b->vendor!=0xffff; b++) {
193      if ((r->dev->vendor==b->vendor) &&
194          (r->dev->device==b->device) &&
195          (r->reg==b->reg)) {
196         r->size=b->actual_size;
197         break;
198      }
199   }
200
201   /* Motorola NT firmware does not configure pci devices which are not
202    * required for booting, others do. For now:
203    * - allocated devices in the ISA range (64kB I/O, 16Mb memory)
204    *   but non zero base registers are left as is.
205    * - all other registers, whether already allocated or not, are
206    *   reallocated unless they require an inordinate amount of
207    *   resources (>256 Mb for memory >64kB for I/O). These
208    *   devices with too large mapping requirements are simply ignored
209    *   and their bases are set to 0. This should disable the
210    *   corresponding decoders according to the PCI specification.
211    *   Many devices are buggy in this respect, however, but the
212    *   limits have hopefully been set high enough to avoid problems.
213    */
214
215   /*
216   ** This is little ugly below.  It seems that at least on the MCP750,
217   ** the PBC has some default IO space mappings that the bsp #defines
218   ** that read/write to PCI I/O space assume, particuarly the i8259
219   ** manipulation code.  So, if we allow the small IO spaces on PCI bus
220   ** 0 and 1 to be remapped, the registers can shift out from under the
221   ** #defines.  This is particuarly awful, but short of redefining the
222   ** PCI I/O primitives to be functions with base addresses read from
223   ** the hardware, we are stuck with the kludge below.  Note that
224   ** everything is remapped on the CPCI backplane and any downstream
225   ** hardware, its just the builtin stuff we're tiptoeing around.
226   **
227   ** Gregm, 7/16/2003
228   **
229   ** Gregm, changed 11/2003 so IO devices only on bus 0 zero are not
230   ** remapped.  This covers the builtin pc-like io devices- but
231   ** properly maps IO devices on higher busses.
232   */
233   if( r->dev->bus->number == 0 )
234   {
235   if ((r->type==PCI_BASE_ADDRESS_SPACE_IO)
236       ? (r->base && r->base <0x10000)
237       : (r->base && r->base <0x1000000)) {
238
239#ifdef PCI_DEBUG
240         printk("freeing region;  %p:%p %d:%02x (%04x:%04x) %08lx %08lx %d\n",
241                r, r->next,
242                r->dev->bus->number, PCI_SLOT(r->dev->devfn),
243                r->dev->vendor, r->dev->device,
244                r->base,
245                r->size,
246                r->type);
247#endif
248      sfree(r);
249      return;
250   }
251   }
252
253   if ((r->type==PCI_BASE_ADDRESS_SPACE_IO)
254       ? (r->size >= 0x10000)
255       : (r->size >= 0x10000000)) {
256      r->size  = 0;
257      r->base  = 0;
258   }
259
260   /* Now insert into the list sorting by
261    * 1) decreasing bus number
262    * 2) space: prefetchable memory, non-prefetchable and finally I/O
263    * 3) decreasing size
264    */
265   if (!pci->resources || insert_before(r, pci->resources)) {
266      r->next = pci->resources;
267      pci->resources=r;
268   } else {
269      for (p=pci->resources; p->next; p=p->next) {
270         if (insert_before(r, p->next)) break;
271      }
272      r->next=p->next;
273      p->next=r;
274   }
275}
276
277/* This version only works for bus 0. I don't have any P2P bridges to test
278 * a more sophisticated version which has therefore not been implemented.
279 * Prefetchable memory is not yet handled correctly either.
280 * And several levels of PCI bridges much less even since there must be
281 * allocated together to be able to setup correctly the top bridge.
282 */
283
284static u_long find_range(u_char bus, u_char type,
285                         pci_resource **first,
286                         pci_resource **past, u_int *flags) {
287   pci_resource *p;
288   u_long total=0;
289   u_int fl=0;
290
291   for (p=pci->resources; p; p=p->next)
292   {
293      if ((p->dev->bus->number == bus) &&
294          AREA(p)==type) break;
295   }
296
297   *first = p;
298
299   for (; p; p=p->next)
300   {
301      if ((p->dev->bus->number != bus) ||
302          AREA(p)!=type || p->size == 0) break;
303      total = total+p->size;
304      fl |= 1<<p->type;
305   }
306
307   *past = p;
308   /* This will be used later to tell whether there are any 32 bit
309    * devices in an area which could be mapped higher than 4Gb
310    * on 64 bits architectures
311    */
312   *flags = fl;
313   return total;
314}
315
316static inline void init_free_area(pci_area_head *h, u_long start,
317                                  u_long end, u_int mask, int high) {
318   pci_area *p;
319   p = salloc(sizeof(pci_area));
320   if (!p) return;
321   h->head = p;
322   p->next = NULL;
323   p->start = (start+mask)&~mask;
324   p->end = (end-mask)|mask;
325   p->bus = NULL;
326   h->mask = mask;
327   h->high = high;
328}
329
330static void insert_area(pci_area_head *h, pci_area *p) {
331   pci_area *q = h->head;
332   if (!p) return;
333   if (q && (q->start< p->start)) {
334      for(;q->next && q->next->start<p->start; q = q->next);
335      if ((q->end >= p->start) ||
336          (q->next && p->end>=q->next->start)) {
337         sfree(p);
338         printk("Overlapping pci areas!\n");
339         return;
340      }
341      p->next = q->next;
342      q->next = p;
343   } else { /* Insert at head */
344      if (q && (p->end >= q->start)) {
345         sfree(p);
346         printk("Overlapping pci areas!\n");
347         return;
348      }
349      p->next = q;
350      h->head = p;
351   }
352}
353
354static
355void remove_area(pci_area_head *h, pci_area *p)
356{
357   pci_area *q = h->head;
358
359   if (!p || !q) return;
360   if (q==p)
361   {
362      h->head = q->next;
363      return;
364   }
365   for(;q && q->next!=p; q=q->next);
366   if (q) q->next=p->next;
367}
368
369static pci_area * alloc_area(pci_area_head *h, struct pci_bus *bus,
370                             u_long required, u_long mask, u_int flags) {
371   pci_area *p;
372   pci_area *from, *split, *new;
373
374   required = (required+h->mask) & ~h->mask;
375   for (p=h->head, from=NULL; p; p=p->next)
376   {
377      u_long l1 = ((p->start+required+mask)&~mask)-1;
378      u_long l2 = ((p->start+mask)&~mask)+required-1;
379      /* Allocated areas point to the bus to which they pertain */
380      if (p->bus) continue;
381      if ((p->end)>=l1 || (p->end)>=l2) from=p;
382      if (from && !h->high) break;
383   }
384   if (!from) return NULL;
385
386   split = salloc(sizeof(pci_area));
387   new = salloc(sizeof(pci_area));
388   /* If allocation of new succeeds then allocation of split has
389    * also been successful (given the current mm algorithms) !
390    */
391   if (!new) {
392      sfree(split);
393      return NULL;
394   }
395   new->bus = bus;
396   new->flags = flags;
397   /* Now allocate pci_space taking alignment into account ! */
398   if (h->high)
399   {
400      u_long l1 = ((from->end+1)&~mask)-required;
401      u_long l2 = (from->end+1-required)&~mask;
402      new->start = (l1>l2) ? l1 : l2;
403      split->end = from->end;
404      from->end = new->start-1;
405      split->start = new->start+required;
406      new->end = new->start+required-1;
407   }
408   else
409   {
410      u_long l1 = ((from->start+mask)&~mask)+required-1;
411      u_long l2 = ((from->start+required+mask)&~mask)-1;
412      new->end = (l1<l2) ? l1 : l2;
413      split->start = from->start;
414      from->start = new->end+1;
415      new->start = new->end+1-required;
416      split->end = new->start-1;
417   }
418
419   if (from->end+1 == from->start) remove_area(h, from);
420   if (split->end+1 != split->start)
421   {
422      split->bus = NULL;
423      insert_area(h, split);
424   }
425   else
426   {
427      sfree(split);
428   }
429   insert_area(h, new);
430   print_pci_areas("alloc_area called:\n");
431   return new;
432}
433
434static inline
435void alloc_space(pci_area *p, pci_resource *r)
436{
437   if (p->start & (r->size-1)) {
438      r->base = p->end+1-r->size;
439      p->end -= r->size;
440   } else {
441      r->base = p->start;
442      p->start += r->size;
443   }
444}
445
446static void reconfigure_bus_space(u_char bus, u_char type, pci_area_head *h)
447{
448   pci_resource *first, *past, *r;
449   pci_area *area, tmp;
450   u_int flags;
451   u_int required = find_range(bus, type, &first, &past, &flags);
452
453   if (required==0) return;
454
455   area = alloc_area(h, first->dev->bus, required, first->size-1, flags);
456
457   if (!area) return;
458
459   tmp = *area;
460   for (r=first; r!=past; r=r->next)
461   {
462      alloc_space(&tmp, r);
463   }
464}
465
466#define BUS0_IO_START           0x10000
467#define BUS0_IO_END             0x1ffff
468#define BUS0_MEM_START          0x1000000
469#define BUS0_MEM_END            0x3f00000
470
471#define BUSREST_IO_START        0x20000
472#define BUSREST_IO_END          0x7ffff
473#define BUSREST_MEM_START       0x4000000
474#define BUSREST_MEM_END        0x10000000
475
476static void reconfigure_pci(void) {
477   pci_resource *r;
478   struct pci_dev *dev;
479
480   /* FIXME: for now memory is relocated from low, it's better
481    * to start from higher addresses.
482    */
483   /*
484   init_free_area(&pci->io, 0x10000, 0x7fffff, 0xfff, 0);
485   init_free_area(&pci->mem, 0x1000000, 0x3cffffff, 0xfffff, 0);
486   */
487
488   init_free_area(&pci->io, BUS0_IO_START, BUS0_IO_END, 0xfff, 0);
489   init_free_area(&pci->mem, BUS0_MEM_START, BUS0_MEM_END, 0xfffff, 0);
490
491   /* First reconfigure the I/O space, this will be more
492    * complex when there is more than 1 bus. And 64 bits
493    * devices are another kind of problems.
494    */
495   reconfigure_bus_space(0, PCI_AREA_IO, &pci->io);
496   reconfigure_bus_space(0, PCI_AREA_MEMORY, &pci->mem);
497   reconfigure_bus_space(0, PCI_AREA_PREFETCHABLE, &pci->mem);
498
499   /* Now we have to touch the configuration space of all
500    * the devices to remap them better than they are right now.
501    * This is done in 3 steps:
502    * 1) first disable I/O and memory response of all devices
503    * 2) modify the base registers
504    * 3) restore the original PCI_COMMAND register.
505    */
506   for (r=pci->resources; r; r= r->next) {
507      if (!r->dev->sysdata) {
508         r->dev->sysdata=r;
509         pci_read_config_word(r->dev, PCI_COMMAND, &r->cmd);
510         pci_write_config_word(r->dev, PCI_COMMAND,
511                               r->cmd & ~(PCI_COMMAND_IO|
512                                          PCI_COMMAND_MEMORY));
513      }
514   }
515
516   for (r=pci->resources; r; r= r->next) {
517      pci_write_config_dword(r->dev,
518                             PCI_BASE_ADDRESS_0+(r->reg<<2),
519                             r->base);
520      if ((r->type&
521           (PCI_BASE_ADDRESS_SPACE|
522            PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
523          (PCI_BASE_ADDRESS_SPACE_MEMORY|
524           PCI_BASE_ADDRESS_MEM_TYPE_64)) {
525         pci_write_config_dword(r->dev,
526                                PCI_BASE_ADDRESS_1+(r->reg<<2),
527                                0);
528      }
529   }
530   for (dev=bd->pci_devices; dev; dev= dev->next) {
531      if (dev->sysdata) {
532         pci_write_config_word(dev, PCI_COMMAND,
533                               ((pci_resource *)dev->sysdata)
534                               ->cmd);
535         dev->sysdata=NULL;
536      }
537   }
538}
539
540static int
541indirect_pci_read_config_byte(unsigned char bus, unsigned char dev_fn,
542                              unsigned char offset, unsigned char *val) {
543   out_be32(pci->config_addr,
544            0x80|(bus<<8)|(dev_fn<<16)|((offset&~3)<<24));
545   *val=in_8(pci->config_data + (offset&3));
546   return PCIBIOS_SUCCESSFUL;
547}
548
549static int
550indirect_pci_read_config_word(unsigned char bus, unsigned char dev_fn,
551                              unsigned char offset, unsigned short *val) {
552   *val = 0xffff;
553   if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
554   out_be32(pci->config_addr,
555            0x80|(bus<<8)|(dev_fn<<16)|((offset&~3)<<24));
556   *val=in_le16((volatile u_short *)(pci->config_data + (offset&3)));
557   return PCIBIOS_SUCCESSFUL;
558}
559
560static int
561indirect_pci_read_config_dword(unsigned char bus, unsigned char dev_fn,
562                               unsigned char offset, unsigned int *val) {
563   *val = 0xffffffff;
564   if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
565   out_be32(pci->config_addr,
566            0x80|(bus<<8)|(dev_fn<<16)|(offset<<24));
567   *val=in_le32((volatile u_int *)pci->config_data);
568   return PCIBIOS_SUCCESSFUL;
569}
570
571static int
572indirect_pci_write_config_byte(unsigned char bus, unsigned char dev_fn,
573                               unsigned char offset, unsigned char val) {
574   out_be32(pci->config_addr,
575            0x80|(bus<<8)|(dev_fn<<16)|((offset&~3)<<24));
576   out_8(pci->config_data + (offset&3), val);
577   return PCIBIOS_SUCCESSFUL;
578}
579
580static int
581indirect_pci_write_config_word(unsigned char bus, unsigned char dev_fn,
582                               unsigned char offset, unsigned short val) {
583   if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
584   out_be32(pci->config_addr,
585            0x80|(bus<<8)|(dev_fn<<16)|((offset&~3)<<24));
586   out_le16((volatile u_short *)(pci->config_data + (offset&3)), val);
587   return PCIBIOS_SUCCESSFUL;
588}
589
590static int
591indirect_pci_write_config_dword(unsigned char bus, unsigned char dev_fn,
592                                unsigned char offset, unsigned int val) {
593   if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
594   out_be32(pci->config_addr,
595            0x80|(bus<<8)|(dev_fn<<16)|(offset<<24));
596   out_le32((volatile u_int *)pci->config_data, val);
597   return PCIBIOS_SUCCESSFUL;
598}
599
600static const struct pci_config_access_functions indirect_functions = {
601   indirect_pci_read_config_byte,
602   indirect_pci_read_config_word,
603   indirect_pci_read_config_dword,
604   indirect_pci_write_config_byte,
605   indirect_pci_write_config_word,
606   indirect_pci_write_config_dword
607};
608
609static int
610direct_pci_read_config_byte(unsigned char bus, unsigned char dev_fn,
611                            unsigned char offset, unsigned char *val) {
612   if (bus != 0 || (1<<PCI_SLOT(dev_fn) & 0xff8007fe)) {
613      *val=0xff;
614      return PCIBIOS_DEVICE_NOT_FOUND;
615   }
616   *val=in_8(pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1)
617             + (PCI_FUNC(dev_fn)<<8) + offset);
618   return PCIBIOS_SUCCESSFUL;
619}
620
621static int
622direct_pci_read_config_word(unsigned char bus, unsigned char dev_fn,
623                            unsigned char offset, unsigned short *val) {
624   *val = 0xffff;
625   if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
626   if (bus != 0 || (1<<PCI_SLOT(dev_fn) & 0xff8007fe)) {
627      return PCIBIOS_DEVICE_NOT_FOUND;
628   }
629   *val=in_le16((volatile u_short *)
630                (pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1)
631                 + (PCI_FUNC(dev_fn)<<8) + offset));
632   return PCIBIOS_SUCCESSFUL;
633}
634
635static int
636direct_pci_read_config_dword(unsigned char bus, unsigned char dev_fn,
637                             unsigned char offset, unsigned int *val) {
638   *val = 0xffffffff;
639   if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
640   if (bus != 0 || (1<<PCI_SLOT(dev_fn) & 0xff8007fe)) {
641      return PCIBIOS_DEVICE_NOT_FOUND;
642   }
643   *val=in_le32((volatile u_int *)
644                (pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1)
645                 + (PCI_FUNC(dev_fn)<<8) + offset));
646   return PCIBIOS_SUCCESSFUL;
647}
648
649static int
650direct_pci_write_config_byte(unsigned char bus, unsigned char dev_fn,
651                             unsigned char offset, unsigned char val) {
652   if (bus != 0 || (1<<PCI_SLOT(dev_fn) & 0xff8007fe)) {
653      return PCIBIOS_DEVICE_NOT_FOUND;
654   }
655   out_8(pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1)
656         + (PCI_FUNC(dev_fn)<<8) + offset,
657         val);
658   return PCIBIOS_SUCCESSFUL;
659}
660
661static int
662direct_pci_write_config_word(unsigned char bus, unsigned char dev_fn,
663                             unsigned char offset, unsigned short val) {
664   if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
665   if (bus != 0 || (1<<PCI_SLOT(dev_fn) & 0xff8007fe)) {
666      return PCIBIOS_DEVICE_NOT_FOUND;
667   }
668   out_le16((volatile u_short *)
669            (pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1)
670             + (PCI_FUNC(dev_fn)<<8) + offset),
671            val);
672   return PCIBIOS_SUCCESSFUL;
673}
674
675static int
676direct_pci_write_config_dword(unsigned char bus, unsigned char dev_fn,
677                              unsigned char offset, unsigned int val) {
678   if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
679   if (bus != 0 || (1<<PCI_SLOT(dev_fn) & 0xff8007fe)) {
680      return PCIBIOS_DEVICE_NOT_FOUND;
681   }
682   out_le32((volatile u_int *)
683            (pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1)
684             + (PCI_FUNC(dev_fn)<<8) + offset),
685            val);
686   return PCIBIOS_SUCCESSFUL;
687}
688
689static const struct pci_config_access_functions direct_functions = {
690   direct_pci_read_config_byte,
691   direct_pci_read_config_word,
692   direct_pci_read_config_dword,
693   direct_pci_write_config_byte,
694   direct_pci_write_config_word,
695   direct_pci_write_config_dword
696};
697
698void pci_read_bases(struct pci_dev *dev, unsigned int howmany)
699{
700   unsigned int reg, nextreg;
701
702#define REG (PCI_BASE_ADDRESS_0 + (reg<<2))
703
704   u_short cmd;
705   u32 l, ml;
706   pci_read_config_word(dev, PCI_COMMAND, &cmd);
707
708   for(reg=0; reg<howmany; reg=nextreg)
709   {
710      pci_resource *r;
711
712      nextreg=reg+1;
713      pci_read_config_dword(dev, REG, &l);
714#if 0
715      if (l == 0xffffffff /*AJF || !l*/) continue;
716#endif
717      /* Note that disabling the memory response of a host bridge
718       * would lose data if a DMA transfer were in progress. In a
719       * bootloader we don't care however. Also we can't print any
720       * message for a while since we might just disable the console.
721       */
722      pci_write_config_word(dev, PCI_COMMAND, cmd &
723                            ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
724      pci_write_config_dword(dev, REG, ~0);
725      pci_read_config_dword(dev, REG, &ml);
726      pci_write_config_dword(dev, REG, l);
727
728      /* Reenable the device now that we've played with
729       * base registers.
730       */
731      pci_write_config_word(dev, PCI_COMMAND, cmd);
732
733      /* seems to be an unused entry skip it */
734      if ( ml == 0 || ml == 0xffffffff ) continue;
735
736      if ((l &
737           (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK))
738          == (PCI_BASE_ADDRESS_MEM_TYPE_64
739              |PCI_BASE_ADDRESS_SPACE_MEMORY)) {
740         nextreg=reg+2;
741      }
742      dev->base_address[reg] = l;
743      r = salloc(sizeof(pci_resource));
744      if (!r) {
745         printk("Error allocating pci_resource struct.\n");
746         continue;
747      }
748      r->dev = dev;
749      r->reg = reg;
750      if ((l&PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
751         r->type = l&~PCI_BASE_ADDRESS_IO_MASK;
752         r->base = l&PCI_BASE_ADDRESS_IO_MASK;
753         /* r->size = ~(ml&PCI_BASE_ADDRESS_IO_MASK)+1; */
754      } else {
755         r->type = l&~PCI_BASE_ADDRESS_MEM_MASK;
756         r->base = l&PCI_BASE_ADDRESS_MEM_MASK;
757         /* r->size = ~(ml&PCI_BASE_ADDRESS_MEM_MASK)+1; */
758      }
759
760      /* find the first bit set to one after the base
761         address type bits to find length of region */
762      {
763         unsigned int c= 16 , val= 0;
764         while( !(val= ml & c) ) c <<= 1;
765         r->size = val;
766      }
767
768#ifdef PCI_DEBUG
769      printk("   readbase bus %d, (%04x:%04x), base %08x, size %08x, type %d\n",
770             r->dev->bus->number, 
771             r->dev->vendor,
772             r->dev->device,
773             r->base,
774             r->size,
775             r->type );
776#endif
777
778      /* Check for the blacklisted entries */
779      insert_resource(r);
780   }
781}
782
783u_int pci_scan_bus(struct pci_bus *bus)
784{
785   unsigned int devfn, l, max, class;
786   unsigned char irq, hdr_type, is_multi = 0;
787   struct pci_dev *dev, **bus_last;
788   struct pci_bus *child;
789
790#if 0
791   printk("scanning pci bus %d\n", bus->number );
792#endif
793
794   bus_last = &bus->devices;
795   max = bus->secondary;
796   for (devfn = 0; devfn < 0xff; ++devfn) {
797      if (PCI_FUNC(devfn) && !is_multi) {
798         /* not a multi-function device */
799         continue;
800      }
801      if (pcibios_read_config_byte(bus->number, devfn, PCI_HEADER_TYPE, &hdr_type))
802         continue;
803      if (!PCI_FUNC(devfn))
804         is_multi = hdr_type & 0x80;
805
806      if (pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID, &l) ||
807          /* some broken boards return 0 if a slot is empty: */
808          l == 0xffffffff || l == 0x00000000 || l == 0x0000ffff || l == 0xffff0000) {
809         is_multi = 0;
810         continue;
811      }
812
813      dev = salloc(sizeof(*dev));
814      dev->bus = bus;
815      dev->devfn  = devfn;
816      dev->vendor = l & 0xffff;
817      dev->device = (l >> 16) & 0xffff;
818
819      pcibios_read_config_dword(bus->number, devfn,
820                                PCI_CLASS_REVISION, &class);
821      class >>= 8;                                  /* upper 3 bytes */
822      dev->class = class;
823      class >>= 8;
824      dev->hdr_type = hdr_type;
825
826      switch (hdr_type & 0x7f) {                    /* header type */
827         case PCI_HEADER_TYPE_NORMAL:               /* standard header */
828            if (class == PCI_CLASS_BRIDGE_PCI)
829               goto bad;
830            /*
831             * If the card generates interrupts, read IRQ number
832             * (some architectures change it during pcibios_fixup())
833             */
834            pcibios_read_config_byte(bus->number, dev->devfn, PCI_INTERRUPT_PIN, &irq);
835            if (irq)
836               pcibios_read_config_byte(bus->number, dev->devfn, PCI_INTERRUPT_LINE, &irq);
837            dev->irq = irq;
838            /*
839             * read base address registers, again pcibios_fixup() can
840             * tweak these
841             */
842            pci_read_bases(dev, 6);
843            pcibios_read_config_dword(bus->number, devfn, PCI_ROM_ADDRESS, &l);
844            dev->rom_address = (l == 0xffffffff) ? 0 : l;
845            break;
846         case PCI_HEADER_TYPE_BRIDGE:               /* bridge header */
847            if (class != PCI_CLASS_BRIDGE_PCI)
848               goto bad;
849            pci_read_bases(dev, 2);
850            pcibios_read_config_dword(bus->number, devfn, PCI_ROM_ADDRESS1, &l);
851            dev->rom_address = (l == 0xffffffff) ? 0 : l;
852            break;
853         case PCI_HEADER_TYPE_CARDBUS:              /* CardBus bridge header */
854            if (class != PCI_CLASS_BRIDGE_CARDBUS)
855               goto bad;
856            pci_read_bases(dev, 1);
857            break;
858
859         default:                                   /* unknown header */
860        bad:
861            printk("PCI device with unknown header type %d ignored.\n",
862                   hdr_type&0x7f);
863            continue;
864      }
865
866      /*
867       * Put it into the global PCI device chain. It's used to
868       * find devices once everything is set up.
869       */
870      *pci->last_dev_p = dev;
871      pci->last_dev_p = &dev->next;
872
873      /*
874       * Now insert it into the list of devices held
875       * by the parent bus.
876       */
877      *bus_last = dev;
878      bus_last = &dev->sibling;
879
880   }
881
882   /*
883    * After performing arch-dependent fixup of the bus, look behind
884    * all PCI-to-PCI bridges on this bus.
885    */
886   for(dev=bus->devices; dev; dev=dev->sibling)
887      /*
888       * If it's a bridge, scan the bus behind it.
889       */
890      if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
891         unsigned int buses;
892         unsigned int devfn = dev->devfn;
893         unsigned short cr;
894
895         /*
896          * Insert it into the tree of buses.
897          */
898         child = salloc(sizeof(*child));
899         child->next = bus->children;
900         bus->children = child;
901         child->self = dev;
902         child->parent = bus;
903
904         /*
905          * Set up the primary, secondary and subordinate
906          * bus numbers.
907          */
908         child->number = child->secondary = ++max;
909         child->primary = bus->secondary;
910         child->subordinate = 0xff;
911         /*
912          * Clear all status bits and turn off memory,
913          * I/O and master enables.
914          */
915         pcibios_read_config_word(bus->number, devfn, PCI_COMMAND, &cr);
916         pcibios_write_config_word(bus->number, devfn, PCI_COMMAND, 0x0000);
917         pcibios_write_config_word(bus->number, devfn, PCI_STATUS, 0xffff);
918         /*
919          * Read the existing primary/secondary/subordinate bus
920          * number configuration to determine if the PCI bridge
921          * has already been configured by the system.  If so,
922          * do not modify the configuration, merely note it.
923          */
924         pcibios_read_config_dword(bus->number, devfn, PCI_PRIMARY_BUS, &buses);
925         if ((buses & 0xFFFFFF) != 0)
926         {
927            unsigned int cmax;
928
929            child->primary = buses & 0xFF;
930            child->secondary = (buses >> 8) & 0xFF;
931            child->subordinate = (buses >> 16) & 0xFF;
932            child->number = child->secondary;
933            cmax = pci_scan_bus(child);
934            if (cmax > max) max = cmax;
935         }
936         else
937         {
938            /*
939             * Configure the bus numbers for this bridge:
940             */
941            buses &= 0xff000000;
942            buses |=
943               (((unsigned int)(child->primary)     <<  0) |
944                ((unsigned int)(child->secondary)   <<  8) |
945                ((unsigned int)(child->subordinate) << 16));
946            pcibios_write_config_dword(bus->number, devfn, PCI_PRIMARY_BUS, buses);
947            /*
948             * Now we can scan all subordinate buses:
949             */
950            max = pci_scan_bus(child);
951            /*
952             * Set the subordinate bus number to its real
953             * value:
954             */
955            child->subordinate = max;
956            buses = (buses & 0xff00ffff)
957               | ((unsigned int)(child->subordinate) << 16);
958            pcibios_write_config_dword(bus->number, devfn, PCI_PRIMARY_BUS, buses);
959         }
960         pcibios_write_config_word(bus->number, devfn, PCI_COMMAND, cr );
961      }
962
963   /*
964    * We've scanned the bus and so we know all about what's on
965    * the other side of any bridges that may be on this bus plus
966    * any devices.
967    *
968    * Return how far we've got finding sub-buses.
969    */
970   return max;
971}
972
973#if 0
974
975void
976pci_fixup(void)
977{
978   struct pci_dev *p;
979   struct pci_bus *bus;
980
981   for (bus = &pci_root; bus; bus=bus->next)
982   {
983      for (p=bus->devices; p; p=p->sibling)
984      {
985      }
986   }
987}
988
989static void print_pci_info()
990{
991   pci_resource *r;
992   struct pci_bus *pb = &pci_root;
993
994   printk("\n");
995   printk("PCI busses:\n");
996
997   for(pb= &pci_root; pb; pb=pb->children )
998   {
999      printk("   number %d, primary %d, secondary %d, subordinate %d\n",
1000             pb->number,
1001             pb->primary,
1002             pb->secondary,
1003             pb->subordinate );
1004      printk("   bridge; vendor %04x, device %04x\n",
1005             pb->self->vendor,
1006             pb->self->device );
1007
1008      {
1009         struct pci_dev *pd;
1010
1011         for(pd= pb->devices; pd; pd=pd->sibling )
1012         {
1013            printk("       vendor %04x, device %04x, irq %d\n",
1014                   pd->vendor,
1015                   pd->device,
1016                   pd->irq );
1017
1018         }
1019         printk("\n");
1020      }
1021
1022   }
1023   printk("\n");
1024
1025   printk("PCI resources:\n");
1026   for (r=pci->resources; r; r= r->next)
1027   {
1028      printk("   bus %d, vendor %04x, device %04x, base %08x, size %08x, type %d\n",
1029             r->dev->bus->number,
1030             r->dev->vendor,
1031             r->dev->device,
1032             r->base,
1033             r->size,
1034             r->type );
1035   }
1036   printk("\n");
1037
1038   return;
1039}
1040
1041#endif
1042
1043static struct _addr_start
1044{
1045      uint32_t   start_pcimem;
1046      uint32_t   start_pciio;
1047      uint32_t   start_prefetch;
1048} astart;
1049
1050static pci_resource *enum_device_resources( struct pci_dev *pdev, int i )
1051{
1052   pci_resource *r;
1053
1054   for(r= pci->resources; r; r= r->next )
1055   {
1056      if( r->dev == pdev )
1057      {
1058         if( i-- == 0 ) break;
1059      }
1060   }
1061   return r;
1062}
1063
1064static void recursive_bus_reconfigure( struct pci_bus *pbus )
1065{
1066   struct pci_dev       *pdev;
1067   struct pci_bus       *childbus;
1068   int  isroot = 0;
1069
1070   if( !pbus )
1071   {
1072      /* start with the root bus */
1073      astart.start_pcimem   = BUSREST_MEM_START;
1074      astart.start_pciio    = BUSREST_IO_START;
1075      astart.start_prefetch = ((BUSREST_MEM_END >> 16) << 16);
1076
1077      pbus = &pci_root;
1078      isroot = -1;
1079   }
1080
1081#define WRITE_BRIDGE_IO
1082#define WRITE_BRIDGE_MEM
1083#define WRITE_BRIDGE_PF
1084#define WRITE_BRIDGE_ENABLE
1085
1086/*
1087** Run thru the p2p bridges on this bus and recurse into subordinate busses
1088*/
1089   for( childbus= pbus->children; childbus; childbus= childbus->next )
1090   {
1091      pdev= childbus->self;
1092
1093      pcibios_write_config_byte(pdev->bus->number, pdev->devfn, PCI_LATENCY_TIMER,     0x80 );
1094      pcibios_write_config_byte(pdev->bus->number, pdev->devfn, PCI_SEC_LATENCY_TIMER, 0x80 );
1095
1096      {
1097         struct _addr_start   addrhold;
1098         uint8_t              base8, limit8;
1099         uint16_t             base16, limit16, ubase16, ulimit16;
1100
1101         /* save the base address values */
1102         memcpy( &addrhold, &astart, sizeof(struct _addr_start));
1103
1104         recursive_bus_reconfigure( childbus );
1105
1106#ifdef PCI_DEBUG
1107         printk("pci: configuring bus %d bridge (%04x:%04x), bus %d : (%d-%d)\n",
1108                pdev->bus->number,
1109                pdev->vendor,
1110                pdev->device,
1111                childbus->primary,
1112                childbus->secondary,
1113                childbus->subordinate );
1114#endif
1115
1116         /*
1117          * use the current values & the saved ones to figure out
1118          * the address spaces for the bridge
1119          */
1120
1121         if( addrhold.start_pciio == astart.start_pciio )
1122         {
1123            base8 = limit8 = 0xff;
1124            ubase16 = ulimit16 = 0xffff;
1125         }
1126         else
1127         {
1128            base8    = (uint8_t) ((addrhold.start_pciio >> 8) & 0xf0);
1129            ubase16  = (uint16_t)(addrhold.start_pciio >> 16);
1130            limit8   = (uint8_t) ((astart.start_pciio >> 8 ) & 0xf0);
1131            ulimit16 = (uint16_t)(astart.start_pciio >> 16);
1132            astart.start_pciio += 0x1000;
1133         }
1134
1135#ifdef PCI_DEBUG
1136         printk("pci:     io base %08x limit %08x\n", (base8<<8)+(ubase16<<16), (limit8<<8)+(ulimit16<<16));
1137#endif
1138#ifdef WRITE_BRIDGE_IO
1139         pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_IO_BASE_UPPER16, ubase16 );
1140         pcibios_write_config_byte(pdev->bus->number, pdev->devfn, PCI_IO_BASE, base8 );
1141
1142         pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_IO_LIMIT_UPPER16, ulimit16 );
1143         pcibios_write_config_byte(pdev->bus->number, pdev->devfn, PCI_IO_LIMIT, limit8 );
1144#endif
1145
1146         if( addrhold.start_pcimem == astart.start_pcimem )
1147         {
1148            limit16 = 0;
1149            base16 = 0xffff;
1150         }
1151         else
1152         {
1153            limit16= (uint16_t)((astart.start_pcimem >> 16) & 0xfff0);
1154            base16 = (uint16_t)((addrhold.start_pcimem >> 16) & 0xfff0);
1155            astart.start_pcimem += 0x100000;
1156         }
1157#ifdef PCI_DEBUG
1158         printk("pci:      memory %04x, limit %04x\n", base16, limit16);
1159#endif
1160#ifdef WRITE_BRIDGE_MEM
1161         pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_MEMORY_BASE, base16 );
1162         pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_MEMORY_LIMIT, limit16 );
1163#endif
1164
1165
1166         if( astart.start_prefetch == addrhold.start_prefetch )
1167         {
1168            limit16 = 0;
1169            base16 = 0xffff;
1170         }
1171         else
1172         {
1173            limit16= (uint16_t)((addrhold.start_prefetch >> 16) & 0xfff0);
1174            base16 = (uint16_t)((astart.start_prefetch >> 16) & 0xfff0);
1175            astart.start_prefetch -= 0x100000;
1176         }
1177#ifdef PCI_DEBUG
1178         printk("pci:   pf memory %04x, limit %04x\n", base16, limit16);
1179#endif
1180#ifdef WRITE_BRIDGE_PF
1181         pcibios_write_config_dword(pdev->bus->number, pdev->devfn, PCI_PREF_BASE_UPPER32, 0);
1182         pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_PREF_MEMORY_BASE, base16 );
1183         pcibios_write_config_dword(pdev->bus->number, pdev->devfn, PCI_PREF_LIMIT_UPPER32, 0);
1184         pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_PREF_MEMORY_LIMIT, limit16 );
1185#endif
1186
1187#ifdef WRITE_BRIDGE_ENABLE
1188         pcibios_write_config_word(pdev->bus->number, 
1189                                   pdev->devfn, 
1190                                   PCI_BRIDGE_CONTROL, 
1191                                   (unsigned16)( 0 ));
1192
1193         pcibios_write_config_word(pdev->bus->number, 
1194                                   pdev->devfn, 
1195                                   PCI_COMMAND, 
1196                                   (unsigned16)( PCI_COMMAND_IO | 
1197                                                 PCI_COMMAND_MEMORY |
1198                                                 PCI_COMMAND_MASTER ));
1199#endif
1200      }
1201   }
1202
1203   if( !isroot )
1204   {
1205#ifdef PCI_DEBUG
1206      printk("pci: Configuring devices on bus %d\n", pbus->number);
1207#endif
1208      /*
1209      ** Run thru this bus and set up addresses for all the non-bridge devices
1210      */
1211      for( pdev = pbus->devices; pdev; pdev= pdev->sibling )
1212      {
1213         if( (pdev->class >> 8) != PCI_CLASS_BRIDGE_PCI )
1214         {
1215            pci_resource *r;
1216            int i = 0;
1217            unsigned alloc;
1218
1219            /* enumerate all the resources defined by this device & reserve space
1220            ** for each of their defined regions.
1221            */
1222
1223#ifdef PCI_DEBUG
1224            printk("pci: configuring; vendor %04x, device %04x\n", pdev->vendor, pdev->device );
1225#endif
1226
1227            while( (r= enum_device_resources( pdev, i++ )) )
1228            {
1229               /*
1230               ** Force all memory spaces to be non-prefetchable because
1231               ** on the pci bus, byte-wise reads against prefetchable
1232               ** memory are applied as 32 bit reads, which is a pain
1233               ** when you're trying to talk to hardware.  This is a
1234               ** little sub-optimal because the algorithm doesn't sort
1235               ** the address regions to pack them in, OTOH, perhaps its
1236               ** not so bad because the inefficient packing will help
1237               ** avoid buffer overflow/underflow problems.
1238               */
1239#if 0
1240               if( (r->type & PCI_BASE_ADDRESS_MEM_PREFETCH) )
1241               {
1242                  /* prefetchable space */
1243
1244                  /* shift base pointer down to an integer multiple of the size of the desired region */
1245                  astart.start_prefetch -= (alloc= ((r->size / PAGE_SIZE) + 1) * PAGE_SIZE);
1246                  /* shift base pointer down to an integer multiple of the size of the desired region */
1247                  astart.start_prefetch = (astart.start_prefetch / r->size) * r->size;
1248
1249                  r->base = astart.start_prefetch;
1250#ifdef PCI_DEBUG
1251                  printk("pci:       pf %08X, size %08X, alloc %08X\n", r->base, r->size, alloc );
1252#endif
1253               }
1254#endif
1255               if( r->type & PCI_BASE_ADDRESS_SPACE_IO )
1256               {
1257                  /* io space */
1258
1259                  /* shift base pointer up to an integer multiple of the size of the desired region */
1260                  if( astart.start_pciio % r->size )
1261                     astart.start_pciio = (((astart.start_pciio / r->size) + 1) * r->size);
1262
1263                  r->base = astart.start_pciio;
1264                  astart.start_pciio += (alloc= ((r->size / PAGE_SIZE) + 1) * PAGE_SIZE);
1265#ifdef PCI_DEBUG
1266                  printk("pci:      io  %08X, size %08X, alloc %08X\n", r->base, r->size, alloc );
1267#endif
1268               }
1269               else
1270               {
1271                  /* memory space */
1272
1273                  /* shift base pointer up to an integer multiple of the size of the desired region */
1274                  if( astart.start_pcimem % r->size )
1275                     astart.start_pcimem = (((astart.start_pcimem / r->size) + 1) * r->size);
1276
1277                  r->base = astart.start_pcimem;
1278                  astart.start_pcimem += (alloc= ((r->size / PAGE_SIZE) + 1) * PAGE_SIZE);
1279#ifdef PCI_DEBUG
1280                  printk("pci:      mem %08X, size %08X, alloc %08X\n", r->base, r->size, alloc );
1281#endif
1282               }
1283            }
1284
1285         }
1286      }
1287   }
1288
1289}
1290
1291void pci_init(void)
1292{
1293   PPC_DEVICE *hostbridge;
1294
1295   if (pci->last_dev_p) {
1296      printk("Two or more calls to pci_init!\n");
1297      return;
1298   }
1299   pci->last_dev_p = &(bd->pci_devices);
1300   hostbridge=residual_find_device(PROCESSORDEVICE, NULL,
1301                                   BridgeController,
1302                                   PCIBridge, -1, 0);
1303   if (hostbridge) {
1304      if (hostbridge->DeviceId.Interface==PCIBridgeIndirect) {
1305         bd->pci_functions=&indirect_functions;
1306         /* Should be extracted from residual data,
1307          * indeed MPC106 in CHRP mode is different,
1308          * but we should not use residual data in
1309          * this case anyway.
1310          */
1311         pci->config_addr = ((volatile u_int *)
1312                             (ptr_mem_map->io_base+0xcf8));
1313         pci->config_data = ptr_mem_map->io_base+0xcfc;
1314      } else if(hostbridge->DeviceId.Interface==PCIBridgeDirect) {
1315         bd->pci_functions=&direct_functions;
1316         pci->config_data=(u_char *) 0x80800000;
1317      } else {
1318      }
1319   } else {
1320      /* Let us try by experimentation at our own risk! */
1321      u_int id0;
1322      bd->pci_functions = &direct_functions;
1323      /* On all direct bridges I know the host bridge itself
1324       * appears as device 0 function 0.
1325       */
1326      pcibios_read_config_dword(0, 0, PCI_VENDOR_ID, &id0);
1327      if (id0==~0U) {
1328         bd->pci_functions = &indirect_functions;
1329         pci->config_addr = ((volatile u_int *)
1330                             (ptr_mem_map->io_base+0xcf8));
1331         pci->config_data = ptr_mem_map->io_base+0xcfc;
1332      }
1333      /* Here we should check that the host bridge is actually
1334       * present, but if it not, we are in such a desperate
1335       * situation, that we probably can't even tell it.
1336       */
1337   }
1338   /* Now build a small database of all found PCI devices */
1339   printk("\nPCI: Probing PCI hardware\n");
1340   pci_root.subordinate=pci_scan_bus(&pci_root);
1341
1342   print_pci_resources("Installed PCI resources:\n");
1343
1344   recursive_bus_reconfigure(NULL);
1345
1346   reconfigure_pci();
1347
1348   print_pci_resources("Allocated PCI resources:\n");
1349
1350#if 0
1351   print_pci_info();
1352#endif
1353}
1354
1355/* eof */
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