source: rtems/c/src/lib/libbsp/powerpc/shared/bootloader/pci.c @ 0b8a6d7

Last change on this file since 0b8a6d7 was 0b8a6d7, checked in by Joel Sherrill <joel@…>, on Mar 28, 2018 at 4:17:45 PM

Eliminate PowerPC libcpu/page.h

Started to eliminate warnings and then realized that only one one-line
macro in the file was used by a few files. The rest of the file was
was not needed. Eliminate the file.

Closes #3354.

  • Property mode set to 100644
File size: 42.0 KB
Line 
1/*
2 *  pci.c -- Crude pci handling for early boot.
3 *
4 *  Copyright (C) 1998, 1999 Gabriel Paubert, paubert@iram.es
5 *
6 *  Modified to compile in RTEMS development environment
7 *  by Eric Valette
8 *
9 *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.org/license/LICENSE.
14 */
15
16#include <sys/types.h>
17#include <rtems/bspIo.h>
18#include <libcpu/spr.h>
19#include "bootldr.h"
20#include "pci.h"
21#include <libcpu/io.h>
22#include <bsp/consoleIo.h>
23#include <string.h>
24#include <bsp.h>
25
26#include <string.h>
27
28
29/*
30#define DEBUG
31#define PCI_DEBUG
32*/
33
34/* Used to reorganize PCI space on stupid machines which spread resources
35 * across a wide address space. This is bad when P2P bridges are present
36 * or when it limits the mappings that a resource hog like a PCI<->VME
37 * bridge can use.
38 */
39
40typedef struct _pci_resource {
41      struct _pci_resource *next;
42      struct pci_dev *dev;
43      u_long base;    /* will be 64 bits on 64 bits machines */
44      u_long size;
45      u_char type;      /* 1 is I/O else low order 4 bits of the memory type */
46      u_char reg;       /* Register # in conf space header */
47      u_short cmd;    /* Original cmd byte */
48} pci_resource;
49
50typedef struct _pci_area {
51      struct _pci_area *next;
52      u_long start;
53      u_long end;
54      struct pci_bus *bus;
55      u_int flags;
56} pci_area;
57
58typedef struct _pci_area_head {
59      pci_area *head;
60      u_long mask;
61      int high; /* To allocate from top */
62} pci_area_head;
63
64#define PCI_AREA_PREFETCHABLE 0
65#define PCI_AREA_MEMORY 1
66#define PCI_AREA_IO 2
67
68struct _pci_private {
69      volatile void * config_addr;
70      volatile u_char * config_data;
71      struct pci_dev **last_dev_p;
72      struct pci_bus pci_root;
73      pci_resource *resources;
74      pci_area_head io, mem;
75
76} pci_private = {
77   config_addr: NULL,
78   config_data: (volatile u_char *) 0x80800000,
79   last_dev_p: NULL,
80   resources: NULL,
81   io: {NULL, 0xfff, 0},
82   mem: {NULL, 0xfffff, 0}
83};
84
85#define pci ((struct _pci_private *)(bd->pci_private))
86#define pci_root pci->pci_root
87
88#if !defined(DEBUG)
89#undef PCI_DEBUG
90/*
91  #else
92  #define PCI_DEBUG
93*/
94#endif
95
96#if defined(PCI_DEBUG)
97static void
98print_pci_resources(const char *s) {
99   pci_resource *p;
100   printk("%s", s);
101   for (p=pci->resources; p; p=p->next) {
102/*
103      printk("  %p:%p %06x %08lx %08lx %d\n",
104             p, p->next,
105             (p->dev->devfn<<8)+(p->dev->bus->number<<16)
106             +0x10+p->reg*4,
107             p->base,
108             p->size,
109             p->type);
110*/
111
112      printk("  %p:%p %d:%02x (%04x:%04x) %08lx %08lx %d\n",
113             p, p->next,
114             p->dev->bus->number, PCI_SLOT(p->dev->devfn),
115             p->dev->vendor, p->dev->device,
116             p->base,
117             p->size,
118             p->type);
119
120   }
121}
122
123static void
124print_pci_area(pci_area *p) {
125   for (; p; p=p->next) {
126      printk("    %p:%p %p %08lx %08lx\n",
127             p, p->next, p->bus, p->start, p->end);
128   }
129}
130
131static void
132print_pci_areas(const char *s) {
133   printk("%s  PCI I/O areas:\n",s);
134   print_pci_area(pci->io.head);
135   printk("  PCI memory areas:\n");
136   print_pci_area(pci->mem.head);
137}
138#else
139#define print_pci_areas(x)
140#define print_pci_resources(x)
141#endif
142
143/* Maybe there are some devices who use a size different
144 * from the alignment. For now we assume both are the same.
145 * The blacklist might be used for other weird things in the future too,
146 * since weird non PCI complying devices seem to proliferate these days.
147 */
148
149struct blacklist_entry {
150      u_short vendor, device;
151      u_char reg;
152      u_long actual_size;
153};
154
155#define BLACKLIST(vid, did, breg, actual_size) \
156        {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##vid##_##did, breg, actual_size}
157
158static struct blacklist_entry blacklist[] = {
159   BLACKLIST(S3, TRIO, 0, 0x04000000),
160   {0xffff, 0, 0, 0}
161};
162
163/* This function filters resources and then inserts them into a list of
164 * configurable pci resources.
165 */
166
167#define AREA(r) \
168(((r->type&PCI_BASE_ADDRESS_SPACE)==PCI_BASE_ADDRESS_SPACE_IO) ? PCI_AREA_IO :\
169          ((r->type&PCI_BASE_ADDRESS_MEM_PREFETCH) ? PCI_AREA_PREFETCHABLE :\
170           PCI_AREA_MEMORY))
171
172static int insert_before(pci_resource *e, pci_resource *t) {
173   if (e->dev->bus->number != t->dev->bus->number)
174      return e->dev->bus->number > t->dev->bus->number;
175   if (AREA(e) != AREA(t)) return AREA(e)<AREA(t);
176   return (e->size > t->size);
177}
178
179static void insert_resource(pci_resource *r) {
180   struct blacklist_entry *b;
181   pci_resource *p;
182   if (!r) return;
183
184   /* First fixup in case we have a blacklist entry. Note that this
185    * may temporarily leave a resource in an inconsistent state: with
186    * (base & (size-1)) !=0. This is harmless.
187    */
188   for (b=blacklist; b->vendor!=0xffff; b++) {
189      if ((r->dev->vendor==b->vendor) &&
190          (r->dev->device==b->device) &&
191          (r->reg==b->reg)) {
192         r->size=b->actual_size;
193         break;
194      }
195   }
196
197   /* Motorola NT firmware does not configure pci devices which are not
198    * required for booting, others do. For now:
199    * - allocated devices in the ISA range (64kB I/O, 16Mb memory)
200    *   but non zero base registers are left as is.
201    * - all other registers, whether already allocated or not, are
202    *   reallocated unless they require an inordinate amount of
203    *   resources (>256 Mb for memory >64kB for I/O). These
204    *   devices with too large mapping requirements are simply ignored
205    *   and their bases are set to 0. This should disable the
206    *   corresponding decoders according to the PCI specification.
207    *   Many devices are buggy in this respect, however, but the
208    *   limits have hopefully been set high enough to avoid problems.
209    */
210
211   /*
212   ** This is little ugly below.  It seems that at least on the MCP750,
213   ** the PBC has some default IO space mappings that the bsp #defines
214   ** that read/write to PCI I/O space assume, particuarly the i8259
215   ** manipulation code.  So, if we allow the small IO spaces on PCI bus
216   ** 0 and 1 to be remapped, the registers can shift out from under the
217   ** #defines.  This is particuarly awful, but short of redefining the
218   ** PCI I/O primitives to be functions with base addresses read from
219   ** the hardware, we are stuck with the kludge below.  Note that
220   ** everything is remapped on the CPCI backplane and any downstream
221   ** hardware, its just the builtin stuff we're tiptoeing around.
222   **
223   ** Gregm, 7/16/2003
224   **
225   ** Gregm, changed 11/2003 so IO devices only on bus 0 zero are not
226   ** remapped.  This covers the builtin pc-like io devices- but
227   ** properly maps IO devices on higher busses.
228   */
229   if( r->dev->bus->number == 0 )
230   {
231   if ((r->type==PCI_BASE_ADDRESS_SPACE_IO)
232       ? (r->base && r->base <0x10000)
233       : (r->base && r->base <0x1000000)) {
234
235#ifdef PCI_DEBUG
236         printk("freeing region;  %p:%p %d:%02x (%04x:%04x) %08lx %08lx %d\n",
237                r, r->next,
238                r->dev->bus->number, PCI_SLOT(r->dev->devfn),
239                r->dev->vendor, r->dev->device,
240                r->base,
241                r->size,
242                r->type);
243#endif
244      sfree(r);
245      return;
246   }
247   }
248
249
250   /* 2004/11/30, PR 729 fix is removing the r->size=0 and r->base=0
251    * assignement which makes too-large regions conflict with onboard
252    * hardware, replacing it with sfree which deletes the memory region
253    * from the setup code, leaving it disabled. */
254   if ((r->type==PCI_BASE_ADDRESS_SPACE_IO)
255       ? (r->size > 0x10000)
256       : (r->size > 0x18000000)) {
257      sfree(r);
258      return;
259   }
260
261   /* Now insert into the list sorting by
262    * 1) decreasing bus number
263    * 2) space: prefetchable memory, non-prefetchable and finally I/O
264    * 3) decreasing size
265    */
266   if (!pci->resources || insert_before(r, pci->resources)) {
267      r->next = pci->resources;
268      pci->resources=r;
269   } else {
270      for (p=pci->resources; p->next; p=p->next) {
271         if (insert_before(r, p->next)) break;
272      }
273      r->next=p->next;
274      p->next=r;
275   }
276}
277
278/* This version only works for bus 0. I don't have any P2P bridges to test
279 * a more sophisticated version which has therefore not been implemented.
280 * Prefetchable memory is not yet handled correctly either.
281 * And several levels of PCI bridges much less even since there must be
282 * allocated together to be able to setup correctly the top bridge.
283 */
284
285static u_long find_range(u_char bus, u_char type,
286                         pci_resource **first,
287                         pci_resource **past, u_int *flags) {
288   pci_resource *p;
289   u_long total=0;
290   u_int fl=0;
291
292   for (p=pci->resources; p; p=p->next)
293   {
294      if ((p->dev->bus->number == bus) &&
295          AREA(p)==type) break;
296   }
297
298   *first = p;
299
300   for (; p; p=p->next)
301   {
302      if ((p->dev->bus->number != bus) ||
303          AREA(p)!=type || p->size == 0) break;
304      total = total+p->size;
305      fl |= 1<<p->type;
306   }
307
308   *past = p;
309   /* This will be used later to tell whether there are any 32 bit
310    * devices in an area which could be mapped higher than 4Gb
311    * on 64 bits architectures
312    */
313   *flags = fl;
314   return total;
315}
316
317static inline void init_free_area(pci_area_head *h, u_long start,
318                                  u_long end, u_int mask, int high) {
319   pci_area *p;
320   p = salloc(sizeof(pci_area));
321   if (!p) return;
322   h->head = p;
323   p->next = NULL;
324   p->start = (start+mask)&~mask;
325   p->end = (end-mask)|mask;
326   p->bus = NULL;
327   h->mask = mask;
328   h->high = high;
329}
330
331static void insert_area(pci_area_head *h, pci_area *p) {
332   pci_area *q = h->head;
333   if (!p) return;
334   if (q && (q->start< p->start)) {
335      for(;q->next && q->next->start<p->start; q = q->next);
336      if ((q->end >= p->start) ||
337          (q->next && p->end>=q->next->start)) {
338         sfree(p);
339         printk("Overlapping pci areas!\n");
340         return;
341      }
342      p->next = q->next;
343      q->next = p;
344   } else { /* Insert at head */
345      if (q && (p->end >= q->start)) {
346         sfree(p);
347         printk("Overlapping pci areas!\n");
348         return;
349      }
350      p->next = q;
351      h->head = p;
352   }
353}
354
355static
356void remove_area(pci_area_head *h, pci_area *p)
357{
358   pci_area *q = h->head;
359
360   if (!p || !q) return;
361   if (q==p)
362   {
363      h->head = q->next;
364      return;
365   }
366   for(;q && q->next!=p; q=q->next);
367   if (q) q->next=p->next;
368}
369
370static pci_area * alloc_area(pci_area_head *h, struct pci_bus *bus,
371                             u_long required, u_long mask, u_int flags) {
372   pci_area *p;
373   pci_area *from, *split, *new;
374
375   required = (required+h->mask) & ~h->mask;
376   for (p=h->head, from=NULL; p; p=p->next)
377   {
378      u_long l1 = ((p->start+required+mask)&~mask)-1;
379      u_long l2 = ((p->start+mask)&~mask)+required-1;
380      /* Allocated areas point to the bus to which they pertain */
381      if (p->bus) continue;
382      if ((p->end)>=l1 || (p->end)>=l2) from=p;
383      if (from && !h->high) break;
384   }
385   if (!from) return NULL;
386
387   split = salloc(sizeof(pci_area));
388   new = salloc(sizeof(pci_area));
389   /* If allocation of new succeeds then allocation of split has
390    * also been successful (given the current mm algorithms) !
391    */
392   if (!new) {
393      sfree(split);
394      return NULL;
395   }
396   new->bus = bus;
397   new->flags = flags;
398   /* Now allocate pci_space taking alignment into account ! */
399   if (h->high)
400   {
401      u_long l1 = ((from->end+1)&~mask)-required;
402      u_long l2 = (from->end+1-required)&~mask;
403      new->start = (l1>l2) ? l1 : l2;
404      split->end = from->end;
405      from->end = new->start-1;
406      split->start = new->start+required;
407      new->end = new->start+required-1;
408   }
409   else
410   {
411      u_long l1 = ((from->start+mask)&~mask)+required-1;
412      u_long l2 = ((from->start+required+mask)&~mask)-1;
413      new->end = (l1<l2) ? l1 : l2;
414      split->start = from->start;
415      from->start = new->end+1;
416      new->start = new->end+1-required;
417      split->end = new->start-1;
418   }
419
420   if (from->end+1 == from->start) remove_area(h, from);
421   if (split->end+1 != split->start)
422   {
423      split->bus = NULL;
424      insert_area(h, split);
425   }
426   else
427   {
428      sfree(split);
429   }
430   insert_area(h, new);
431   print_pci_areas("alloc_area called:\n");
432   return new;
433}
434
435static inline
436void alloc_space(pci_area *p, pci_resource *r)
437{
438   if (p->start & (r->size-1)) {
439      r->base = p->end+1-r->size;
440      p->end -= r->size;
441   } else {
442      r->base = p->start;
443      p->start += r->size;
444   }
445}
446
447static void reconfigure_bus_space(u_char bus, u_char type, pci_area_head *h)
448{
449   pci_resource *first, *past, *r;
450   pci_area *area, tmp;
451   u_int flags;
452   u_int required = find_range(bus, type, &first, &past, &flags);
453
454   if (required==0) return;
455
456   area = alloc_area(h, first->dev->bus, required, first->size-1, flags);
457
458   if (!area) return;
459
460   tmp = *area;
461   for (r=first; r!=past; r=r->next)
462   {
463      alloc_space(&tmp, r);
464   }
465}
466
467#define BUS0_IO_START           0x10000
468#define BUS0_IO_END             0x1ffff
469#define BUS0_MEM_START          0x1000000
470#define BUS0_MEM_END            0x3f00000
471
472#define BUSREST_IO_START        0x20000
473#define BUSREST_IO_END          0x7ffff
474#define BUSREST_MEM_START       0x4000000
475#define BUSREST_MEM_END        0x10000000
476
477static void reconfigure_pci(void) {
478   pci_resource *r;
479   struct pci_dev *dev;
480
481   u_long bus0_mem_start = BUS0_MEM_START;
482   u_long bus0_mem_end   = BUS0_MEM_END;
483
484   if ( residual_fw_is_qemu( bd->residual ) ) {
485     bus0_mem_start += PREP_ISA_MEM_BASE;
486     bus0_mem_end   += PREP_ISA_MEM_BASE;
487   }
488
489   /* FIXME: for now memory is relocated from low, it's better
490    * to start from higher addresses.
491    */
492   /*
493   init_free_area(&pci->io, 0x10000, 0x7fffff, 0xfff, 0);
494   init_free_area(&pci->mem, 0x1000000, 0x3cffffff, 0xfffff, 0);
495   */
496
497   init_free_area(&pci->io, BUS0_IO_START, BUS0_IO_END, 0xfff, 0);
498   init_free_area(&pci->mem, bus0_mem_start, bus0_mem_end, 0xfffff, 0);
499
500   /* First reconfigure the I/O space, this will be more
501    * complex when there is more than 1 bus. And 64 bits
502    * devices are another kind of problems.
503    */
504   reconfigure_bus_space(0, PCI_AREA_IO, &pci->io);
505   reconfigure_bus_space(0, PCI_AREA_MEMORY, &pci->mem);
506   reconfigure_bus_space(0, PCI_AREA_PREFETCHABLE, &pci->mem);
507
508   /* Now we have to touch the configuration space of all
509    * the devices to remap them better than they are right now.
510    * This is done in 3 steps:
511    * 1) first disable I/O and memory response of all devices
512    * 2) modify the base registers
513    * 3) restore the original PCI_COMMAND register.
514    */
515   for (r=pci->resources; r; r= r->next) {
516      if (!r->dev->sysdata) {
517         r->dev->sysdata=r;
518         pci_bootloader_read_config_word(r->dev, PCI_COMMAND, &r->cmd);
519         pci_bootloader_write_config_word(r->dev, PCI_COMMAND,
520                               r->cmd & ~(PCI_COMMAND_IO|
521                                          PCI_COMMAND_MEMORY));
522      }
523   }
524
525   for (r=pci->resources; r; r= r->next) {
526      pci_bootloader_write_config_dword(r->dev,
527                             PCI_BASE_ADDRESS_0+(r->reg<<2),
528                             r->base);
529
530      if ( residual_fw_is_qemu( bd->residual ) && r->dev->sysdata ) {
531        if ( PCI_BASE_ADDRESS_SPACE_IO == (r->type &  PCI_BASE_ADDRESS_SPACE) )
532                        ((pci_resource*)r->dev->sysdata)->cmd |= PCI_COMMAND_IO;
533                else
534                        ((pci_resource*)r->dev->sysdata)->cmd |= PCI_COMMAND_MEMORY;
535      }
536
537      if ((r->type&
538           (PCI_BASE_ADDRESS_SPACE|
539            PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
540          (PCI_BASE_ADDRESS_SPACE_MEMORY|
541           PCI_BASE_ADDRESS_MEM_TYPE_64)) {
542         pci_bootloader_write_config_dword(r->dev,
543                                PCI_BASE_ADDRESS_1+(r->reg<<2),
544                                0);
545      }
546   }
547   for (dev=bd->pci_devices; dev; dev= dev->next) {
548      if (dev->sysdata) {
549         pci_bootloader_write_config_word(dev, PCI_COMMAND,
550                               ((pci_resource *)dev->sysdata)
551                               ->cmd);
552         dev->sysdata=NULL;
553      }
554   }
555}
556
557static int
558indirect_pci_read_config_byte(unsigned char bus, unsigned char dev_fn,
559                              unsigned char offset, uint8_t *val) {
560   out_be32(pci->config_addr,
561            0x80|(bus<<8)|(dev_fn<<16)|((offset&~3)<<24));
562   *val=in_8(pci->config_data + (offset&3));
563   return PCIBIOS_SUCCESSFUL;
564}
565
566static int
567indirect_pci_read_config_word(unsigned char bus, unsigned char dev_fn,
568                              unsigned char offset, uint16_t *val) {
569   *val = 0xffff;
570   if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
571   out_be32(pci->config_addr,
572            0x80|(bus<<8)|(dev_fn<<16)|((offset&~3)<<24));
573   *val=in_le16((volatile uint16_t *)(pci->config_data + (offset&3)));
574   return PCIBIOS_SUCCESSFUL;
575}
576
577static int
578indirect_pci_read_config_dword(unsigned char bus, unsigned char dev_fn,
579                               unsigned char offset, uint32_t *val) {
580   *val = 0xffffffff;
581   if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
582   out_be32(pci->config_addr,
583            0x80|(bus<<8)|(dev_fn<<16)|(offset<<24));
584   *val=in_le32((volatile uint32_t *)pci->config_data);
585   return PCIBIOS_SUCCESSFUL;
586}
587
588static int
589indirect_pci_write_config_byte(unsigned char bus, unsigned char dev_fn,
590                               unsigned char offset, uint8_t val) {
591   out_be32(pci->config_addr,
592            0x80|(bus<<8)|(dev_fn<<16)|((offset&~3)<<24));
593   out_8(pci->config_data + (offset&3), val);
594   return PCIBIOS_SUCCESSFUL;
595}
596
597static int
598indirect_pci_write_config_word(unsigned char bus, unsigned char dev_fn,
599                               unsigned char offset, uint16_t val) {
600   if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
601   out_be32(pci->config_addr,
602            0x80|(bus<<8)|(dev_fn<<16)|((offset&~3)<<24));
603   out_le16((volatile uint16_t *)(pci->config_data + (offset&3)), val);
604   return PCIBIOS_SUCCESSFUL;
605}
606
607static int
608indirect_pci_write_config_dword(unsigned char bus, unsigned char dev_fn,
609                                unsigned char offset, uint32_t val) {
610   if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
611   out_be32(pci->config_addr,
612            0x80|(bus<<8)|(dev_fn<<16)|(offset<<24));
613   out_le32((volatile uint32_t *)pci->config_data, val);
614   return PCIBIOS_SUCCESSFUL;
615}
616
617static const struct pci_bootloader_config_access_functions indirect_functions = {
618   indirect_pci_read_config_byte,
619   indirect_pci_read_config_word,
620   indirect_pci_read_config_dword,
621   indirect_pci_write_config_byte,
622   indirect_pci_write_config_word,
623   indirect_pci_write_config_dword
624};
625
626static int
627direct_pci_read_config_byte(unsigned char bus, unsigned char dev_fn,
628                            unsigned char offset, uint8_t *val) {
629   if (bus != 0 || (1<<PCI_SLOT(dev_fn) & 0xff8007fe)) {
630      *val=0xff;
631      return PCIBIOS_DEVICE_NOT_FOUND;
632   }
633   *val=in_8(pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1)
634             + (PCI_FUNC(dev_fn)<<8) + offset);
635   return PCIBIOS_SUCCESSFUL;
636}
637
638static int
639direct_pci_read_config_word(unsigned char bus, unsigned char dev_fn,
640                            unsigned char offset, uint16_t *val) {
641   *val = 0xffff;
642   if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
643   if (bus != 0 || (1<<PCI_SLOT(dev_fn) & 0xff8007fe)) {
644      return PCIBIOS_DEVICE_NOT_FOUND;
645   }
646   *val=in_le16((volatile uint16_t *)
647                (pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1)
648                 + (PCI_FUNC(dev_fn)<<8) + offset));
649   return PCIBIOS_SUCCESSFUL;
650}
651
652static int
653direct_pci_read_config_dword(unsigned char bus, unsigned char dev_fn,
654                             unsigned char offset, uint32_t *val) {
655   *val = 0xffffffff;
656   if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
657   if (bus != 0 || (1<<PCI_SLOT(dev_fn) & 0xff8007fe)) {
658      return PCIBIOS_DEVICE_NOT_FOUND;
659   }
660   *val=in_le32((volatile uint32_t *)
661                (pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1)
662                 + (PCI_FUNC(dev_fn)<<8) + offset));
663   return PCIBIOS_SUCCESSFUL;
664}
665
666static int
667direct_pci_write_config_byte(unsigned char bus, unsigned char dev_fn,
668                             unsigned char offset, uint8_t val) {
669   if (bus != 0 || (1<<PCI_SLOT(dev_fn) & 0xff8007fe)) {
670      return PCIBIOS_DEVICE_NOT_FOUND;
671   }
672   out_8(pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1)
673         + (PCI_FUNC(dev_fn)<<8) + offset,
674         val);
675   return PCIBIOS_SUCCESSFUL;
676}
677
678static int
679direct_pci_write_config_word(unsigned char bus, unsigned char dev_fn,
680                             unsigned char offset, uint16_t val) {
681   if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER;
682   if (bus != 0 || (1<<PCI_SLOT(dev_fn) & 0xff8007fe)) {
683      return PCIBIOS_DEVICE_NOT_FOUND;
684   }
685   out_le16((volatile uint16_t *)
686            (pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1)
687             + (PCI_FUNC(dev_fn)<<8) + offset),
688            val);
689   return PCIBIOS_SUCCESSFUL;
690}
691
692static int
693direct_pci_write_config_dword(unsigned char bus, unsigned char dev_fn,
694                              unsigned char offset, uint32_t val) {
695   if (offset&3) return PCIBIOS_BAD_REGISTER_NUMBER;
696   if (bus != 0 || (1<<PCI_SLOT(dev_fn) & 0xff8007fe)) {
697      return PCIBIOS_DEVICE_NOT_FOUND;
698   }
699   out_le32((volatile uint32_t *)
700            (pci->config_data + ((1<<PCI_SLOT(dev_fn))&~1)
701             + (PCI_FUNC(dev_fn)<<8) + offset),
702            val);
703   return PCIBIOS_SUCCESSFUL;
704}
705
706static const struct pci_bootloader_config_access_functions direct_functions = {
707   direct_pci_read_config_byte,
708   direct_pci_read_config_word,
709   direct_pci_read_config_dword,
710   direct_pci_write_config_byte,
711   direct_pci_write_config_word,
712   direct_pci_write_config_dword
713};
714
715static void pci_read_bases(struct pci_dev *dev, unsigned int howmany)
716{
717   unsigned int reg, nextreg;
718
719#define REG (PCI_BASE_ADDRESS_0 + (reg<<2))
720
721   u_short cmd;
722   uint32_t l, ml;
723   pci_bootloader_read_config_word(dev, PCI_COMMAND, &cmd);
724
725   for(reg=0; reg<howmany; reg=nextreg)
726   {
727      pci_resource *r;
728
729      nextreg=reg+1;
730      pci_bootloader_read_config_dword(dev, REG, &l);
731#if 0
732      if (l == 0xffffffff /*AJF || !l*/) continue;
733#endif
734      /* Note that disabling the memory response of a host bridge
735       * would lose data if a DMA transfer were in progress. In a
736       * bootloader we don't care however. Also we can't print any
737       * message for a while since we might just disable the console.
738       */
739      pci_bootloader_write_config_word(dev, PCI_COMMAND, cmd &
740                            ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
741      pci_bootloader_write_config_dword(dev, REG, ~0);
742      pci_bootloader_read_config_dword(dev, REG, &ml);
743      pci_bootloader_write_config_dword(dev, REG, l);
744
745      /* Reenable the device now that we've played with
746       * base registers.
747       */
748      pci_bootloader_write_config_word(dev, PCI_COMMAND, cmd);
749
750      /* seems to be an unused entry skip it */
751      if ( ml == 0 || ml == 0xffffffff ) continue;
752
753      if ((l &
754           (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK))
755          == (PCI_BASE_ADDRESS_MEM_TYPE_64
756              |PCI_BASE_ADDRESS_SPACE_MEMORY)) {
757         nextreg=reg+2;
758      }
759      dev->base_address[reg] = l;
760      r = salloc(sizeof(pci_resource));
761      if (!r) {
762         printk("Error allocating pci_resource struct.\n");
763         continue;
764      }
765      r->dev = dev;
766      r->reg = reg;
767      if ((l&PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
768         r->type = l&~PCI_BASE_ADDRESS_IO_MASK;
769         r->base = l&PCI_BASE_ADDRESS_IO_MASK;
770         /* r->size = ~(ml&PCI_BASE_ADDRESS_IO_MASK)+1; */
771      } else {
772         r->type = l&~PCI_BASE_ADDRESS_MEM_MASK;
773         r->base = l&PCI_BASE_ADDRESS_MEM_MASK;
774         /* r->size = ~(ml&PCI_BASE_ADDRESS_MEM_MASK)+1; */
775      }
776
777      /* find the first bit set to one after the base
778         address type bits to find length of region */
779      {
780         unsigned int c= 16 , val= 0;
781         while( !(val= ml & c) ) c <<= 1;
782         r->size = val;
783      }
784
785#ifdef PCI_DEBUG
786      printk("   readbase bus %d, (%04x:%04x), base %08x, size %08x, type %d\n",
787             r->dev->bus->number,
788             r->dev->vendor,
789             r->dev->device,
790             r->base,
791             r->size,
792             r->type );
793#endif
794
795      /* Check for the blacklisted entries */
796      insert_resource(r);
797   }
798}
799
800static u_int pci_scan_bus(struct pci_bus *bus)
801{
802   unsigned int devfn, max;
803   uint32_t class;
804   uint32_t l;
805   unsigned char irq, hdr_type, is_multi = 0;
806   struct pci_dev *dev, **bus_last;
807   struct pci_bus *child;
808
809#if 0
810   printk("scanning pci bus %d\n", bus->number );
811#endif
812
813   bus_last = &bus->devices;
814   max = bus->secondary;
815   for (devfn = 0; devfn < 0xff; ++devfn) {
816      if (PCI_FUNC(devfn) && !is_multi) {
817         /* not a multi-function device */
818         continue;
819      }
820      if (pcibios_read_config_byte(bus->number, devfn, PCI_HEADER_TYPE, &hdr_type))
821         continue;
822      if (!PCI_FUNC(devfn))
823         is_multi = hdr_type & 0x80;
824
825      if (pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID, &l) ||
826          /* some broken boards return 0 if a slot is empty: */
827          l == 0xffffffff || l == 0x00000000 || l == 0x0000ffff || l == 0xffff0000) {
828         is_multi = 0;
829         continue;
830      }
831
832      dev = salloc(sizeof(*dev));
833      dev->bus = bus;
834      dev->devfn  = devfn;
835      dev->vendor = l & 0xffff;
836      dev->device = (l >> 16) & 0xffff;
837
838      pcibios_read_config_dword(bus->number, devfn,
839                                PCI_CLASS_REVISION, &class);
840      class >>= 8;                                  /* upper 3 bytes */
841      dev->class = class;
842      class >>= 8;
843      dev->hdr_type = hdr_type;
844
845      switch (hdr_type & 0x7f) {                    /* header type */
846         case PCI_HEADER_TYPE_NORMAL:               /* standard header */
847            if (class == PCI_CLASS_BRIDGE_PCI)
848               goto bad;
849            /*
850             * If the card generates interrupts, read IRQ number
851             * (some architectures change it during pcibios_fixup())
852             */
853            pcibios_read_config_byte(bus->number, dev->devfn, PCI_INTERRUPT_PIN, &irq);
854            if (irq)
855               pcibios_read_config_byte(bus->number, dev->devfn, PCI_INTERRUPT_LINE, &irq);
856            dev->irq = irq;
857            /*
858             * read base address registers, again pcibios_fixup() can
859             * tweak these
860             */
861            pci_read_bases(dev, 6);
862            pcibios_read_config_dword(bus->number, devfn, PCI_ROM_ADDRESS, &l);
863            dev->rom_address = (l == 0xffffffff) ? 0 : l;
864            break;
865         case PCI_HEADER_TYPE_BRIDGE:               /* bridge header */
866            if (class != PCI_CLASS_BRIDGE_PCI)
867               goto bad;
868            pci_read_bases(dev, 2);
869            pcibios_read_config_dword(bus->number, devfn, PCI_ROM_ADDRESS1, &l);
870            dev->rom_address = (l == 0xffffffff) ? 0 : l;
871            break;
872         case PCI_HEADER_TYPE_CARDBUS:              /* CardBus bridge header */
873            if (class != PCI_CLASS_BRIDGE_CARDBUS)
874               goto bad;
875            pci_read_bases(dev, 1);
876            break;
877
878         default:                                   /* unknown header */
879        bad:
880            printk("PCI device with unknown header type %d ignored.\n",
881                   hdr_type&0x7f);
882            continue;
883      }
884
885      /*
886       * Put it into the global PCI device chain. It's used to
887       * find devices once everything is set up.
888       */
889      *pci->last_dev_p = dev;
890      pci->last_dev_p = &dev->next;
891
892      /*
893       * Now insert it into the list of devices held
894       * by the parent bus.
895       */
896      *bus_last = dev;
897      bus_last = &dev->sibling;
898
899   }
900
901   /*
902    * After performing arch-dependent fixup of the bus, look behind
903    * all PCI-to-PCI bridges on this bus.
904    */
905   for(dev=bus->devices; dev; dev=dev->sibling)
906      /*
907       * If it's a bridge, scan the bus behind it.
908       */
909      if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
910         uint32_t buses;
911         unsigned int devfn = dev->devfn;
912         unsigned short cr;
913
914         /*
915          * Insert it into the tree of buses.
916          */
917         child = salloc(sizeof(*child));
918         child->next = bus->children;
919         bus->children = child;
920         child->self = dev;
921         child->parent = bus;
922
923         /*
924          * Set up the primary, secondary and subordinate
925          * bus numbers.
926          */
927         child->number = child->secondary = ++max;
928         child->primary = bus->secondary;
929         child->subordinate = 0xff;
930         /*
931          * Clear all status bits and turn off memory,
932          * I/O and master enables.
933          */
934         pcibios_read_config_word(bus->number, devfn, PCI_COMMAND, &cr);
935         pcibios_write_config_word(bus->number, devfn, PCI_COMMAND, 0x0000);
936         pcibios_write_config_word(bus->number, devfn, PCI_STATUS, 0xffff);
937         /*
938          * Read the existing primary/secondary/subordinate bus
939          * number configuration to determine if the PCI bridge
940          * has already been configured by the system.  If so,
941          * do not modify the configuration, merely note it.
942          */
943         pcibios_read_config_dword(bus->number, devfn, PCI_PRIMARY_BUS, &buses);
944         if ((buses & 0xFFFFFF) != 0)
945         {
946            unsigned int cmax;
947
948            child->primary = buses & 0xFF;
949            child->secondary = (buses >> 8) & 0xFF;
950            child->subordinate = (buses >> 16) & 0xFF;
951            child->number = child->secondary;
952            cmax = pci_scan_bus(child);
953            if (cmax > max) max = cmax;
954         }
955         else
956         {
957            /*
958             * Configure the bus numbers for this bridge:
959             */
960            buses &= 0xff000000;
961            buses |=
962               (((unsigned int)(child->primary)     <<  0) |
963                ((unsigned int)(child->secondary)   <<  8) |
964                ((unsigned int)(child->subordinate) << 16));
965            pcibios_write_config_dword(bus->number, devfn, PCI_PRIMARY_BUS, buses);
966            /*
967             * Now we can scan all subordinate buses:
968             */
969            max = pci_scan_bus(child);
970            /*
971             * Set the subordinate bus number to its real
972             * value:
973             */
974            child->subordinate = max;
975            buses = (buses & 0xff00ffff)
976               | ((unsigned int)(child->subordinate) << 16);
977            pcibios_write_config_dword(bus->number, devfn, PCI_PRIMARY_BUS, buses);
978         }
979         pcibios_write_config_word(bus->number, devfn, PCI_COMMAND, cr );
980      }
981
982   /*
983    * We've scanned the bus and so we know all about what's on
984    * the other side of any bridges that may be on this bus plus
985    * any devices.
986    *
987    * Return how far we've got finding sub-buses.
988    */
989   return max;
990}
991
992#if 0
993
994void
995pci_fixup(void)
996{
997   struct pci_dev *p;
998   struct pci_bus *bus;
999
1000   for (bus = &pci_root; bus; bus=bus->next)
1001   {
1002      for (p=bus->devices; p; p=p->sibling)
1003      {
1004      }
1005   }
1006}
1007
1008static void print_pci_info()
1009{
1010   pci_resource *r;
1011   struct pci_bus *pb = &pci_root;
1012
1013   printk("\n");
1014   printk("PCI busses:\n");
1015
1016   for(pb= &pci_root; pb; pb=pb->children )
1017   {
1018      printk("   number %d, primary %d, secondary %d, subordinate %d\n",
1019             pb->number,
1020             pb->primary,
1021             pb->secondary,
1022             pb->subordinate );
1023      printk("   bridge; vendor %04x, device %04x\n",
1024             pb->self->vendor,
1025             pb->self->device );
1026
1027      {
1028         struct pci_dev *pd;
1029
1030         for(pd= pb->devices; pd; pd=pd->sibling )
1031         {
1032            printk("       vendor %04x, device %04x, irq %d\n",
1033                   pd->vendor,
1034                   pd->device,
1035                   pd->irq );
1036
1037         }
1038         printk("\n");
1039      }
1040
1041   }
1042   printk("\n");
1043
1044   printk("PCI resources:\n");
1045   for (r=pci->resources; r; r= r->next)
1046   {
1047      printk("   bus %d, vendor %04x, device %04x, base %08x, size %08x, type %d\n",
1048             r->dev->bus->number,
1049             r->dev->vendor,
1050             r->dev->device,
1051             r->base,
1052             r->size,
1053             r->type );
1054   }
1055   printk("\n");
1056
1057   return;
1058}
1059
1060#endif
1061
1062static struct _addr_start
1063{
1064      uint32_t   start_pcimem;
1065      uint32_t   start_pciio;
1066      uint32_t   start_prefetch;
1067} astart;
1068
1069static pci_resource *enum_device_resources( struct pci_dev *pdev, int i )
1070{
1071   pci_resource *r;
1072
1073   for(r= pci->resources; r; r= r->next )
1074   {
1075      if( r->dev == pdev )
1076      {
1077         if( i-- == 0 ) break;
1078      }
1079   }
1080   return r;
1081}
1082
1083static void recursive_bus_reconfigure( struct pci_bus *pbus )
1084{
1085   struct pci_dev       *pdev;
1086   struct pci_bus       *childbus;
1087   int  isroot = 0;
1088
1089   if( !pbus )
1090   {
1091      /* start with the root bus */
1092      astart.start_pcimem   = BUSREST_MEM_START;
1093      astart.start_pciio    = BUSREST_IO_START;
1094      astart.start_prefetch = ((BUSREST_MEM_END >> 16) << 16);
1095
1096      pbus = &pci_root;
1097      isroot = -1;
1098   }
1099
1100#define WRITE_BRIDGE_IO
1101#define WRITE_BRIDGE_MEM
1102#define WRITE_BRIDGE_PF
1103#define WRITE_BRIDGE_ENABLE
1104
1105/*
1106** Run thru the p2p bridges on this bus and recurse into subordinate busses
1107*/
1108   for( childbus= pbus->children; childbus; childbus= childbus->next )
1109   {
1110      pdev= childbus->self;
1111
1112      pcibios_write_config_byte(pdev->bus->number, pdev->devfn, PCI_LATENCY_TIMER,     0x80 );
1113      pcibios_write_config_byte(pdev->bus->number, pdev->devfn, PCI_SEC_LATENCY_TIMER, 0x80 );
1114
1115      {
1116         struct _addr_start   addrhold;
1117         uint8_t              base8, limit8;
1118         uint16_t             base16, limit16, ubase16, ulimit16;
1119
1120         /* save the base address values */
1121         memcpy( &addrhold, &astart, sizeof(struct _addr_start));
1122
1123         recursive_bus_reconfigure( childbus );
1124
1125#ifdef PCI_DEBUG
1126         printk("pci: configuring bus %d bridge (%04x:%04x), bus %d : (%d-%d)\n",
1127                pdev->bus->number,
1128                pdev->vendor,
1129                pdev->device,
1130                childbus->primary,
1131                childbus->secondary,
1132                childbus->subordinate );
1133#endif
1134
1135         /*
1136          * use the current values & the saved ones to figure out
1137          * the address spaces for the bridge
1138          */
1139
1140         if( addrhold.start_pciio == astart.start_pciio )
1141         {
1142            base8 = limit8 = 0xff;
1143            ubase16 = ulimit16 = 0xffff;
1144         }
1145         else
1146         {
1147            base8    = (uint8_t) ((addrhold.start_pciio >> 8) & 0xf0);
1148            ubase16  = (uint16_t)(addrhold.start_pciio >> 16);
1149            limit8   = (uint8_t) ((astart.start_pciio >> 8 ) & 0xf0);
1150            ulimit16 = (uint16_t)(astart.start_pciio >> 16);
1151            astart.start_pciio += 0x1000;
1152         }
1153
1154#ifdef PCI_DEBUG
1155         printk("pci:     io base %08x limit %08x\n", (base8<<8)+(ubase16<<16), (limit8<<8)+(ulimit16<<16));
1156#endif
1157#ifdef WRITE_BRIDGE_IO
1158         pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_IO_BASE_UPPER16, ubase16 );
1159         pcibios_write_config_byte(pdev->bus->number, pdev->devfn, PCI_IO_BASE, base8 );
1160
1161         pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_IO_LIMIT_UPPER16, ulimit16 );
1162         pcibios_write_config_byte(pdev->bus->number, pdev->devfn, PCI_IO_LIMIT, limit8 );
1163#endif
1164
1165         if( addrhold.start_pcimem == astart.start_pcimem )
1166         {
1167            limit16 = 0;
1168            base16 = 0xffff;
1169         }
1170         else
1171         {
1172            limit16= (uint16_t)((astart.start_pcimem >> 16) & 0xfff0);
1173            base16 = (uint16_t)((addrhold.start_pcimem >> 16) & 0xfff0);
1174            astart.start_pcimem += 0x100000;
1175         }
1176#ifdef PCI_DEBUG
1177         printk("pci:      memory %04x, limit %04x\n", base16, limit16);
1178#endif
1179#ifdef WRITE_BRIDGE_MEM
1180         pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_MEMORY_BASE, base16 );
1181         pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_MEMORY_LIMIT, limit16 );
1182#endif
1183
1184
1185         if( astart.start_prefetch == addrhold.start_prefetch )
1186         {
1187            limit16 = 0;
1188            base16 = 0xffff;
1189         }
1190         else
1191         {
1192            limit16= (uint16_t)((addrhold.start_prefetch >> 16) & 0xfff0);
1193            base16 = (uint16_t)((astart.start_prefetch >> 16) & 0xfff0);
1194            astart.start_prefetch -= 0x100000;
1195         }
1196#ifdef PCI_DEBUG
1197         printk("pci:   pf memory %04x, limit %04x\n", base16, limit16);
1198#endif
1199#ifdef WRITE_BRIDGE_PF
1200         pcibios_write_config_dword(pdev->bus->number, pdev->devfn, PCI_PREF_BASE_UPPER32, 0);
1201         pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_PREF_MEMORY_BASE, base16 );
1202         pcibios_write_config_dword(pdev->bus->number, pdev->devfn, PCI_PREF_LIMIT_UPPER32, 0);
1203         pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_PREF_MEMORY_LIMIT, limit16 );
1204#endif
1205
1206#ifdef WRITE_BRIDGE_ENABLE
1207         pcibios_write_config_word(pdev->bus->number,
1208                                   pdev->devfn,
1209                                   PCI_BRIDGE_CONTROL,
1210                                   (uint16_t)( 0 ));
1211
1212         pcibios_write_config_word(pdev->bus->number,
1213                                   pdev->devfn,
1214                                   PCI_COMMAND,
1215                                   (uint16_t)( PCI_COMMAND_IO |
1216                                                 PCI_COMMAND_MEMORY |
1217                                                 PCI_COMMAND_MASTER ));
1218#endif
1219      }
1220   }
1221
1222   if( !isroot )
1223   {
1224#ifdef PCI_DEBUG
1225      printk("pci: Configuring devices on bus %d\n", pbus->number);
1226#endif
1227      /*
1228      ** Run thru this bus and set up addresses for all the non-bridge devices
1229      */
1230      for( pdev = pbus->devices; pdev; pdev= pdev->sibling )
1231      {
1232         if( (pdev->class >> 8) != PCI_CLASS_BRIDGE_PCI )
1233         {
1234            pci_resource *r;
1235            int i = 0;
1236            unsigned alloc;
1237
1238            /* enumerate all the resources defined by this device & reserve space
1239            ** for each of their defined regions.
1240            */
1241
1242#ifdef PCI_DEBUG
1243            printk("pci: configuring; vendor %04x, device %04x\n", pdev->vendor, pdev->device );
1244#endif
1245
1246            while( (r= enum_device_resources( pdev, i++ )) )
1247            {
1248               /*
1249               ** Force all memory spaces to be non-prefetchable because
1250               ** on the pci bus, byte-wise reads against prefetchable
1251               ** memory are applied as 32 bit reads, which is a pain
1252               ** when you're trying to talk to hardware.  This is a
1253               ** little sub-optimal because the algorithm doesn't sort
1254               ** the address regions to pack them in, OTOH, perhaps its
1255               ** not so bad because the inefficient packing will help
1256               ** avoid buffer overflow/underflow problems.
1257               */
1258#if 0
1259               if( (r->type & PCI_BASE_ADDRESS_MEM_PREFETCH) )
1260               {
1261                  /* prefetchable space */
1262
1263                  /* shift base pointer down to an integer multiple of the size of the desired region */
1264                  astart.start_prefetch -= (alloc= ((r->size / PAGE_SIZE) + 1) * PAGE_SIZE);
1265                  /* shift base pointer down to an integer multiple of the size of the desired region */
1266                  astart.start_prefetch = (astart.start_prefetch / r->size) * r->size;
1267
1268                  r->base = astart.start_prefetch;
1269#ifdef PCI_DEBUG
1270                  printk("pci:       pf %08X, size %08X, alloc %08X\n", r->base, r->size, alloc );
1271#endif
1272               }
1273#endif
1274               if( r->type & PCI_BASE_ADDRESS_SPACE_IO )
1275               {
1276                  /* io space */
1277
1278                  /* shift base pointer up to an integer multiple of the size of the desired region */
1279                  if( astart.start_pciio % r->size )
1280                     astart.start_pciio = (((astart.start_pciio / r->size) + 1) * r->size);
1281
1282                  r->base = astart.start_pciio;
1283                  astart.start_pciio += (alloc= ((r->size / PAGE_SIZE) + 1) * PAGE_SIZE);
1284#ifdef PCI_DEBUG
1285                  printk("pci:      io  %08X, size %08X, alloc %08X\n", r->base, r->size, alloc );
1286#endif
1287               }
1288               else
1289               {
1290                  /* memory space */
1291
1292                  /* shift base pointer up to an integer multiple of the size of the desired region */
1293                  if( astart.start_pcimem % r->size )
1294                     astart.start_pcimem = (((astart.start_pcimem / r->size) + 1) * r->size);
1295
1296                  r->base = astart.start_pcimem;
1297                  astart.start_pcimem += (alloc= ((r->size / PAGE_SIZE) + 1) * PAGE_SIZE);
1298#ifdef PCI_DEBUG
1299                  printk("pci:      mem %08X, size %08X, alloc %08X\n", r->base, r->size, alloc );
1300#endif
1301               }
1302            }
1303
1304         }
1305      }
1306   }
1307
1308}
1309
1310void pci_init(void)
1311{
1312   PPC_DEVICE *hostbridge;
1313
1314   if (pci->last_dev_p) {
1315      printk("Two or more calls to pci_init!\n");
1316      return;
1317   }
1318   pci->last_dev_p = &(bd->pci_devices);
1319   hostbridge=residual_find_device(PROCESSORDEVICE, NULL,
1320                                   BridgeController,
1321                                   PCIBridge, -1, 0);
1322   if (hostbridge) {
1323      if (hostbridge->DeviceId.Interface==PCIBridgeIndirect) {
1324         bd->pci_functions=&indirect_functions;
1325         /* Should be extracted from residual data,
1326          * indeed MPC106 in CHRP mode is different,
1327          * but we should not use residual data in
1328          * this case anyway.
1329          */
1330         pci->config_addr = ((volatile void *)
1331                             (ptr_mem_map->io_base+0xcf8));
1332         pci->config_data = ptr_mem_map->io_base+0xcfc;
1333      } else if(hostbridge->DeviceId.Interface==PCIBridgeDirect) {
1334         bd->pci_functions=&direct_functions;
1335         pci->config_data=(u_char *) 0x80800000;
1336      } else {
1337      }
1338   } else {
1339      /* Let us try by experimentation at our own risk! */
1340      uint32_t id0;
1341      bd->pci_functions = &direct_functions;
1342      /* On all direct bridges I know the host bridge itself
1343       * appears as device 0 function 0.
1344       */
1345      pcibios_read_config_dword(0, 0, PCI_VENDOR_ID, &id0);
1346      if (id0==~0U) {
1347         bd->pci_functions = &indirect_functions;
1348         pci->config_addr = ((volatile u_int *)
1349                             (ptr_mem_map->io_base+0xcf8));
1350         pci->config_data = ptr_mem_map->io_base+0xcfc;
1351      }
1352      /* Here we should check that the host bridge is actually
1353       * present, but if it not, we are in such a desperate
1354       * situation, that we probably can't even tell it.
1355       */
1356   }
1357   /* Now build a small database of all found PCI devices */
1358   printk("\nPCI: Probing PCI hardware\n");
1359   pci_root.subordinate=pci_scan_bus(&pci_root);
1360
1361   print_pci_resources("Installed PCI resources:\n");
1362
1363   recursive_bus_reconfigure(NULL);
1364
1365   reconfigure_pci();
1366
1367   print_pci_resources("Allocated PCI resources:\n");
1368
1369#if 0
1370   print_pci_info();
1371#endif
1372}
1373
1374/* eof */
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