1 | /* |
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2 | * head.S -- Bootloader Entry point |
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3 | * |
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4 | * Copyright (C) 1998, 1999 Gabriel Paubert, paubert@iram.es |
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5 | * |
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6 | * Modified to compile in RTEMS development environment |
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7 | * by Eric Valette |
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8 | * |
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9 | * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in found in the file LICENSE in this distribution or at |
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13 | * http://www.OARcorp.com/rtems/license.html. |
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14 | * |
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15 | * $Id$ |
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16 | */ |
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17 | |
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18 | #include <asm.h> |
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19 | #include <rtems/score/cpu.h> |
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20 | #include "bootldr.h" |
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21 | |
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22 | #undef TEST_PPCBUG_CALLS |
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23 | #define FRAME_SIZE 32 |
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24 | #define LOCK_CACHES (HID0_DLOCK|HID0_ILOCK) |
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25 | #define INVL_CACHES (HID0_DCI|HID0_ICFI) |
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26 | #define ENBL_CACHES (HID0_DCE|HID0_ICE) |
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27 | |
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28 | #define USE_PPCBUG |
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29 | #undef USE_PPCBUG |
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30 | |
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31 | #define MONITOR_ENTER \ |
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32 | mfmsr r10 ; \ |
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33 | ori r10,r10,MSR_IP ; \ |
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34 | mtmsr r10 ; \ |
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35 | li r10,0x63 ; \ |
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36 | sc |
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37 | |
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38 | START_GOT |
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39 | GOT_ENTRY(_GOT2_TABLE_) |
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40 | GOT_ENTRY(_FIXUP_TABLE_) |
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41 | GOT_ENTRY(.bss) |
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42 | GOT_ENTRY(codemove) |
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43 | GOT_ENTRY(0) |
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44 | GOT_ENTRY(__bd) |
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45 | GOT_ENTRY(moved) |
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46 | GOT_ENTRY(_binary_rtems_gz_start) |
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47 | GOT_ENTRY(_binary_initrd_gz_start) |
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48 | GOT_ENTRY(_binary_initrd_gz_end) |
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49 | #ifdef TEST_PPCBUG_CALLS |
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50 | GOT_ENTRY(banner_start) |
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51 | GOT_ENTRY(banner_end) |
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52 | #endif |
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53 | END_GOT |
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54 | .globl start |
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55 | .type start,@function |
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56 | /* Point the stack into the PreP partition header in the x86 reserved |
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57 | * code area, so that simple C routines can be called. |
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58 | */ |
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59 | start: |
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60 | #ifdef USE_PPCBUG |
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61 | MONITOR_ENTER |
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62 | #endif |
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63 | bl 1f |
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64 | 1: mflr r1 |
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65 | li r0,0 |
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66 | stwu r0,start-1b-0x400+0x1b0-FRAME_SIZE(r1) |
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67 | stmw r26,FRAME_SIZE-24(r1) |
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68 | GET_GOT |
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69 | mfmsr r28 /* Turn off interrupts */ |
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70 | ori r0,r28,MSR_EE |
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71 | xori r0,r0,MSR_EE |
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72 | mtmsr r0 |
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73 | |
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74 | /* Enable the caches, from now on cr2.eq set means processor is 601 */ |
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75 | mfpvr r0 |
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76 | mfspr r29,HID0 |
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77 | srwi r0,r0,16 |
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78 | cmplwi cr2,r0,1 |
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79 | beq 2,2f |
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80 | #ifndef USE_PPCBUG |
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81 | ori r0,r29,ENBL_CACHES|INVL_CACHES|LOCK_CACHES |
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82 | xori r0,r0,INVL_CACHES|LOCK_CACHES |
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83 | sync |
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84 | isync |
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85 | mtspr HID0,r0 |
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86 | #endif |
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87 | 2: bl reloc |
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88 | |
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89 | /* save all the parameters and the orginal msr/hid0/r31 */ |
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90 | lwz bd,GOT(__bd) |
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91 | stw r3,0(bd) |
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92 | stw r4,4(bd) |
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93 | stw r5,8(bd) |
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94 | stw r6,12(bd) |
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95 | lis r3,__size@sectoff@ha |
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96 | stw r7,16(bd) |
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97 | stw r8,20(bd) |
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98 | addi r3,r3,__size@sectoff@l |
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99 | stw r9,24(bd) |
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100 | stw r10,28(bd) |
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101 | stw r28,o_msr(bd) |
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102 | stw r29,o_hid0(bd) |
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103 | stw r31,o_r31(bd) |
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104 | |
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105 | /* Call the routine to fill boot_data structure from residual data. |
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106 | * And to find where the code has to be moved. |
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107 | */ |
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108 | bl early_setup |
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109 | |
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110 | /* Now we need to relocate ourselves, where we are told to. First put a |
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111 | * copy of the codemove routine to some place in memory. |
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112 | * (which may be where the 0x41 partition was loaded, so size is critical). |
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113 | */ |
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114 | lwz r4,GOT(codemove) |
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115 | li r5,_size_codemove |
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116 | lwz r3,mover(bd) |
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117 | lwz r6,cache_lsize(bd) |
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118 | bl codemove |
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119 | mtctr r3 # Where the temporary codemove is. |
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120 | lwz r3,image(bd) |
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121 | lis r5,_edata@sectoff@ha |
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122 | lwz r4,GOT(0) # Our own address |
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123 | addi r5,r5,_edata@sectoff@l |
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124 | lwz r6,cache_lsize(bd) |
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125 | lwz r8,GOT(moved) |
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126 | sub r7,r3,r4 # Difference to adjust pointers. |
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127 | add r8,r8,r7 |
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128 | add r30,r30,r7 |
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129 | add bd,bd,r7 |
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130 | /* Call the copy routine but return to the new area. */ |
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131 | mtlr r8 # for the return address |
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132 | bctr # returns to the moved instruction |
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133 | /* Establish the new top stack frame. */ |
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134 | moved: lwz r1,stack(bd) |
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135 | li r0,0 |
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136 | stwu r0,-16(r1) |
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137 | |
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138 | /* relocate again */ |
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139 | bl reloc |
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140 | /* Clear all of BSS */ |
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141 | lwz r10,GOT(.bss) |
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142 | li r0,__bss_words@sectoff@l |
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143 | subi r10,r10,4 |
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144 | cmpwi r0,0 |
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145 | mtctr r0 |
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146 | li r0,0 |
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147 | beq 4f |
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148 | 3: stwu r0,4(r10) |
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149 | bdnz 3b |
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150 | |
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151 | /* Final memory initialization. First switch to unmapped mode |
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152 | * in case the FW had set the MMU on, and flush the TLB to avoid |
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153 | * stale entries from interfering. No I/O access is allowed |
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154 | * during this time! |
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155 | */ |
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156 | #ifndef USE_PPCBUG |
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157 | 4: bl MMUoff |
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158 | #endif |
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159 | bl flush_tlb |
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160 | /* Some firmware versions leave stale values in the BATs, it's time |
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161 | * to invalidate them to avoid interferences with our own mappings. |
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162 | * But the 601 valid bit is in the BATL (IBAT only) and others are in |
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163 | * the [ID]BATU. Bloat, bloat.. fortunately thrown away later. |
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164 | */ |
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165 | li r3,0 |
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166 | beq cr2,5f |
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167 | mtdbatu 0,r3 |
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168 | mtdbatu 1,r3 |
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169 | mtdbatu 2,r3 |
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170 | mtdbatu 3,r3 |
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171 | 5: mtibatu 0,r3 |
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172 | mtibatl 0,r3 |
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173 | mtibatu 1,r3 |
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174 | mtibatl 1,r3 |
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175 | mtibatu 2,r3 |
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176 | mtibatl 2,r3 |
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177 | mtibatu 3,r3 |
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178 | mtibatl 3,r3 |
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179 | lis r3,__size@sectoff@ha |
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180 | addi r3,r3,__size@sectoff@l |
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181 | sync # We are going to touch SDR1 ! |
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182 | bl mm_init |
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183 | bl MMUon |
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184 | |
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185 | /* Now we are mapped and can perform I/O if we want */ |
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186 | #ifdef TEST_PPCBUG_CALLS |
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187 | /* Experience seems to show that PPCBug can only be called with the |
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188 | * data cache disabled and with MMU disabled. Bummer. |
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189 | */ |
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190 | li r10,0x22 # .OUTLN |
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191 | lwz r3,GOT(banner_start) |
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192 | lwz r4,GOT(banner_end) |
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193 | sc |
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194 | #endif |
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195 | bl setup_hw |
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196 | lwz r4,GOT(_binary_rtems_gz_start) |
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197 | lis r5,_rtems_gz_size@sectoff@ha |
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198 | lwz r6,GOT(_binary_initrd_gz_start) |
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199 | lis r3,_rtems_size@sectoff@ha |
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200 | lwz r7,GOT(_binary_initrd_gz_end) |
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201 | addi r5,r5,_rtems_gz_size@sectoff@l |
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202 | addi r3,r3,_rtems_size@sectoff@l |
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203 | sub r7,r7,r6 |
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204 | bl decompress_kernel |
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205 | |
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206 | /* Back here we are unmapped and we start the kernel, passing up to eight |
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207 | * parameters just in case, only r3 to r7 used for now. Flush the tlb so |
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208 | * that the loaded image starts in a clean state. |
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209 | */ |
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210 | bl flush_tlb |
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211 | lwz r3,0(bd) |
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212 | lwz r4,4(bd) |
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213 | lwz r5,8(bd) |
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214 | lwz r6,12(bd) |
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215 | lwz r7,16(bd) |
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216 | lwz r8,20(bd) |
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217 | lwz r9,24(bd) |
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218 | lwz r10,28(bd) |
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219 | |
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220 | lwz r30,0(0) |
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221 | mtctr r30 |
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222 | /* |
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223 | * Linux code again |
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224 | lis r30,0xdeadc0de@ha |
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225 | addi r30,r30,0xdeadc0de@l |
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226 | stw r30,0(0) |
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227 | li r30,0 |
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228 | */ |
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229 | dcbst 0,r30 /* Make sure it's in memory ! */ |
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230 | /* We just flash invalidate and disable the dcache, unless it's a 601, |
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231 | * critical areas have been flushed and we don't care about the stack |
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232 | * and other scratch areas. |
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233 | */ |
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234 | beq cr2,1f |
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235 | mfspr r0,HID0 |
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236 | ori r0,r0,HID0_DCI|HID0_DCE |
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237 | sync |
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238 | mtspr HID0,r0 |
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239 | xori r0,r0,HID0_DCI|HID0_DCE |
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240 | mtspr HID0,r0 |
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241 | /* Provisional return to FW, works for PPCBug */ |
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242 | #if 0 |
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243 | MONITOR_ENTER |
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244 | #else |
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245 | 1: bctr |
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246 | #endif |
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247 | |
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248 | |
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249 | |
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250 | /* relocation function, r30 must point to got2+0x8000 */ |
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251 | reloc: |
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252 | /* Adjust got2 pointers, no need to check for 0, this code already puts |
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253 | * a few entries in the table. |
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254 | */ |
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255 | li r0,__got2_entries@sectoff@l |
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256 | la r12,GOT(_GOT2_TABLE_) |
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257 | lwz r11,GOT(_GOT2_TABLE_) |
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258 | mtctr r0 |
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259 | sub r11,r12,r11 |
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260 | addi r12,r12,-4 |
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261 | 1: lwzu r0,4(r12) |
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262 | add r0,r0,r11 |
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263 | stw r0,0(r12) |
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264 | bdnz 1b |
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265 | |
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266 | /* Now adjust the fixups and the pointers to the fixups in case we need |
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267 | * to move ourselves again. |
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268 | */ |
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269 | 2: li r0,__fixup_entries@sectoff@l |
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270 | lwz r12,GOT(_FIXUP_TABLE_) |
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271 | cmpwi r0,0 |
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272 | mtctr r0 |
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273 | addi r12,r12,-4 |
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274 | beqlr |
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275 | 3: lwzu r10,4(r12) |
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276 | lwzux r0,r10,r11 |
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277 | add r0,r0,r11 |
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278 | stw r10,0(r12) |
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279 | stw r0,0(r10) |
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280 | bdnz 3b |
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281 | blr |
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282 | |
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283 | /* Set the MMU on and off: code is always mapped 1:1 and does not need MMU, |
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284 | * but it does not cost so much to map it also and it catches calls through |
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285 | * NULL function pointers. |
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286 | */ |
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287 | .globl MMUon |
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288 | .type MMUon,@function |
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289 | MMUon: mfmsr r0 |
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290 | ori r0,r0,MSR_IR|MSR_DR|MSR_IP |
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291 | mflr r11 |
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292 | xori r0,r0,MSR_IP |
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293 | mtsrr0 r11 |
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294 | mtsrr1 r0 |
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295 | rfi |
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296 | .globl MMUoff |
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297 | .type MMUoff,@function |
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298 | MMUoff: mfmsr r0 |
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299 | ori r0,r0,MSR_IR|MSR_DR|MSR_IP |
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300 | mflr r11 |
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301 | xori r0,r0,MSR_IR|MSR_DR |
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302 | mtsrr0 r11 |
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303 | mtsrr1 r0 |
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304 | rfi |
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305 | |
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306 | /* Due to the PPC architecture (and according to the specifications), a |
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307 | * series of tlbie which goes through a whole 256 MB segment always flushes |
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308 | * the whole TLB. This is obviously overkill and slow, but who cares ? |
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309 | * It takes about 1 ms on a 200 MHz 603e and works even if residual data |
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310 | * get the number of TLB entries wrong. |
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311 | */ |
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312 | flush_tlb: |
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313 | lis r11,0x1000 |
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314 | 1: addic. r11,r11,-0x1000 |
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315 | tlbie r11 |
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316 | bnl 1b |
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317 | /* tlbsync is not implemented on 601, so use sync which seems to be a superset |
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318 | * of tlbsync in all cases and do not bother with CPU dependant code |
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319 | */ |
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320 | sync |
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321 | blr |
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322 | |
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323 | .globl codemove |
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324 | codemove: |
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325 | .type codemove,@function |
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326 | /* r3 dest, r4 src, r5 length in bytes, r6 cachelinesize */ |
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327 | cmplw cr1,r3,r4 |
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328 | addi r0,r5,3 |
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329 | srwi. r0,r0,2 |
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330 | beq cr1,4f /* In place copy is not necessary */ |
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331 | beq 7f /* Protect against 0 count */ |
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332 | mtctr r0 |
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333 | bge cr1,2f |
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334 | |
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335 | la r8,-4(r4) |
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336 | la r7,-4(r3) |
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337 | 1: lwzu r0,4(r8) |
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338 | stwu r0,4(r7) |
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339 | bdnz 1b |
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340 | b 4f |
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341 | |
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342 | 2: slwi r0,r0,2 |
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343 | add r8,r4,r0 |
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344 | add r7,r3,r0 |
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345 | 3: lwzu r0,-4(r8) |
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346 | stwu r0,-4(r7) |
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347 | bdnz 3b |
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348 | |
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349 | /* Now flush the cache: note that we must start from a cache aligned |
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350 | * address. Otherwise we might miss one cache line. |
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351 | */ |
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352 | 4: cmpwi r6,0 |
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353 | add r5,r3,r5 |
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354 | beq 7f /* Always flush prefetch queue in any case */ |
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355 | subi r0,r6,1 |
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356 | andc r3,r3,r0 |
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357 | mr r4,r3 |
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358 | 5: cmplw r4,r5 |
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359 | dcbst 0,r4 |
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360 | add r4,r4,r6 |
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361 | blt 5b |
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362 | sync /* Wait for all dcbst to complete on bus */ |
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363 | mr r4,r3 |
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364 | 6: cmplw r4,r5 |
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365 | icbi 0,r4 |
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366 | add r4,r4,r6 |
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367 | blt 6b |
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368 | 7: sync /* Wait for all icbi to complete on bus */ |
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369 | isync |
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370 | blr |
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371 | .size codemove,.-codemove |
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372 | _size_codemove=.-codemove |
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373 | |
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374 | .section ".data" # .rodata |
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375 | .align 2 |
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376 | #ifdef TEST_PPCBUG_CALLS |
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377 | banner_start: |
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378 | .ascii "This message was printed by PPCBug with MMU enabled" |
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379 | banner_end: |
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380 | #endif |
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