1 | /* |
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2 | * exception.S -- Exception handlers for early boot. |
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3 | * |
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4 | * Copyright (C) 1998, 1999 Gabriel Paubert, paubert@iram.es |
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5 | * |
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6 | * Modified to compile in RTEMS development environment |
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7 | * by Eric Valette |
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8 | * |
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9 | * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in found in the file LICENSE in this distribution or at |
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13 | * http://www.OARcorp.com/rtems/license.html. |
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14 | * |
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15 | * $Id$ |
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16 | */ |
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17 | |
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18 | /* This is an improved version of the TLB interrupt handling code from |
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19 | * the 603e users manual (603eUM.pdf) downloaded from the WWW. All the |
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20 | * visible bugs have been removed. Note that many have survived in the errata |
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21 | * to the 603 user manual (603UMer.pdf). |
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22 | * |
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23 | * This code also pays particular attention to optimization, takes into |
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24 | * account the differences between 603 and 603e, single/multiple processor |
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25 | * systems and tries to order instructions for dual dispatch in many places. |
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26 | * |
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27 | * The optimization has been performed along two lines: |
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28 | * 1) to minimize the number of instruction cache lines needed for the most |
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29 | * common execution paths (the ones that do not result in an exception). |
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30 | * 2) then to order the code to maximize the number of dual issue and |
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31 | * completion opportunities without increasing the number of cache lines |
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32 | * used in the same cases. |
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33 | * |
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34 | * The last goal of this code is to fit inside the address range |
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35 | * assigned to the interrupt vectors: 192 instructions with fixed |
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36 | * entry points every 64 instructions. |
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37 | * |
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38 | * Some typos have also been corrected and the Power l (lowercase L) |
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39 | * instructions replaced by lwz without comment. |
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40 | * |
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41 | * I have attempted to describe the reasons of the order and of the choice |
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42 | * of the instructions but the comments may be hard to understand without |
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43 | * the processor manual. |
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44 | * |
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45 | * Note that the fact that the TLB are reloaded by software in theory |
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46 | * allows tremendous flexibility, for example we could avoid setting the |
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47 | * reference bit of the PTE which will could actually not be accessed because |
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48 | * of protection violation by changing a few lines of code. However, |
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49 | * this would significantly slow down most TLB reload operations, and |
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50 | * this is the reason for which we try never to make checks which would be |
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51 | * redundant with hardware and usually indicate a bug in a program. |
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52 | * |
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53 | * There are some inconsistencies in the documentation concerning the |
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54 | * settings of SRR1 bit 15. All recent documentations say now that it is set |
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55 | * for stores and cleared for loads. Anyway this handler never uses this bit. |
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56 | * |
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57 | * A final remark, the rfi instruction seems to implicitly clear the |
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58 | * MSR<14> (tgpr)bit. The documentation claims that this bit is restored |
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59 | * from SRR1 by rfi, but the corresponding bit in SRR1 is the LRU way bit. |
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60 | * Anyway, the only exception which can occur while TGPR is set is a machine |
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61 | * check which would indicate an unrecoverable problem. Recent documentation |
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62 | * now says in some place that rfi clears MSR<14>. |
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63 | * |
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64 | * TLB software load for 602/603/603e/603ev: |
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65 | * Specific Instructions: |
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66 | * tlbld - write the dtlb with the pte in rpa reg |
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67 | * tlbli - write the itlb with the pte in rpa reg |
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68 | * Specific SPRs: |
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69 | * dmiss - address of dstream miss |
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70 | * imiss - address of istream miss |
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71 | * hash1 - address primary hash PTEG address |
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72 | * hash2 - returns secondary hash PTEG address |
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73 | * iCmp - returns the primary istream compare value |
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74 | * dCmp - returns the primary dstream compare value |
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75 | * rpa - the second word of pte used by tlblx |
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76 | * Other specific resources: |
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77 | * cr0 saved in 4 high order bits of SRR1, |
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78 | * SRR1 bit 14 [WAY] selects TLB set to load from LRU algorithm |
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79 | * gprs r0..r3 shadowed by the setting of MSR bit 14 [TGPR] |
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80 | * other bits in SRR1 (unused by this handler but see earlier comments) |
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81 | * |
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82 | * There are three basic flows corresponding to three vectors: |
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83 | * 0x1000: Instruction TLB miss, |
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84 | * 0x1100: Data TLB miss on load, |
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85 | * 0x1200: Data TLB miss on store or not dirty page |
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86 | */ |
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87 | |
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88 | /* define the following if code does not have to run on basic 603 */ |
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89 | /* #define USE_KEY_BIT */ |
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90 | |
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91 | /* define the following for safe multiprocessing */ |
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92 | /* #define MULTIPROCESSING */ |
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93 | |
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94 | /* define the following for mixed endian */ |
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95 | /* #define CHECK_MIXED_ENDIAN */ |
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96 | |
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97 | /* define the following if entries always have the reference bit set */ |
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98 | #define ASSUME_REF_SET |
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99 | |
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100 | /* Some OS kernels may want to keep a single copy of the dirty bit in a per |
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101 | * page table. In this case writable pages are always write-protected as long |
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102 | * as they are clean, and the dirty bit set actually means that the page |
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103 | * is writable. |
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104 | */ |
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105 | #define DIRTY_MEANS_WRITABLE |
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106 | |
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107 | #include <libcpu/cpu.h> |
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108 | #include "asm.h" |
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109 | #include "bootldr.h" |
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110 | |
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111 | /* |
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112 | * Instruction TLB miss flow |
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113 | * Entry at 0x1000 with the following: |
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114 | * srr0 -> address of instruction that missed |
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115 | * srr1 -> 0:3=cr0, 13=1 (instruction), 14=lru way, 16:31=saved MSR |
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116 | * msr<tgpr> -> 1 |
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117 | * iMiss -> ea that missed |
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118 | * iCmp -> the compare value for the va that missed |
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119 | * hash1 -> pointer to first hash pteg |
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120 | * hash2 -> pointer to second hash pteg |
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121 | * |
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122 | * Register usage: |
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123 | * r0 is limit address during search / scratch after |
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124 | * r1 is pte data / error code for ISI exception when search fails |
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125 | * r2 is pointer to pte |
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126 | * r3 is compare value during search / scratch after |
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127 | */ |
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128 | /* Binutils or assembler bug ? Declaring the section executable and writable |
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129 | * generates an error message on the @fixup entries. |
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130 | */ |
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131 | .section .exception,"aw" |
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132 | # .org 0x1000 # instruction TLB miss entry point |
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133 | .globl tlb_handlers |
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134 | tlb_handlers: |
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135 | .type tlb_handlers,@function |
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136 | #define ISIVec tlb_handlers-0x1000+0x400 |
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137 | #define DSIVec tlb_handlers-0x1000+0x300 |
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138 | mfspr r2,HASH1 |
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139 | lwz r1,0(r2) # Start memory access as soon as possible |
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140 | mfspr r3,ICMP # to load the cache. |
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141 | 0: la r0,48(r2) # Use explicit loop to avoid using ctr |
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142 | 1: cmpw r1,r3 # In theory the loop is somewhat slower |
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143 | beq- 2f # than documentation example |
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144 | cmpw r0,r2 # but we gain from starting cache load |
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145 | lwzu r1,8(r2) # earlier and using slots between load |
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146 | bne+ 1b # and comparison for other purposes. |
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147 | cmpw r1,r3 |
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148 | bne- 4f # Secondary hash check |
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149 | 2: lwz r1,4(r2) # Found: load second word of PTE |
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150 | mfspr r0,IMISS # get miss address during load delay |
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151 | #ifdef ASSUME_REF_SET |
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152 | andi. r3,r1,8 # check for guarded memory |
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153 | bne- 5f |
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154 | mtspr RPA,r1 |
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155 | mfsrr1 r3 |
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156 | tlbli r0 |
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157 | #else |
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158 | /* This is basically the original code from the manual. */ |
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159 | # andi. r3,r1,8 # check for guarded memory |
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160 | # bne- 5f |
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161 | # andi. r3,r1,0x100 # check R bit ahead to help folding |
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162 | /* However there is a better solution: these last three instructions can be |
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163 | replaced by the following which should cause less pipeline stalls because |
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164 | both tests are combined and there is a single CR rename buffer */ |
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165 | extlwi r3,r1,6,23 # Keep only RCWIMG in 6 most significant bits. |
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166 | rlwinm. r3,r3,5,0,27 # Keep only G (in sign) and R and test. |
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167 | blt- 5f # Negative means guarded, zero R not set. |
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168 | mfsrr1 r3 # get saved cr0 bits now to dual issue |
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169 | ori r1,r1,0x100 |
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170 | mtspr RPA,r1 |
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171 | tlbli r0 |
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172 | /* Do not update PTE if R bit already set, this will save one cache line |
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173 | writeback at a later time, and avoid even more bus traffic in |
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174 | multiprocessing systems, when several processors access the same PTEGs. |
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175 | We also hope that the reference bit will be already set. */ |
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176 | bne+ 3f |
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177 | #ifdef MULTIPROCESSING |
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178 | srwi r1,r1,8 # get byte 7 of pte |
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179 | stb r1,+6(r2) # update page table |
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180 | #else |
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181 | sth r1,+6(r2) # update page table |
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182 | #endif |
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183 | #endif |
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184 | 3: mtcrf 0x80,r3 # restore CR0 |
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185 | rfi # return to executing program |
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186 | |
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187 | /* The preceding code is 20 to 25 instructions long, which occupies |
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188 | 3 or 4 cache lines. */ |
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189 | 4: andi. r0,r3,0x0040 # see if we have done second hash |
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190 | lis r1,0x4000 # set up error code in case next branch taken |
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191 | bne- 6f # speculatively issue the following |
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192 | mfspr r2,HASH2 # get the second pointer |
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193 | ori r3,r3,0x0040 # change the compare value |
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194 | lwz r1,0(r2) # load first entry |
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195 | b 0b # and go back to main loop |
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196 | /* We are now at 27 to 32 instructions, using 3 or 4 cache lines for all |
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197 | cases in which the TLB is successfully loaded. */ |
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198 | |
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199 | /* Guarded memory protection violation: synthesize an ISI exception. */ |
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200 | 5: lis r1,0x1000 # set srr1<3>=1 to flag guard violation |
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201 | /* Entry Not Found branches here with r1 correctly set. */ |
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202 | 6: mfsrr1 r3 |
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203 | mfmsr r0 |
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204 | insrwi r1,r3,16,16 # build srr1 for ISI exception |
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205 | mtsrr1 r1 # set srr1 |
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206 | /* It seems few people have realized rlwinm can be used to clear a bit or |
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207 | a field of contiguous bits in a register by setting mask_begin>mask_end. */ |
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208 | rlwinm r0,r0,0,15,13 # clear the msr<tgpr> bit |
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209 | mtcrf 0x80, r3 # restore CR0 |
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210 | mtmsr r0 # flip back to the native gprs |
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211 | isync # Required from 602 doc! |
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212 | b ISIVec # go to instruction access exception |
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213 | /* Up to now there are 37 to 42 instructions so at least 20 could be |
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214 | inserted for complex cases or for statistics recording. */ |
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215 | |
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216 | |
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217 | /* |
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218 | Data TLB miss on load flow |
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219 | Entry at 0x1100 with the following: |
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220 | srr0 -> address of instruction that caused the miss |
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221 | srr1 -> 0:3=cr0, 13=0 (data), 14=lru way, 15=0, 16:31=saved MSR |
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222 | msr<tgpr> -> 1 |
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223 | dMiss -> ea that missed |
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224 | dCmp -> the compare value for the va that missed |
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225 | hash1 -> pointer to first hash pteg |
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226 | hash2 -> pointer to second hash pteg |
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227 | |
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228 | Register usage: |
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229 | r0 is limit address during search / scratch after |
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230 | r1 is pte data / error code for DSI exception when search fails |
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231 | r2 is pointer to pte |
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232 | r3 is compare value during search / scratch after |
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233 | */ |
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234 | .org tlb_handlers+0x100 |
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235 | mfspr r2,HASH1 |
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236 | lwz r1,0(r2) # Start memory access as soon as possible |
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237 | mfspr r3,DCMP # to load the cache. |
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238 | 0: la r0,48(r2) # Use explicit loop to avoid using ctr |
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239 | 1: cmpw r1,r3 # In theory the loop is somewhat slower |
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240 | beq- 2f # than documentation example |
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241 | cmpw r0,r2 # but we gain from starting cache load |
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242 | lwzu r1,8(r2) # earlier and using slots between load |
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243 | bne+ 1b # and comparison for other purposes. |
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244 | cmpw r1,r3 |
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245 | bne- 4f # Secondary hash check |
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246 | 2: lwz r1,4(r2) # Found: load second word of PTE |
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247 | mfspr r0,DMISS # get miss address during load delay |
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248 | #ifdef ASSUME_REF_SET |
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249 | mtspr RPA,r1 |
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250 | mfsrr1 r3 |
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251 | tlbld r0 |
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252 | #else |
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253 | andi. r3,r1,0x100 # check R bit ahead to help folding |
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254 | mfsrr1 r3 # get saved cr0 bits now to dual issue |
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255 | ori r1,r1,0x100 |
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256 | mtspr RPA,r1 |
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257 | tlbld r0 |
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258 | /* Do not update PTE if R bit already set, this will save one cache line |
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259 | writeback at a later time, and avoid even more bus traffic in |
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260 | multiprocessing systems, when several processors access the same PTEGs. |
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261 | We also hope that the reference bit will be already set. */ |
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262 | bne+ 3f |
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263 | #ifdef MULTIPROCESSING |
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264 | srwi r1,r1,8 # get byte 7 of pte |
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265 | stb r1,+6(r2) # update page table |
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266 | #else |
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267 | sth r1,+6(r2) # update page table |
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268 | #endif |
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269 | #endif |
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270 | 3: mtcrf 0x80,r3 # restore CR0 |
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271 | rfi # return to executing program |
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272 | |
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273 | /* The preceding code is 18 to 23 instructions long, which occupies |
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274 | 3 cache lines. */ |
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275 | 4: andi. r0,r3,0x0040 # see if we have done second hash |
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276 | lis r1,0x4000 # set up error code in case next branch taken |
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277 | bne- 9f # speculatively issue the following |
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278 | mfspr r2,HASH2 # get the second pointer |
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279 | ori r3,r3,0x0040 # change the compare value |
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280 | lwz r1,0(r2) # load first entry asap |
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281 | b 0b # and go back to main loop |
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282 | /* We are now at 25 to 30 instructions, using 3 or 4 cache lines for all |
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283 | cases in which the TLB is successfully loaded. */ |
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284 | |
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285 | |
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286 | /* |
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287 | Data TLB miss on store or not dirty page flow |
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288 | Entry at 0x1200 with the following: |
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289 | srr0 -> address of instruction that caused the miss |
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290 | srr1 -> 0:3=cr0, 13=0 (data), 14=lru way, 15=1, 16:31=saved MSR |
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291 | msr<tgpr> -> 1 |
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292 | dMiss -> ea that missed |
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293 | dCmp -> the compare value for the va that missed |
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294 | hash1 -> pointer to first hash pteg |
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295 | hash2 -> pointer to second hash pteg |
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296 | |
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297 | Register usage: |
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298 | r0 is limit address during search / scratch after |
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299 | r1 is pte data / error code for DSI exception when search fails |
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300 | r2 is pointer to pte |
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301 | r3 is compare value during search / scratch after |
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302 | */ |
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303 | .org tlb_handlers+0x200 |
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304 | mfspr r2,HASH1 |
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305 | lwz r1,0(r2) # Start memory access as soon as possible |
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306 | mfspr r3,DCMP # to load the cache. |
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307 | 0: la r0,48(r2) # Use explicit loop to avoid using ctr |
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308 | 1: cmpw r1,r3 # In theory the loop is somewhat slower |
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309 | beq- 2f # than documentation example |
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310 | cmpw r0,r2 # but we gain from starting cache load |
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311 | lwzu r1,8(r2) # earlier and using slots between load |
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312 | bne+ 1b # and comparison for other purposes. |
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313 | cmpw r1,r3 |
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314 | bne- 4f # Secondary hash check |
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315 | 2: lwz r1,4(r2) # Found: load second word of PTE |
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316 | mfspr r0,DMISS # get miss address during load delay |
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317 | /* We could simply set the C bit and then rely on hardware to flag protection |
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318 | violations. This raises the problem that a page which actually has not been |
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319 | modified may be marked as dirty and violates the OEA model for guaranteed |
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320 | bit settings (table 5-8 of 603eUM.pdf). This can have harmful consequences |
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321 | on operating system memory management routines, and play havoc with copy on |
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322 | write schemes. So the protection check is ABSOLUTELY necessary. */ |
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323 | andi. r3,r1,0x80 # check C bit |
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324 | beq- 5f # if (C==0) go to check protection |
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325 | 3: mfsrr1 r3 # get the saved cr0 bits |
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326 | mtspr RPA,r1 # set the pte |
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327 | tlbld r0 # load the dtlb |
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328 | mtcrf 0x80,r3 # restore CR0 |
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329 | rfi # return to executing program |
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330 | /* The preceding code is 20 instructions long, which occupy |
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331 | 3 cache lines. */ |
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332 | 4: andi. r0,r3,0x0040 # see if we have done second hash |
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333 | lis r1,0x4200 # set up error code in case next branch taken |
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334 | bne- 9f # speculatively issue the following |
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335 | mfspr r2,HASH2 # get the second pointer |
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336 | ori r3,r3,0x0040 # change the compare value |
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337 | lwz r1,0(r2) # load first entry asap |
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338 | b 0b # and go back to main loop |
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339 | /* We are now at 27 instructions, using 3 or 4 cache lines for all |
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340 | cases in which the TLB C bit is already set. */ |
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341 | |
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342 | #ifdef DIRTY_MEANS_WRITABLE |
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343 | 5: lis r1,0x0A00 # protection violation on store |
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344 | #else |
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345 | /* |
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346 | Entry found and C==0: check protection before setting C: |
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347 | Register usage: |
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348 | r0 is dMiss register |
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349 | r1 is PTE entry (to be copied to RPA if success) |
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350 | r2 is pointer to pte |
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351 | r3 is trashed |
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352 | |
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353 | For the 603e, the key bit in SRR1 helps to decide whether there is a |
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354 | protection violation. However the way the check is done in the manual is |
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355 | not very efficient. The code shown here works as well for 603 and 603e and |
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356 | is much more efficient for the 603 and comparable to the manual example |
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357 | for 603e. This code however has quite a bad structure due to the fact it |
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358 | has been reordered to speed up the most common cases. |
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359 | */ |
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360 | /* The first of the following two instructions could be replaced by |
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361 | andi. r3,r1,3 but it would compete with cmplwi for cr0 resource. */ |
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362 | 5: clrlwi r3,r1,30 # Extract two low order bits |
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363 | cmplwi r3,2 # Test for PP=10 |
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364 | bne- 7f # assume fallthrough is more frequent |
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365 | 6: ori r1,r1,0x180 # set referenced and changed bit |
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366 | sth r1,6(r2) # update page table |
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367 | b 3b # and finish loading TLB |
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368 | /* We are now at 33 instructions, using 5 cache lines. */ |
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369 | 7: bgt- 8f # if PP=11 then DSI protection exception |
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370 | /* This code only works if key bit is present (602/603e/603ev) */ |
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371 | #ifdef USE_KEY_BIT |
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372 | mfsrr1 r3 # get the KEY bit and test it |
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373 | andis. r3,r3,0x0008 |
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374 | beq 6b # default prediction taken, truly better ? |
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375 | #else |
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376 | /* This code is for all 602 and 603 family models: */ |
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377 | mfsrr1 r3 # Here the trick is to use the MSR PR bit as a |
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378 | mfsrin r0,r0 # shift count for an rlwnm. instruction which |
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379 | extrwi r3,r3,1,17 # extracts and tests the correct key bit from |
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380 | rlwnm. r3,r0,r3,1,1 # the segment register. RISC they said... |
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381 | mfspr r0,DMISS # Restore fault address to r0 |
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382 | beq 6b # if 0 load tlb else protection fault |
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383 | #endif |
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384 | /* We are now at 40 instructions, (37 if using key bit), using 5 cache |
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385 | lines in all cases in which the C bit is successfully set */ |
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386 | 8: lis r1,0x0A00 # protection violation on store |
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387 | #endif /* DIRTY_IS_WRITABLE */ |
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388 | /* PTE entry not found branch here with DSISR code in r1 */ |
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389 | 9: mfsrr1 r3 |
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390 | mtdsisr r1 |
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391 | clrlwi r2,r3,16 # set up srr1 for DSI exception |
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392 | mfmsr r0 |
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393 | /* I have some doubts about the usefulness of the xori instruction in |
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394 | mixed or pure little-endian environment. The address is in the same |
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395 | doubleword, hence in the same protection domain and performing an exclusive |
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396 | or with 7 is only valid for byte accesses. */ |
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397 | #ifdef CHECK_MIXED_ENDIAN |
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398 | andi. r1,r2,1 # test LE bit ahead to help folding |
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399 | #endif |
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400 | mtsrr1 r2 |
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401 | rlwinm r0,r0,0,15,13 # clear the msr<tgpr> bit |
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402 | mfspr r1,DMISS # get miss address |
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403 | #ifdef CHECK_MIXED_ENDIAN |
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404 | beq 1f # if little endian then: |
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405 | xori r1,r1,0x07 # de-mung the data address |
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406 | 1: |
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407 | #endif |
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408 | mtdar r1 # put in dar |
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409 | mtcrf 0x80,r3 # restore CR0 |
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410 | mtmsr r0 # flip back to the native gprs |
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411 | isync # required from 602 manual |
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412 | b DSIVec # branch to DSI exception |
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413 | /* We are now between 50 and 56 instructions. Close to the limit |
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414 | but should be sufficient in case bugs are found. */ |
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415 | /* Altogether the three handlers occupy 128 instructions in the worst |
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416 | case, 64 instructions could still be added (non contiguously). */ |
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417 | .org tlb_handlers+0x300 |
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418 | .globl _handler_glue |
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419 | _handler_glue: |
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420 | /* Entry code for exceptions: DSI (0x300), ISI(0x400), alignment(0x600) and |
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421 | * traps(0x700). In theory it is not necessary to save and restore r13 and all |
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422 | * higher numbered registers, but it is done because it allowed to call the |
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423 | * firmware (PPCBug) for debugging in the very first stages when writing the |
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424 | * bootloader. |
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425 | */ |
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426 | stwu r1,-160(r1) |
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427 | stw r0,save_r(0) |
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428 | mflr r0 |
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429 | stmw r2,save_r(2) |
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430 | bl 0f |
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431 | 0: mfctr r4 |
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432 | stw r0,save_lr |
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433 | mflr r9 /* Interrupt vector + few instructions */ |
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434 | la r10,160(r1) |
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435 | stw r4,save_ctr |
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436 | mfcr r5 |
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437 | lwz r8,2f-0b(r9) |
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438 | mfxer r6 |
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439 | stw r5,save_cr |
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440 | mtctr r8 |
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441 | stw r6,save_xer |
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442 | mfsrr0 r7 |
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443 | stw r10,save_r(1) |
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444 | mfsrr1 r8 |
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445 | stw r7,save_nip |
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446 | la r4,8(r1) |
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447 | lwz r13,1f-0b(r9) |
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448 | rlwinm r3,r9,24,0x3f /* Interrupt vector >> 8 */ |
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449 | stw r8,save_msr |
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450 | bctrl |
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451 | |
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452 | lwz r7,save_msr |
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453 | lwz r6,save_nip |
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454 | mtsrr1 r7 |
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455 | lwz r5,save_xer |
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456 | mtsrr0 r6 |
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457 | lwz r4,save_ctr |
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458 | mtxer r5 |
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459 | lwz r3,save_lr |
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460 | mtctr r4 |
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461 | lwz r0,save_cr |
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462 | mtlr r3 |
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463 | lmw r2,save_r(2) |
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464 | mtcr r0 |
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465 | lwz r0,save_r(0) |
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466 | la r1,160(r1) |
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467 | rfi |
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468 | 1: .long (__bd)@fixup |
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469 | 2: .long (_handler)@fixup |
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470 | .section .fixup,"aw" |
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471 | .align 2 |
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472 | .long 1b, 2b |
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473 | .previous |
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