source: rtems/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c @ b14e2f2

4.104.114.84.95
Last change on this file since b14e2f2 was b14e2f2, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 4, 2003 at 6:52:35 PM

2003-09-04 Joel Sherrill <joel@…>

  • PCI_bus/PCI.h, clock/clock.c, console/85c30.c, console/85c30.h, console/console.c, console/consolebsp.h, console/consolereserveresources.c, console/tbl85c30.c, include/bsp.h, include/coverhd.h, include/gen2.h, include/tod.h, startup/FPGA.c, startup/bspclean.c, startup/bspstart.c, startup/genpvec.c, startup/setvec.c, startup/vmeintr.c, timer/timer.c, tod/tod.c: URL for license changed.
  • Property mode set to 100644
File size: 6.4 KB
Line 
1/*  bspstart.c
2 *
3 *  This set of routines starts the application.  It includes application,
4 *  board, and monitor specific initialization and configuration.
5 *  The generic CPU dependent initialization has been performed
6 *  before any of these are invoked.
7 *
8 *  COPYRIGHT (c) 1989-1997.
9 *  On-Line Applications Research Corporation (OAR).
10 *
11 *  The license and distribution terms for this file may in
12 *  the file LICENSE in this distribution or at
13 *  http://www.rtems.com/license/LICENSE.
14 *
15 *  $Id:
16 */
17
18#include <string.h>
19
20#include <bsp.h>
21#include <rtems/libio.h>
22#include <rtems/libcsupport.h>
23
24/*
25 *  The original table from the application and our copy of it with
26 *  some changes.
27 */
28 
29extern rtems_configuration_table  Configuration;
30rtems_configuration_table         BSP_Configuration;
31rtems_cpu_table                   Cpu_table;
32rtems_unsigned32                  bsp_isr_level;
33
34/*
35 *  Use the shared implementations of the following routines
36 */
37
38void bsp_postdriver_hook(void);
39void bsp_libc_init( void *, unsigned32, int );
40
41/*PAGE
42 *
43 *  bsp_pretasking_hook
44 *
45 *  BSP pretasking hook.  Called just before drivers are initialized.
46 *  Used to setup libc and install any BSP extensions.
47 */
48
49void bsp_pretasking_hook(void)
50{
51  extern int end;
52  rtems_unsigned32 heap_start;
53  rtems_unsigned32 heap_size;
54
55  heap_start = (rtems_unsigned32) &end;
56  if (heap_start & (CPU_ALIGNMENT-1))
57    heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
58
59  heap_size = BSP_Configuration.work_space_start - (void *)&end;
60  heap_size &= 0xfffffff0;  /* keep it as a multiple of 16 bytes */
61
62  bsp_libc_init((void *) heap_start, heap_size, 0);
63
64#ifdef RTEMS_DEBUG
65  rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
66#endif
67}
68
69/*PAGE
70 *
71 *  bsp_predriver_hook
72 *
73 *  Before drivers are setup initialize interupt vectors.
74 */ 
75
76void init_RTC();
77void initialize_PMC();
78
79void bsp_predriver_hook(void)
80{
81  init_RTC();
82
83  init_PCI();
84  initialize_universe();
85  initialize_PCI_bridge ();
86
87#if (HAS_PMC_PSC8)
88  initialize_PMC();
89#endif
90
91 /*
92  * Initialize Bsp General purpose vector table.
93  */
94 initialize_external_exception_vector();
95
96#if (0)
97  /*
98   * XXX - Modify this to write a 48000000 (loop to self) command
99   *       to each interrupt location.  This is better for debug.
100   */
101 bsp_spurious_initialize();
102#endif
103
104}
105
106/*PAGE
107 *
108 *  initialize_PMC
109 */
110
111void initialize_PMC() {
112  volatile rtems_unsigned32 *PMC_addr;
113  rtems_unsigned8  data;
114
115#if (0) /* First Values sent */
116  /*
117   * set PMC base address.
118   */
119  PMC_addr  = SCORE603E_PCI_DEVICE_ADDRESS( 0x14 );
120  *PMC_addr = (SCORE603E_PCI_REGISTER_BASE >> 24) & 0x3f;
121
122  /*
123   * Clear status, enable SERR and memory space only.
124   */
125  PMC_addr = SCORE603E_PCI_DEVICE_ADDRESS( 0x4 );
126  *PMC_addr = 0x0201ff37;
127
128  /*
129   * Bit 0 and 1 HI cause Medium Loopback to occur.
130   */
131  PMC_addr = (volatile rtems_unsigned32 *)
132        SCORE603E_PMC_SERIAL_ADDRESS( 0x100000 );
133  data = *PMC_addr;
134  /*   *PMC_addr = data | 0x3;  */
135  *PMC_addr = data & 0xfc;
136
137#endif
138
139
140#if (1)
141
142  /*
143   * Clear status, enable SERR and memory space only.
144   */
145  PMC_addr = SCORE603E_PCI_DEVICE_ADDRESS( 0x4 );
146  *PMC_addr = 0x020080cc;
147
148  /*
149   * set PMC base address.
150   */
151  PMC_addr  = SCORE603E_PCI_DEVICE_ADDRESS( 0x14 );
152  *PMC_addr = (SCORE603E_PCI_REGISTER_BASE >> 24) & 0x3f;
153
154  PMC_addr = (volatile rtems_unsigned32 *)
155      SCORE603E_PMC_SERIAL_ADDRESS( 0x100000 );
156  data = *PMC_addr;
157  *PMC_addr = data & 0xfc;
158
159#endif
160}
161
162
163
164/*PAGE
165 *
166 *  SCORE603e_bsp_postdriver_hook
167 *
168 *  Standard post driver hook plus some BSP specific stuff.
169 */
170 
171void SCORE603e_bsp_postdriver_hook(void)
172{
173  extern void Init_EE_mask_init(void);
174
175  bsp_postdriver_hook();
176
177  Init_EE_mask_init();
178}
179
180void bsp_set_trap_vectors( void );
181
182/*PAGE
183 *
184 *  bsp_start
185 *
186 *  This routine does the bulk of the system initialization.
187 */
188
189void bsp_start( void )
190{
191  unsigned char *work_space_start;
192  unsigned int  msr_value = 0x0000;
193  volatile rtems_unsigned32 *ptr;
194
195  rtems_bsp_delay( 1000 );
196
197  /*
198   *  Zero out lots of memory
199   */
200
201  memset(
202    &end,
203    0,
204    (unsigned char *)&RAM_END - (unsigned char *) &end
205  );
206
207  /*
208   *  There are multiple ROM monitors available for this board. 
209   */
210#if (SCORE603E_USE_SDS)
211
212  /*
213   * Write instruction for Unconditional Branch to ROM vector.
214   */
215   
216   Code = 0x4bf00002;         
217   for (Address = 0x100; Address <= 0xe00; Address += 0x100) { 
218     A_Vector = (unsigned32    *)Address;
219     Code = 0x4bf00002 + Address;
220     *A_Vector = Code;
221   }
222   
223   for (Address = 0x1000; Address <= 0x1400; Address += 0x100) { 
224     A_Vector = (unsigned32    *)Address;
225     Code = 0x4bf00002 + Address;
226     *A_Vector = Code;
227   }
228   
229  Cpu_table.exceptions_in_RAM = TRUE;
230  msr_value = 0x2030;
231
232#elif (SCORE603E_USE_OPEN_FIRMWARE)
233  Cpu_table.exceptions_in_RAM = TRUE;
234  msr_value = 0x2030;
235
236#elif (SCORE603E_USE_NONE)
237  Cpu_table.exceptions_in_RAM = TRUE;
238  msr_value = 0x2030;
239  _CPU_MSR_SET( msr_value );
240  bsp_set_trap_vectors();
241
242#elif (SCORE603E_USE_DINK)
243  Cpu_table.exceptions_in_RAM = TRUE;
244  msr_value = 0x2030;
245  _CPU_MSR_SET( msr_value );
246
247  /*
248   * Override the DINK error on a Decrementor interrupt.
249   */
250  /* org    dec_vector  - rfi */
251  ptr = (rtems_unsigned32 *)0x900;
252  *ptr = 0x4c000064;
253
254#else
255#error "SCORE603E BSPSTART.C -- what ROM monitor are you using"
256#endif
257
258  _CPU_MSR_SET( msr_value );
259
260  /*
261   *  Need to "allocate" the memory for the RTEMS Workspace and
262   *  tell the RTEMS configuration where it is.  This memory is
263   *  not malloc'ed.  It is just "pulled from the air".
264   */
265
266  work_space_start = 
267    (unsigned char *)&RAM_END - BSP_Configuration.work_space_size;
268
269  if ( work_space_start <= (unsigned char *)&end ) {
270    DEBUG_puts( "bspstart: Not enough RAM!!!\n" );
271    bsp_cleanup();
272  }
273
274  BSP_Configuration.work_space_start = work_space_start;
275
276  /*
277   *  initialize the CPU table for this BSP
278   */
279
280  /* Cpu_table.exceptions_in_RAM was set above */
281  Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */
282  Cpu_table.predriver_hook  = bsp_predriver_hook;   /* Init vectors    */
283  Cpu_table.postdriver_hook = SCORE603e_bsp_postdriver_hook;
284  Cpu_table.clicks_per_usec = 66 / 4;  /* XXX get from linkcmds */
285  Cpu_table.do_zero_of_workspace = TRUE;
286  Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
287  Cpu_table.idle_task_stack_size = (3 * STACK_MINIMUM_SIZE);
288
289#if ( PPC_USE_DATA_CACHE )
290  instruction_cache_enable (); 
291  data_cache_enable ();
292#endif
293}
294
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