[80207b8] | 1 | /* |
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| 2 | * This routine does the bulk of the system initialization. |
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| 3 | */ |
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| 4 | |
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| 5 | /* |
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[c5833ef8] | 6 | * COPYRIGHT (c) 1989-2010. |
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[9c448e1] | 7 | * On-Line Applications Research Corporation (OAR). |
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| 8 | * |
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[42b6dd2a] | 9 | * The license and distribution terms for this file may be |
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| 10 | * found in the file LICENSE in this distribution or at |
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[c499856] | 11 | * http://www.rtems.org/license/LICENSE. |
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[9c448e1] | 12 | */ |
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| 13 | |
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[eba2e4f] | 14 | #include <string.h> |
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| 15 | |
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[9c448e1] | 16 | #include <bsp.h> |
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[80207b8] | 17 | #include <bsp/bootcard.h> |
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[a714cb4] | 18 | #include <rtems/libio.h> |
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[42b6dd2a] | 19 | #include <rtems/libcsupport.h> |
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| 20 | #include <rtems/bspIo.h> |
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[24bf11e] | 21 | #include <rtems/counter.h> |
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[40e7ae2] | 22 | #include <libcpu/cpuIdent.h> |
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[c5833ef8] | 23 | #include <bsp/irq.h> |
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[42b6dd2a] | 24 | |
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| 25 | #define DEBUG 0 |
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[40e7ae2] | 26 | |
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| 27 | /* |
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| 28 | * Where the heap starts; is used by bsp_pretasking_hook; |
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| 29 | */ |
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| 30 | unsigned int BSP_heap_start; |
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[bb41881e] | 31 | |
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| 32 | /* |
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| 33 | * PCI Bus Frequency |
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| 34 | */ |
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[ac7af4a] | 35 | unsigned int BSP_bus_frequency; |
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[bb41881e] | 36 | |
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| 37 | /* |
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| 38 | * processor clock frequency |
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| 39 | */ |
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[ac7af4a] | 40 | unsigned int BSP_processor_frequency; |
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[bb41881e] | 41 | |
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| 42 | /* |
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| 43 | * Time base divisior (how many tick for 1 second). |
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[9f6aaf7] | 44 | * Note: Calibrated with an application using a 20ms timer and |
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| 45 | * a scope. |
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[bb41881e] | 46 | */ |
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[9f6aaf7] | 47 | unsigned int BSP_time_base_divisor = 3960; |
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[9c448e1] | 48 | |
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[07e9642c] | 49 | /* |
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| 50 | * Driver configuration parameters |
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| 51 | */ |
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| 52 | uint32_t bsp_clicks_per_usec; |
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| 53 | |
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[42b6dd2a] | 54 | /* |
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| 55 | * Memory on this board. |
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| 56 | */ |
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| 57 | extern char RamSize[]; |
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| 58 | uint32_t BSP_mem_size; |
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| 59 | |
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| 60 | extern unsigned long __rtems_end[]; |
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| 61 | |
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[bb41881e] | 62 | void BSP_panic(char *s) |
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| 63 | { |
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| 64 | printk("%s PANIC %s\n",_RTEMS_version, s); |
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| 65 | __asm__ __volatile ("sc"); |
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| 66 | } |
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| 67 | |
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| 68 | void _BSP_Fatal_error(unsigned int v) |
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| 69 | { |
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| 70 | printk("%s PANIC ERROR %x\n",_RTEMS_version, v); |
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| 71 | __asm__ __volatile ("sc"); |
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| 72 | } |
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| 73 | |
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[42b6dd2a] | 74 | /*PAGE |
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| 75 | * |
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[9c448e1] | 76 | * bsp_predriver_hook |
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| 77 | * |
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| 78 | * Before drivers are setup initialize interupt vectors. |
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[6128a4a] | 79 | */ |
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[9c448e1] | 80 | |
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[42b6dd2a] | 81 | void init_RTC(void); |
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| 82 | void initialize_PMC(void); |
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[9c448e1] | 83 | |
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| 84 | void bsp_predriver_hook(void) |
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| 85 | { |
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[42b6dd2a] | 86 | init_PCI(); |
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| 87 | initialize_universe(); |
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| 88 | |
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| 89 | #if DEBUG |
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| 90 | printk("bsp_predriver_hook: initialize_PCI_bridge\n"); |
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| 91 | #endif |
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| 92 | initialize_PCI_bridge (); |
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[9c448e1] | 93 | |
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| 94 | #if (HAS_PMC_PSC8) |
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[40e7ae2] | 95 | #if DEBUG |
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| 96 | printk("bsp_predriver_hook: initialize_PMC\n"); |
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| 97 | #endif |
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[9c448e1] | 98 | initialize_PMC(); |
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| 99 | #endif |
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| 100 | |
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[40e7ae2] | 101 | #if DEBUG |
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| 102 | printk("bsp_predriver_hook: End of routine\n"); |
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| 103 | #endif |
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| 104 | |
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[9c448e1] | 105 | } |
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| 106 | |
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| 107 | /*PAGE |
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| 108 | * |
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| 109 | * initialize_PMC |
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| 110 | */ |
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| 111 | |
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[42b6dd2a] | 112 | void initialize_PMC(void) { |
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[3d50574] | 113 | volatile uint32_t *PMC_addr; |
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| 114 | uint32_t data; |
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[9c448e1] | 115 | |
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| 116 | /* |
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| 117 | * Clear status, enable SERR and memory space only. |
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| 118 | */ |
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[f309cda] | 119 | PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x4 ); |
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[3d50574] | 120 | *PMC_addr = 0x020080cc; |
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[40e7ae2] | 121 | #if DEBUG |
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[3d50574] | 122 | printk("initialize_PMC: 0x%x = 0x%x\n", PMC_addr, 0x020080cc); |
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[40e7ae2] | 123 | #endif |
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[9c448e1] | 124 | |
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| 125 | /* |
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| 126 | * set PMC base address. |
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| 127 | */ |
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[f309cda] | 128 | PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x14 ); |
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| 129 | *PMC_addr = (BSP_PCI_REGISTER_BASE >> 24) & 0x3f; |
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[40e7ae2] | 130 | #if DEBUG |
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[3d50574] | 131 | printk("initialize_PMC: 0x%x = 0x%x\n", PMC_addr, ((BSP_PCI_REGISTER_BASE >> 24) & 0x3f)); |
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[40e7ae2] | 132 | #endif |
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[3d50574] | 133 | |
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[40e7ae2] | 134 | PMC_addr = (volatile uint32_t*) |
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[f309cda] | 135 | BSP_PMC_SERIAL_ADDRESS( 0x100000 ); |
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[9c448e1] | 136 | data = *PMC_addr; |
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[3d50574] | 137 | #if DEBUG |
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| 138 | printk("initialize_PMC: Read 0x%x (0x%x)\n", PMC_addr, data ); |
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| 139 | printk("initialize_PMC: Read 0x%x (0x%x)\n", PMC_addr, data & 0xfc ); |
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| 140 | #endif |
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[9c448e1] | 141 | *PMC_addr = data & 0xfc; |
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| 142 | } |
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| 143 | |
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| 144 | /*PAGE |
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| 145 | * |
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| 146 | * bsp_start |
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| 147 | * |
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| 148 | * This routine does the bulk of the system initialization. |
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| 149 | */ |
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| 150 | |
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| 151 | void bsp_start( void ) |
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| 152 | { |
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[5ce16e9] | 153 | unsigned int msr_value = 0x0000; |
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[2d2de4eb] | 154 | uintptr_t intrStackStart; |
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| 155 | uintptr_t intrStackSize; |
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[5ce16e9] | 156 | ppc_cpu_id_t myCpu; |
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| 157 | ppc_cpu_revision_t myCpuRevision; |
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[42b6dd2a] | 158 | |
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[3d5bd91b] | 159 | rtems_bsp_delay( 1000 ); |
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[9c448e1] | 160 | |
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| 161 | /* |
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| 162 | * Zero out lots of memory |
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| 163 | */ |
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[40e7ae2] | 164 | #if DEBUG |
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| 165 | printk("bsp_start: Zero out lots of memory\n"); |
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| 166 | #endif |
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[9c448e1] | 167 | |
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[bb41881e] | 168 | BSP_processor_frequency = 266000000; |
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| 169 | BSP_bus_frequency = 66000000; |
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| 170 | |
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[40e7ae2] | 171 | /* |
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| 172 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() |
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[ac7af4a] | 173 | * function store the result in global variables so that it can be used |
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[40e7ae2] | 174 | * later... |
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| 175 | */ |
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| 176 | myCpu = get_ppc_cpu_type(); |
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| 177 | myCpuRevision = get_ppc_cpu_revision(); |
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[3d50574] | 178 | printk("Cpu: 0x%x Revision: %d\n", myCpu, myCpuRevision); |
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| 179 | printk("Cpu %s\n", get_ppc_cpu_type_name(myCpu) ); |
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[40e7ae2] | 180 | |
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| 181 | /* |
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| 182 | * Initialize the interrupt related settings. |
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| 183 | */ |
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[2d2de4eb] | 184 | intrStackStart = (uintptr_t) __rtems_end; |
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[40e7ae2] | 185 | intrStackSize = rtems_configuration_get_interrupt_stack_size(); |
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[42b6dd2a] | 186 | printk("Interrupt Stack Start: 0x%x Size: 0x%x Heap Start: 0x%x\n", |
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| 187 | intrStackStart, intrStackSize, BSP_heap_start |
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| 188 | ); |
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[387a69a] | 189 | |
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[c5833ef8] | 190 | BSP_mem_size = (uint32_t) RamSize; |
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| 191 | printk("BSP_mem_size: %p\n", RamSize ); |
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[40e7ae2] | 192 | |
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| 193 | /* |
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| 194 | * Initialize default raw exception handlers. |
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| 195 | */ |
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[801b5d8] | 196 | ppc_exc_initialize(intrStackStart, intrStackSize); |
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[9c448e1] | 197 | |
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| 198 | msr_value = 0x2030; |
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| 199 | _CPU_MSR_SET( msr_value ); |
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[d3463aed] | 200 | __asm__ volatile("sync; isync"); |
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[9c448e1] | 201 | |
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| 202 | /* |
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[d34d8692] | 203 | * initialize the device driver parameters |
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[9c448e1] | 204 | */ |
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[40e7ae2] | 205 | #if DEBUG |
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| 206 | printk("bsp_start: set clicks poer usec\n"); |
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| 207 | #endif |
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[42b6dd2a] | 208 | bsp_clicks_per_usec = 66 / 4; |
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[24bf11e] | 209 | rtems_counter_initialize_converter(bsp_clicks_per_usec * 1000000); |
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[42b6dd2a] | 210 | |
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[353be08] | 211 | #if BSP_DATA_CACHE_ENABLED |
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[42b6dd2a] | 212 | #if DEBUG |
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| 213 | printk("bsp_start: cache_enable\n"); |
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| 214 | #endif |
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| 215 | instruction_cache_enable (); |
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| 216 | data_cache_enable (); |
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| 217 | #if DEBUG |
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[353be08] | 218 | printk("bsp_start: END BSP_DATA_CACHE_ENABLED\n"); |
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[42b6dd2a] | 219 | #endif |
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[40e7ae2] | 220 | #endif |
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[3d50574] | 221 | |
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[42b6dd2a] | 222 | /* |
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| 223 | * Initalize RTEMS IRQ system |
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| 224 | */ |
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[ac7af4a] | 225 | #if DEBUG |
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[42b6dd2a] | 226 | printk("bspstart: Call BSP_rtems_irq_mng_init\n"); |
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| 227 | #endif |
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| 228 | BSP_rtems_irq_mng_init(0); |
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[ac7af4a] | 229 | |
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[40e7ae2] | 230 | #if DEBUG |
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| 231 | printk("bsp_start: end BSPSTART\n"); |
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[42b6dd2a] | 232 | ShowBATS(); |
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[40e7ae2] | 233 | #endif |
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[9c448e1] | 234 | } |
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