source: rtems/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c @ f309cda

4.104.114.84.95
Last change on this file since f309cda was f309cda, checked in by Jennifer Averett <Jennifer.Averett@…>, on Apr 11, 2005 at 8:20:18 PM

2005-04-11 Jennifer Averett<jennifer.averett@…>

PR 778/bsps

  • include/bsp.h, include/gen2.h, startup/FPGA.c, startup/Hwr_init.c, startup/bspstart.c, tod/tod.c: modify SCORE_.. to BSP_.. for externally used define's.
  • Property mode set to 100644
File size: 4.8 KB
Line 
1/*  Hwr_init.c
2 *
3 *  $Id:
4 */
5
6#include <bsp.h>
7
8#define PPC603e_SPR_HID0        1008
9#define PPC603e_SPR_HID1        1009
10#define PPC603e_SPR_IBAT0U       528
11#define PPC603e_SPR_IBAT0L       529
12#define PPC603e_SPR_DBAT0U       536
13#define PPC603e_SPR_DBAT0L       537
14#define PPC603e_SPR_IBAT1U       530
15#define PPC603e_SPR_IBAT1L       531
16#define PPC603e_SPR_DBAT1U       538
17#define PPC603e_SPR_DBAT1L       539
18#define PPC603e_SPR_IBAT2U       532
19#define PPC603e_SPR_IBAT2L       533
20#define PPC603e_SPR_DBAT2U       540
21#define PPC603e_SPR_DBAT2L       541
22#define PPC603e_SPR_IBAT3U       534
23#define PPC603e_SPR_IBAT3L       535
24#define PPC603e_SPR_DBAT3U       542
25#define PPC603e_SPR_DBAT3L       543
26#define PPC603e_SPR_DMISS        976
27#define PPC603e_SPR_DCMP         977
28#define PPC603e_SPR_HASH1        978
29#define PPC603e_SPR_HASH2        979
30#define PPC603e_SPR_IMISS        980
31#define PPC603e_SPR_ICMP         981
32#define PPC603e_SPR_RPA          982
33#define PPC603e_SPR_SDR1          25
34#define PPC603e_SPR_PVR          287
35#define PPC603e_SPR_DAR           19
36#define PPC603e_SPR_SPRG0        272
37#define PPC603e_SPR_SPRG1        273
38#define PPC603e_SPR_SPRG2        274
39#define PPC603e_SPR_SPRG3        275
40#define PPC603e_SPR_DSISR         18
41#define PPC603e_SPR_SRR0          26
42#define PPC603e_SPR_SRR1          27
43#define PPC603e_SPR_TBL_WRITE    284
44#define PPC603e_SPR_TBU_WRITE    285
45#define PPC603e_SPR_DEC           22
46#define PPC603e_SPR_IABR        1010
47#define PPC603e_SPR_EAR          282
48
49#define PCI_MEM_CMD   (SCORE603E_PCI_MEM_BASE >> 16)
50
51typedef struct {
52  uint32_t          counter_1_100;
53  uint32_t          counter_hours;
54  uint32_t          counter_min;
55  uint32_t          counter_sec;
56  uint32_t          counter_month;
57  uint32_t          counter_date;
58  uint32_t          counter_year;
59  uint32_t          counter_day_of_week;
60
61  uint32_t          RAM_1_100;
62  uint32_t          RAM_hours;
63  uint32_t          RAM_month;
64  uint32_t          RAM_date;
65  uint32_t          RAM_year;
66  uint32_t          RAM_day_of_week;
67
68  uint32_t          interupt_status_mask;
69  uint32_t          command_register;
70}Harris_RTC;
71
72void init_RTC()
73{
74  volatile Harris_RTC *the_RTC;
75
76  the_RTC = (volatile Harris_RTC *)BSP_RTC_ADDRESS;
77
78  the_RTC->command_register = 0x0;
79}
80
81void init_PCI()
82{
83#if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE)
84  uint32_t         value;
85
86 /*
87  * NOTE:  Accessing any memory location not mapped by the BAT
88  * registers will cause a TLB miss exception.
89  * Set the DBAT1 to be configured for 256M of PCI MEM
90  * at 0xC0000000 with Write-through and Guarded Attributed and
91  * read/write access allowed
92  */
93
94 /* load DBAT1U (spr538) - 256Mbytes, User, Super */
95  value = SCORE603E_PCI_MEM_BASE | 0x1FFF;
96  asm volatile(
97    "isync;"
98    "mtspr 538, %0"
99    : "=r" (value)
100    : "0" (value)
101  );
102
103  /* load DBAT1L (spr539) - Write-through, Guarded and Read/Write */
104  value = SCORE603E_PCI_MEM_BASE | 0x0002;
105  asm volatile (
106      "mtspr 539, %0;"
107      "isync"
108      : "=r" (value)
109      : "0" (value)
110  );
111
112#elif (SCORE603E_USE_DINK)
113  /* DINK Monitor setsup and uses all 4 BAT registers.  */
114  /* The fourth BAT register can be modified to access this area */
115
116#if (0)
117 /*
118  * NOTE:  Accessing any memory location not mapped by the BAT
119  * registers will cause a TLB miss exception.
120  * Set the DBAT3 to be configured for 256M of PCI MEM
121  * at 0xC0000000 with Write-through and Guarded Attributed and
122  * read/write access allowed
123  */
124
125 /* load DBAT3U (spr542) - 256Mbytes, User, Super */
126  value = SCORE603E_PCI_MEM_BASE | 0x1FFF;
127  asm volatile(
128    "isync;"
129    "mtspr 542, %0"
130    : "=r" (value)
131    : "0" (value)
132  );
133
134  /* load DBAT3L (spr543) - Write-through, Guarded and Read/Write */
135  value = SCORE603E_PCI_MEM_BASE | 0x0002;
136  asm volatile (
137      "mtspr 543, %0;"
138      "isync"
139      : "=r" (value)
140      : "0" (value)
141  );
142#endif
143
144#else
145#error "SCORE603E BSPSTART.C -- what ROM monitor are you using"
146#endif
147}
148
149#define PPC_Get_HID0( _value ) \
150  do { \
151      _value = 0;        /* to avoid warnings */ \
152      asm volatile( \
153          "mfspr %0, 0x3f0;"     /* get HID0 */ \
154          "isync" \
155          : "=r" (_value) \
156          : "0" (_value) \
157      ); \
158  } while (0)
159
160#define PPC_Set_HID0( _value ) \
161  do { \
162      asm volatile( \
163          "isync;" \
164          "mtspr 0x3f0, %0;"     /* load HID0 */ \
165          "isync" \
166          : "=r" (_value) \
167          : "0" (_value) \
168      ); \
169  } while (0)
170
171void instruction_cache_enable ()
172{
173  uint32_t         value;
174
175  /*
176   * Enable the instruction cache
177   */
178
179  PPC_Get_HID0( value );
180
181  value |= 0x00008000;       /* Set ICE bit */
182
183  PPC_Set_HID0( value );
184}
185
186void data_cache_enable ()
187{
188  uint32_t         value;
189
190  /*
191   * enable data cache
192   */
193
194  PPC_Get_HID0( value );
195
196  value |= 0x00004000;        /* set DCE bit */
197
198  PPC_Set_HID0( value );
199}
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