source: rtems/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c @ dac4208

4.104.114.84.95
Last change on this file since dac4208 was dac4208, checked in by Ralf Corsepius <ralf.corsepius@…>, on Mar 31, 2004 at 3:47:07 AM

2004-03-31 Ralf Corsepius <ralf_corsepius@…>

  • PCI_bus/PCI.c, PCI_bus/PCI.h, PCI_bus/flash.c, PCI_bus/universe.c, clock/clock.c, console/85c30.c, console/console.c, console/consolebsp.h, include/bsp.h, include/gen2.h, startup/FPGA.c, startup/Hwr_init.c, startup/bspstart.c, startup/genpvec.c, startup/spurious.c, startup/vmeintr.c, timer/timer.c, tod/tod.c: Convert to using c99 fixed size types.
  • Property mode set to 100644
File size: 4.9 KB
Line 
1/*  Hwr_init.c
2 *
3 *  $Id:
4 */
5
6#include <bsp.h>
7
8#define PPC603e_SPR_HID0        1008
9#define PPC603e_SPR_HID1        1009
10#define PPC603e_SPR_IBAT0U       528
11#define PPC603e_SPR_IBAT0L       529
12#define PPC603e_SPR_DBAT0U       536
13#define PPC603e_SPR_DBAT0L       537
14#define PPC603e_SPR_IBAT1U       530
15#define PPC603e_SPR_IBAT1L       531
16#define PPC603e_SPR_DBAT1U       538
17#define PPC603e_SPR_DBAT1L       539
18#define PPC603e_SPR_IBAT2U       532
19#define PPC603e_SPR_IBAT2L       533
20#define PPC603e_SPR_DBAT2U       540
21#define PPC603e_SPR_DBAT2L       541
22#define PPC603e_SPR_IBAT3U       534
23#define PPC603e_SPR_IBAT3L       535
24#define PPC603e_SPR_DBAT3U       542
25#define PPC603e_SPR_DBAT3L       543
26#define PPC603e_SPR_DMISS        976
27#define PPC603e_SPR_DCMP         977
28#define PPC603e_SPR_HASH1        978
29#define PPC603e_SPR_HASH2        979
30#define PPC603e_SPR_IMISS        980
31#define PPC603e_SPR_ICMP         981
32#define PPC603e_SPR_RPA          982
33#define PPC603e_SPR_SDR1          25
34#define PPC603e_SPR_PVR          287
35#define PPC603e_SPR_DAR           19
36#define PPC603e_SPR_SPRG0        272
37#define PPC603e_SPR_SPRG1        273
38#define PPC603e_SPR_SPRG2        274
39#define PPC603e_SPR_SPRG3        275
40#define PPC603e_SPR_DSISR         18
41#define PPC603e_SPR_SRR0          26
42#define PPC603e_SPR_SRR1          27
43#define PPC603e_SPR_TBL_WRITE    284
44#define PPC603e_SPR_TBU_WRITE    285
45#define PPC603e_SPR_DEC           22
46#define PPC603e_SPR_IABR        1010
47#define PPC603e_SPR_EAR          282
48
49
50
51#define PCI_MEM_CMD   (SCORE603E_PCI_MEM_BASE >> 16)
52
53
54typedef struct {
55  uint32_t          counter_1_100;
56  uint32_t          counter_hours;
57  uint32_t          counter_min;
58  uint32_t          counter_sec;
59  uint32_t          counter_month;
60  uint32_t          counter_date;
61  uint32_t          counter_year;
62  uint32_t          counter_day_of_week;
63
64  uint32_t          RAM_1_100;
65  uint32_t          RAM_hours;
66  uint32_t          RAM_month;
67  uint32_t          RAM_date;
68  uint32_t          RAM_year;
69  uint32_t          RAM_day_of_week;
70
71  uint32_t          interupt_status_mask;
72  uint32_t          command_register;
73}Harris_RTC;
74
75void init_RTC()
76{
77  volatile Harris_RTC *the_RTC;
78 
79  the_RTC = (volatile Harris_RTC *)SCORE603E_RTC_ADDRESS;
80
81  the_RTC->command_register = 0x0;
82}
83
84void init_PCI()
85{ 
86#if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE)
87  uint32_t         value;
88
89 /*
90  * NOTE:  Accessing any memory location not mapped by the BAT
91  * registers will cause a TLB miss exception.   
92  * Set the DBAT1 to be configured for 256M of PCI MEM
93  * at 0xC0000000 with Write-through and Guarded Attributed and
94  * read/write access allowed
95  */
96
97 /* load DBAT1U (spr538) - 256Mbytes, User, Super */
98  value = SCORE603E_PCI_MEM_BASE | 0x1FFF;
99  asm volatile(
100    "isync;"
101    "mtspr 538, %0"
102    : "=r" (value)
103    : "0" (value)
104  );
105
106  /* load DBAT1L (spr539) - Write-through, Guarded and Read/Write */
107  value = SCORE603E_PCI_MEM_BASE | 0x0002;
108  asm volatile (
109      "mtspr 539, %0;"
110      "isync"
111      : "=r" (value)
112      : "0" (value)
113  );
114
115#elif (SCORE603E_USE_DINK)
116  /* DINK Monitor setsup and uses all 4 BAT registers.  */
117  /* The fourth BAT register can be modified to access this area */
118
119#if (0)
120 /*
121  * NOTE:  Accessing any memory location not mapped by the BAT
122  * registers will cause a TLB miss exception.   
123  * Set the DBAT3 to be configured for 256M of PCI MEM
124  * at 0xC0000000 with Write-through and Guarded Attributed and
125  * read/write access allowed
126  */
127
128 /* load DBAT3U (spr542) - 256Mbytes, User, Super */
129  value = SCORE603E_PCI_MEM_BASE | 0x1FFF;
130  asm volatile(
131    "isync;"
132    "mtspr 542, %0"
133    : "=r" (value)
134    : "0" (value)
135  );
136
137  /* load DBAT3L (spr543) - Write-through, Guarded and Read/Write */
138  value = SCORE603E_PCI_MEM_BASE | 0x0002;
139  asm volatile (
140      "mtspr 543, %0;"
141      "isync"
142      : "=r" (value)
143      : "0" (value)
144  );
145#endif
146
147#else
148#error "SCORE603E BSPSTART.C -- what ROM monitor are you using"
149#endif
150}
151
152#define PPC_Get_HID0( _value ) \
153  do { \
154      _value = 0;        /* to avoid warnings */ \
155      asm volatile( \
156          "mfspr %0, 0x3f0;"     /* get HID0 */ \
157          "isync" \
158          : "=r" (_value) \
159          : "0" (_value) \
160      ); \
161  } while (0)
162
163#define PPC_Set_HID0( _value ) \
164  do { \
165      asm volatile( \
166          "isync;" \
167          "mtspr 0x3f0, %0;"     /* load HID0 */ \
168          "isync" \
169          : "=r" (_value) \
170          : "0" (_value) \
171      ); \
172  } while (0)
173
174
175void instruction_cache_enable ()
176{
177  uint32_t         value;
178
179  /*
180   * Enable the instruction cache
181   */
182
183  PPC_Get_HID0( value );
184
185  value |= 0x00008000;       /* Set ICE bit */
186
187  PPC_Set_HID0( value );
188}
189
190void data_cache_enable ()
191{
192  uint32_t         value;
193
194  /*
195   * enable data cache
196   */
197
198  PPC_Get_HID0( value );
199
200  value |= 0x00004000;        /* set DCE bit */
201
202  PPC_Set_HID0( value );
203}
204
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