1 | /* Hwr_init.c |
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2 | * |
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3 | * COPYRIGHT (c) 1989-2009. |
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4 | * On-Line Applications Research Corporation (OAR). |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in the file LICENSE in this distribution or at |
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8 | * http://www.rtems.com/license/LICENSE. |
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9 | * |
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10 | * $Id$ |
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11 | */ |
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12 | |
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13 | #include <bsp.h> |
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14 | |
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15 | #define PPC603e_SPR_HID0 1008 |
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16 | #define PPC603e_SPR_HID1 1009 |
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17 | #define PPC603e_SPR_IBAT0U 528 |
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18 | #define PPC603e_SPR_IBAT0L 529 |
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19 | #define PPC603e_SPR_DBAT0U 536 |
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20 | #define PPC603e_SPR_DBAT0L 537 |
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21 | #define PPC603e_SPR_IBAT1U 530 |
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22 | #define PPC603e_SPR_IBAT1L 531 |
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23 | #define PPC603e_SPR_DBAT1U 538 |
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24 | #define PPC603e_SPR_DBAT1L 539 |
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25 | #define PPC603e_SPR_IBAT2U 532 |
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26 | #define PPC603e_SPR_IBAT2L 533 |
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27 | #define PPC603e_SPR_DBAT2U 540 |
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28 | #define PPC603e_SPR_DBAT2L 541 |
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29 | #define PPC603e_SPR_IBAT3U 534 |
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30 | #define PPC603e_SPR_IBAT3L 535 |
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31 | #define PPC603e_SPR_DBAT3U 542 |
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32 | #define PPC603e_SPR_DBAT3L 543 |
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33 | #define PPC603e_SPR_DMISS 976 |
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34 | #define PPC603e_SPR_DCMP 977 |
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35 | #define PPC603e_SPR_HASH1 978 |
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36 | #define PPC603e_SPR_HASH2 979 |
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37 | #define PPC603e_SPR_IMISS 980 |
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38 | #define PPC603e_SPR_ICMP 981 |
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39 | #define PPC603e_SPR_RPA 982 |
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40 | #define PPC603e_SPR_SDR1 25 |
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41 | #define PPC603e_SPR_PVR 287 |
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42 | #define PPC603e_SPR_DAR 19 |
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43 | #define PPC603e_SPR_SPRG0 272 |
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44 | #define PPC603e_SPR_SPRG1 273 |
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45 | #define PPC603e_SPR_SPRG2 274 |
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46 | #define PPC603e_SPR_SPRG3 275 |
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47 | #define PPC603e_SPR_DSISR 18 |
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48 | #define PPC603e_SPR_SRR0 26 |
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49 | #define PPC603e_SPR_SRR1 27 |
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50 | #define PPC603e_SPR_TBL_WRITE 284 |
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51 | #define PPC603e_SPR_TBU_WRITE 285 |
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52 | #define PPC603e_SPR_DEC 22 |
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53 | #define PPC603e_SPR_IABR 1010 |
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54 | #define PPC603e_SPR_EAR 282 |
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55 | |
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56 | #define PCI_MEM_CMD (SCORE603E_PCI_MEM_BASE >> 16) |
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57 | |
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58 | typedef struct { |
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59 | uint32_t counter_1_100; |
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60 | uint32_t counter_hours; |
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61 | uint32_t counter_min; |
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62 | uint32_t counter_sec; |
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63 | uint32_t counter_month; |
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64 | uint32_t counter_date; |
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65 | uint32_t counter_year; |
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66 | uint32_t counter_day_of_week; |
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67 | |
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68 | uint32_t RAM_1_100; |
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69 | uint32_t RAM_hours; |
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70 | uint32_t RAM_month; |
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71 | uint32_t RAM_date; |
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72 | uint32_t RAM_year; |
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73 | uint32_t RAM_day_of_week; |
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74 | |
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75 | uint32_t interupt_status_mask; |
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76 | uint32_t command_register; |
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77 | }Harris_RTC; |
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78 | |
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79 | void init_RTC(void) |
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80 | { |
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81 | volatile Harris_RTC *the_RTC; |
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82 | |
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83 | the_RTC = (volatile Harris_RTC *)BSP_RTC_ADDRESS; |
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84 | |
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85 | the_RTC->command_register = 0x0; |
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86 | } |
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87 | |
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88 | void init_PCI(void) |
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89 | { |
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90 | /* DINK Monitor setsup and uses all 4 BAT registers. */ |
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91 | /* The fourth BAT register can be modified to access this area */ |
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92 | } |
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93 | |
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94 | #define PPC_Get_HID0( _value ) \ |
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95 | do { \ |
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96 | _value = 0; /* to avoid warnings */ \ |
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97 | asm volatile( \ |
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98 | "mfspr %0, 0x3f0;" /* get HID0 */ \ |
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99 | "isync" \ |
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100 | : "=r" (_value) \ |
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101 | : "0" (_value) \ |
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102 | ); \ |
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103 | } while (0) |
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104 | |
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105 | #define PPC_Set_HID0( _value ) \ |
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106 | do { \ |
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107 | asm volatile( \ |
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108 | "isync;" \ |
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109 | "mtspr 0x3f0, %0;" /* load HID0 */ \ |
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110 | "isync" \ |
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111 | : "=r" (_value) \ |
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112 | : "0" (_value) \ |
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113 | ); \ |
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114 | } while (0) |
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115 | |
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116 | void instruction_cache_enable () |
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117 | { |
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118 | uint32_t value; |
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119 | |
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120 | /* |
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121 | * Enable the instruction cache |
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122 | */ |
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123 | |
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124 | PPC_Get_HID0( value ); |
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125 | |
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126 | value |= 0x00008000; /* Set ICE bit */ |
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127 | |
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128 | PPC_Set_HID0( value ); |
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129 | } |
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130 | |
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131 | void data_cache_enable () |
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132 | { |
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133 | uint32_t value; |
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134 | |
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135 | /* |
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136 | * enable data cache |
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137 | */ |
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138 | |
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139 | PPC_Get_HID0( value ); |
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140 | |
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141 | value |= 0x00004000; /* set DCE bit */ |
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142 | |
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143 | PPC_Set_HID0( value ); |
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144 | } |
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