source: rtems/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c @ 8e230e6

4.9
Last change on this file since 8e230e6 was 31a5ec8, checked in by Jennifer Averett <Jennifer.Averett@…>, on May 5, 2009 at 4:18:06 PM

2009-05-05 Jennifer Averett <jennifer.averett@…>

  • Makefile.am, README, configure.ac, preinstall.am, PCI_bus/PCI.c, PCI_bus/PCI.h, PCI_bus/flash.c, PCI_bus/universe.c, console/85c30.c, console/85c30.h, console/console.c, console/consolebsp.h, console/tbl85c30.c, include/bsp.h, include/coverhd.h, include/gen2.h, include/irq-config.h, include/tm27.h, irq/FPGA.c, irq/irq.h, irq/irq_init.c, start/start.S, startup/Hwr_init.c, startup/bspstart.c, timer/timer.c, tod/tod.c: Updated and tested with the latest powerpc isr source
  • irq/no_pic.c: New file.
  • irq/irq.c, startup/genpvec.c, startup/setvec.c, startup/vmeintr.c: Removed.
  • Property mode set to 100644
File size: 3.5 KB
Line 
1/*  Hwr_init.c
2 *
3 *  COPYRIGHT (c) 1989-2009.
4 *  On-Line Applications Research Corporation (OAR).
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.rtems.com/license/LICENSE.
9 *
10 *  $Id$
11 */
12
13#include <bsp.h>
14
15#define PPC603e_SPR_HID0        1008
16#define PPC603e_SPR_HID1        1009
17#define PPC603e_SPR_IBAT0U       528
18#define PPC603e_SPR_IBAT0L       529
19#define PPC603e_SPR_DBAT0U       536
20#define PPC603e_SPR_DBAT0L       537
21#define PPC603e_SPR_IBAT1U       530
22#define PPC603e_SPR_IBAT1L       531
23#define PPC603e_SPR_DBAT1U       538
24#define PPC603e_SPR_DBAT1L       539
25#define PPC603e_SPR_IBAT2U       532
26#define PPC603e_SPR_IBAT2L       533
27#define PPC603e_SPR_DBAT2U       540
28#define PPC603e_SPR_DBAT2L       541
29#define PPC603e_SPR_IBAT3U       534
30#define PPC603e_SPR_IBAT3L       535
31#define PPC603e_SPR_DBAT3U       542
32#define PPC603e_SPR_DBAT3L       543
33#define PPC603e_SPR_DMISS        976
34#define PPC603e_SPR_DCMP         977
35#define PPC603e_SPR_HASH1        978
36#define PPC603e_SPR_HASH2        979
37#define PPC603e_SPR_IMISS        980
38#define PPC603e_SPR_ICMP         981
39#define PPC603e_SPR_RPA          982
40#define PPC603e_SPR_SDR1          25
41#define PPC603e_SPR_PVR          287
42#define PPC603e_SPR_DAR           19
43#define PPC603e_SPR_SPRG0        272
44#define PPC603e_SPR_SPRG1        273
45#define PPC603e_SPR_SPRG2        274
46#define PPC603e_SPR_SPRG3        275
47#define PPC603e_SPR_DSISR         18
48#define PPC603e_SPR_SRR0          26
49#define PPC603e_SPR_SRR1          27
50#define PPC603e_SPR_TBL_WRITE    284
51#define PPC603e_SPR_TBU_WRITE    285
52#define PPC603e_SPR_DEC           22
53#define PPC603e_SPR_IABR        1010
54#define PPC603e_SPR_EAR          282
55
56#define PCI_MEM_CMD   (SCORE603E_PCI_MEM_BASE >> 16)
57
58typedef struct {
59  uint32_t          counter_1_100;
60  uint32_t          counter_hours;
61  uint32_t          counter_min;
62  uint32_t          counter_sec;
63  uint32_t          counter_month;
64  uint32_t          counter_date;
65  uint32_t          counter_year;
66  uint32_t          counter_day_of_week;
67
68  uint32_t          RAM_1_100;
69  uint32_t          RAM_hours;
70  uint32_t          RAM_month;
71  uint32_t          RAM_date;
72  uint32_t          RAM_year;
73  uint32_t          RAM_day_of_week;
74
75  uint32_t          interupt_status_mask;
76  uint32_t          command_register;
77}Harris_RTC;
78
79void init_RTC(void)
80{
81  volatile Harris_RTC *the_RTC;
82
83  the_RTC = (volatile Harris_RTC *)BSP_RTC_ADDRESS;
84
85  the_RTC->command_register = 0x0;
86}
87
88void init_PCI(void)
89{
90  /* DINK Monitor setsup and uses all 4 BAT registers.  */
91  /* The fourth BAT register can be modified to access this area */
92}
93
94#define PPC_Get_HID0( _value ) \
95  do { \
96      _value = 0;        /* to avoid warnings */ \
97      asm volatile( \
98          "mfspr %0, 0x3f0;"     /* get HID0 */ \
99          "isync" \
100          : "=r" (_value) \
101          : "0" (_value) \
102      ); \
103  } while (0)
104
105#define PPC_Set_HID0( _value ) \
106  do { \
107      asm volatile( \
108          "isync;" \
109          "mtspr 0x3f0, %0;"     /* load HID0 */ \
110          "isync" \
111          : "=r" (_value) \
112          : "0" (_value) \
113      ); \
114  } while (0)
115
116void instruction_cache_enable ()
117{
118  uint32_t         value;
119
120  /*
121   * Enable the instruction cache
122   */
123
124  PPC_Get_HID0( value );
125
126  value |= 0x00008000;       /* Set ICE bit */
127
128  PPC_Set_HID0( value );
129}
130
131void data_cache_enable ()
132{
133  uint32_t         value;
134
135  /*
136   * enable data cache
137   */
138
139  PPC_Get_HID0( value );
140
141  value |= 0x00004000;        /* set DCE bit */
142
143  PPC_Set_HID0( value );
144}
Note: See TracBrowser for help on using the repository browser.