[9c448e1] | 1 | /* Hwr_init.c |
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| 2 | * |
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| 3 | * $Id: |
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| 4 | */ |
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| 5 | |
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| 6 | #include <bsp.h> |
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| 7 | |
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| 8 | #define PPC603e_SPR_HID0 1008 |
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| 9 | #define PPC603e_SPR_HID1 1009 |
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| 10 | #define PPC603e_SPR_IBAT0U 528 |
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| 11 | #define PPC603e_SPR_IBAT0L 529 |
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| 12 | #define PPC603e_SPR_DBAT0U 536 |
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| 13 | #define PPC603e_SPR_DBAT0L 537 |
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| 14 | #define PPC603e_SPR_IBAT1U 530 |
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| 15 | #define PPC603e_SPR_IBAT1L 531 |
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| 16 | #define PPC603e_SPR_DBAT1U 538 |
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| 17 | #define PPC603e_SPR_DBAT1L 539 |
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| 18 | #define PPC603e_SPR_IBAT2U 532 |
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| 19 | #define PPC603e_SPR_IBAT2L 533 |
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| 20 | #define PPC603e_SPR_DBAT2U 540 |
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| 21 | #define PPC603e_SPR_DBAT2L 541 |
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| 22 | #define PPC603e_SPR_IBAT3U 534 |
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| 23 | #define PPC603e_SPR_IBAT3L 535 |
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| 24 | #define PPC603e_SPR_DBAT3U 542 |
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| 25 | #define PPC603e_SPR_DBAT3L 543 |
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| 26 | #define PPC603e_SPR_DMISS 976 |
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| 27 | #define PPC603e_SPR_DCMP 977 |
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| 28 | #define PPC603e_SPR_HASH1 978 |
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| 29 | #define PPC603e_SPR_HASH2 979 |
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| 30 | #define PPC603e_SPR_IMISS 980 |
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| 31 | #define PPC603e_SPR_ICMP 981 |
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| 32 | #define PPC603e_SPR_RPA 982 |
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| 33 | #define PPC603e_SPR_SDR1 25 |
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| 34 | #define PPC603e_SPR_PVR 287 |
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| 35 | #define PPC603e_SPR_DAR 19 |
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| 36 | #define PPC603e_SPR_SPRG0 272 |
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| 37 | #define PPC603e_SPR_SPRG1 273 |
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| 38 | #define PPC603e_SPR_SPRG2 274 |
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| 39 | #define PPC603e_SPR_SPRG3 275 |
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| 40 | #define PPC603e_SPR_DSISR 18 |
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| 41 | #define PPC603e_SPR_SRR0 26 |
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| 42 | #define PPC603e_SPR_SRR1 27 |
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| 43 | #define PPC603e_SPR_TBL_WRITE 284 |
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| 44 | #define PPC603e_SPR_TBU_WRITE 285 |
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| 45 | #define PPC603e_SPR_DEC 22 |
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| 46 | #define PPC603e_SPR_IABR 1010 |
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| 47 | #define PPC603e_SPR_EAR 282 |
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| 48 | |
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| 49 | |
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| 50 | |
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| 51 | #define PCI_MEM_CMD (SCORE603E_PCI_MEM_BASE >> 16) |
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| 52 | |
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| 53 | |
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| 54 | typedef struct { |
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[dac4208] | 55 | uint32_t counter_1_100; |
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| 56 | uint32_t counter_hours; |
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| 57 | uint32_t counter_min; |
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| 58 | uint32_t counter_sec; |
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| 59 | uint32_t counter_month; |
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| 60 | uint32_t counter_date; |
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| 61 | uint32_t counter_year; |
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| 62 | uint32_t counter_day_of_week; |
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| 63 | |
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| 64 | uint32_t RAM_1_100; |
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| 65 | uint32_t RAM_hours; |
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| 66 | uint32_t RAM_month; |
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| 67 | uint32_t RAM_date; |
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| 68 | uint32_t RAM_year; |
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| 69 | uint32_t RAM_day_of_week; |
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| 70 | |
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| 71 | uint32_t interupt_status_mask; |
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| 72 | uint32_t command_register; |
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[9c448e1] | 73 | }Harris_RTC; |
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| 74 | |
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| 75 | void init_RTC() |
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| 76 | { |
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| 77 | volatile Harris_RTC *the_RTC; |
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| 78 | |
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| 79 | the_RTC = (volatile Harris_RTC *)SCORE603E_RTC_ADDRESS; |
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| 80 | |
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| 81 | the_RTC->command_register = 0x0; |
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| 82 | } |
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| 83 | |
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| 84 | void init_PCI() |
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| 85 | { |
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[c819ea4] | 86 | #if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE) |
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[dac4208] | 87 | uint32_t value; |
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[9c448e1] | 88 | |
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| 89 | /* |
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| 90 | * NOTE: Accessing any memory location not mapped by the BAT |
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| 91 | * registers will cause a TLB miss exception. |
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| 92 | * Set the DBAT1 to be configured for 256M of PCI MEM |
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| 93 | * at 0xC0000000 with Write-through and Guarded Attributed and |
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| 94 | * read/write access allowed |
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| 95 | */ |
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| 96 | |
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| 97 | /* load DBAT1U (spr538) - 256Mbytes, User, Super */ |
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| 98 | value = SCORE603E_PCI_MEM_BASE | 0x1FFF; |
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| 99 | asm volatile( |
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| 100 | "isync;" |
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| 101 | "mtspr 538, %0" |
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| 102 | : "=r" (value) |
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| 103 | : "0" (value) |
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| 104 | ); |
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| 105 | |
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| 106 | /* load DBAT1L (spr539) - Write-through, Guarded and Read/Write */ |
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| 107 | value = SCORE603E_PCI_MEM_BASE | 0x0002; |
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| 108 | asm volatile ( |
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| 109 | "mtspr 539, %0;" |
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| 110 | "isync" |
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| 111 | : "=r" (value) |
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| 112 | : "0" (value) |
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| 113 | ); |
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| 114 | |
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| 115 | #elif (SCORE603E_USE_DINK) |
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| 116 | /* DINK Monitor setsup and uses all 4 BAT registers. */ |
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| 117 | /* The fourth BAT register can be modified to access this area */ |
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| 118 | |
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| 119 | #if (0) |
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| 120 | /* |
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| 121 | * NOTE: Accessing any memory location not mapped by the BAT |
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| 122 | * registers will cause a TLB miss exception. |
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| 123 | * Set the DBAT3 to be configured for 256M of PCI MEM |
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| 124 | * at 0xC0000000 with Write-through and Guarded Attributed and |
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| 125 | * read/write access allowed |
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| 126 | */ |
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| 127 | |
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| 128 | /* load DBAT3U (spr542) - 256Mbytes, User, Super */ |
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| 129 | value = SCORE603E_PCI_MEM_BASE | 0x1FFF; |
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| 130 | asm volatile( |
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| 131 | "isync;" |
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| 132 | "mtspr 542, %0" |
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| 133 | : "=r" (value) |
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| 134 | : "0" (value) |
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| 135 | ); |
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| 136 | |
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| 137 | /* load DBAT3L (spr543) - Write-through, Guarded and Read/Write */ |
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| 138 | value = SCORE603E_PCI_MEM_BASE | 0x0002; |
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| 139 | asm volatile ( |
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| 140 | "mtspr 543, %0;" |
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| 141 | "isync" |
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| 142 | : "=r" (value) |
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| 143 | : "0" (value) |
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| 144 | ); |
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| 145 | #endif |
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| 146 | |
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| 147 | #else |
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| 148 | #error "SCORE603E BSPSTART.C -- what ROM monitor are you using" |
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| 149 | #endif |
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| 150 | } |
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| 151 | |
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| 152 | #define PPC_Get_HID0( _value ) \ |
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| 153 | do { \ |
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| 154 | _value = 0; /* to avoid warnings */ \ |
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| 155 | asm volatile( \ |
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| 156 | "mfspr %0, 0x3f0;" /* get HID0 */ \ |
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| 157 | "isync" \ |
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| 158 | : "=r" (_value) \ |
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| 159 | : "0" (_value) \ |
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| 160 | ); \ |
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| 161 | } while (0) |
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| 162 | |
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| 163 | #define PPC_Set_HID0( _value ) \ |
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| 164 | do { \ |
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| 165 | asm volatile( \ |
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| 166 | "isync;" \ |
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| 167 | "mtspr 0x3f0, %0;" /* load HID0 */ \ |
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| 168 | "isync" \ |
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| 169 | : "=r" (_value) \ |
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| 170 | : "0" (_value) \ |
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| 171 | ); \ |
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| 172 | } while (0) |
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| 173 | |
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| 174 | |
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| 175 | void instruction_cache_enable () |
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| 176 | { |
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[dac4208] | 177 | uint32_t value; |
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[9c448e1] | 178 | |
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| 179 | /* |
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| 180 | * Enable the instruction cache |
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| 181 | */ |
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| 182 | |
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| 183 | PPC_Get_HID0( value ); |
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| 184 | |
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| 185 | value |= 0x00008000; /* Set ICE bit */ |
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| 186 | |
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| 187 | PPC_Set_HID0( value ); |
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| 188 | } |
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| 189 | |
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| 190 | void data_cache_enable () |
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| 191 | { |
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[dac4208] | 192 | uint32_t value; |
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[9c448e1] | 193 | |
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| 194 | /* |
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| 195 | * enable data cache |
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| 196 | */ |
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| 197 | |
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| 198 | PPC_Get_HID0( value ); |
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| 199 | |
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| 200 | value |= 0x00004000; /* set DCE bit */ |
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| 201 | |
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| 202 | PPC_Set_HID0( value ); |
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| 203 | } |
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| 204 | |
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| 213 | |
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