source: rtems/c/src/lib/libbsp/powerpc/score603e/irq/irq.h @ 7068d7ac

4.104.114.84.95
Last change on this file since 7068d7ac was 7068d7ac, checked in by Jennifer Averett <Jennifer.Averett@…>, on 05/17/05 at 15:05:03

2005-05-17 Jennifer Averett <jennifer.averett@…>

  • irq/irq.c, irq/irq.h: Modified to use rtems/irq.h.
  • Property mode set to 100644
File size: 3.8 KB
Line 
1/* irq.h
2 *
3 *  This include file describe the data structure and the functions implemented
4 *  by RTEMS to write interrupt handlers.
5 *
6 *  Copyright (C) 1999 valette@crf.canon.fr
7 *
8 *  This code is heavilly inspired by the public specification of STREAM V2
9 *  that can be found at :
10 *
11 *      <http://www.chorus.com/Documentation/index.html> by following
12 *  the STREAM API Specification Document link.
13 *
14 *  The license and distribution terms for this file may be
15 *  found in found in the file LICENSE in this distribution or at
16 *  http://www.rtems.com/license/LICENSE.
17 *
18 *  $Id$
19 */
20
21#ifndef LIBBSP_POWERPC_IRQ_H
22#define LIBBSP_POWERPC_IRQ_H
23
24#define BSP_SHARED_HANDLER_SUPPORT      1
25#include <rtems/irq.h>
26
27/*
28 * 8259 edge/level control definitions at VIA
29 */
30#define ISA8259_M_ELCR          0x4d0
31#define ISA8259_S_ELCR          0x4d1
32
33#define ELCRS_INT15_LVL         0x80
34#define ELCRS_INT14_LVL         0x40
35#define ELCRS_INT13_LVL         0x20
36#define ELCRS_INT12_LVL         0x10
37#define ELCRS_INT11_LVL         0x08
38#define ELCRS_INT10_LVL         0x04
39#define ELCRS_INT9_LVL          0x02
40#define ELCRS_INT8_LVL          0x01
41#define ELCRM_INT7_LVL          0x80
42#define ELCRM_INT6_LVL          0x40
43#define ELCRM_INT5_LVL          0x20
44#define ELCRM_INT4_LVL          0x10
45#define ELCRM_INT3_LVL          0x8
46#define ELCRM_INT2_LVL          0x4
47#define ELCRM_INT1_LVL          0x2
48#define ELCRM_INT0_LVL          0x1
49
50#define BSP_ASM_IRQ_VECTOR_BASE 0x0
51    /* PIC's command and mask registers */
52#define PIC_MASTER_COMMAND_IO_PORT              0x20    /* Master PIC command register */
53#define PIC_SLAVE_COMMAND_IO_PORT               0xa0    /* Slave PIC command register */
54#define PIC_MASTER_IMR_IO_PORT                  0x21    /* Master PIC Interrupt Mask Register */
55#define PIC_SLAVE_IMR_IO_PORT                   0xa1    /* Slave PIC Interrupt Mask Register */
56
57    /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
58#define PIC_EOSI        0x60    /* End of Specific Interrupt (EOSI) */
59#define SLAVE_PIC_EOSI  0x62    /* End of Specific Interrupt (EOSI) for cascade */
60#define PIC_EOI         0x20    /* Generic End of Interrupt (EOI) */
61
62#ifndef ASM
63
64#ifdef __cplusplus
65extern "C" {
66#endif
67
68/*
69 * Symbolic IRQ names and related definitions
70 */
71
72  /* Base vector for our ISA IRQ handlers. */
73#define BSP_ISA_IRQ_VECTOR_BASE         BSP_ASM_IRQ_VECTOR_BASE
74  /*
75   * ISA IRQ handler related definitions
76   */
77#define BSP_ISA_IRQ_NUMBER              (16)
78#define BSP_ISA_IRQ_LOWEST_OFFSET       (0)
79#define BSP_ISA_IRQ_MAX_OFFSET          (BSP_ISA_IRQ_LOWEST_OFFSET+BSP_ISA_IRQ_NUMBER-1)
80  /*
81   * PCI IRQ handlers related definitions
82   * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
83   */
84#define BSP_PCI_IRQ_NUMBER              (16)
85#define BSP_PCI_IRQ_LOWEST_OFFSET       (BSP_ISA_IRQ_NUMBER)
86#define BSP_PCI_IRQ_MAX_OFFSET          (BSP_PCI_IRQ_LOWEST_OFFSET+BSP_PCI_IRQ_NUMBER-1)
87  /*
88   * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
89   * handler might be connected
90   */
91#define BSP_PROCESSOR_IRQ_NUMBER        (1)
92#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
93#define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET+BSP_PROCESSOR_IRQ_NUMBER-1)
94  /* Misc vectors for OPENPIC irqs (IPI, timers)
95   */
96#define BSP_MISC_IRQ_NUMBER             (8)
97#define BSP_MISC_IRQ_LOWEST_OFFSET      (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
98#define BSP_MISC_IRQ_MAX_OFFSET         (BSP_MISC_IRQ_LOWEST_OFFSET+BSP_MISC_IRQ_NUMBER-1)
99  /*
100   * Summary
101   */
102#define BSP_IRQ_NUMBER                  (BSP_MISC_IRQ_MAX_OFFSET + 1)
103#define BSP_LOWEST_OFFSET               (BSP_ISA_IRQ_LOWEST_OFFSET)
104#define BSP_MAX_OFFSET                  (BSP_MISC_IRQ_MAX_OFFSET)
105    /*
106     * Some PCI IRQ symbolic name definition
107     */
108#define BSP_PCI_IRQ0                    (BSP_PCI_IRQ_LOWEST_OFFSET)
109
110    /*
111     * Some Processor execption handled as RTEMS IRQ symbolic name definition
112     */
113#define BSP_DECREMENTER                 (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
114
115#ifdef __cplusplus
116}
117#endif
118
119#endif
120
121#endif
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