1 | /* irq.h |
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2 | * |
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3 | * This include file describe the data structure and the functions implemented |
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4 | * by RTEMS to write interrupt handlers. |
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5 | * |
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6 | * Copyright (C) 1999 valette@crf.canon.fr |
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7 | * |
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8 | * This code is heavilly inspired by the public specification of STREAM V2 |
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9 | * that can be found at : |
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10 | * |
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11 | * <http://www.chorus.com/Documentation/index.html> by following |
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12 | * the STREAM API Specification Document link. |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in found in the file LICENSE in this distribution or at |
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16 | * http://www.rtems.com/license/LICENSE. |
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17 | * |
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18 | * $Id$ |
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19 | */ |
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20 | |
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21 | #ifndef LIBBSP_POWERPC_IRQ_H |
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22 | #define LIBBSP_POWERPC_IRQ_H |
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23 | |
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24 | #define BSP_SHARED_HANDLER_SUPPORT 1 |
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25 | #include <rtems/irq.h> |
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26 | |
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27 | /* |
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28 | * 8259 edge/level control definitions at VIA |
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29 | */ |
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30 | #define ISA8259_M_ELCR 0x4d0 |
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31 | #define ISA8259_S_ELCR 0x4d1 |
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32 | |
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33 | #define ELCRS_INT15_LVL 0x80 |
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34 | #define ELCRS_INT14_LVL 0x40 |
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35 | #define ELCRS_INT13_LVL 0x20 |
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36 | #define ELCRS_INT12_LVL 0x10 |
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37 | #define ELCRS_INT11_LVL 0x08 |
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38 | #define ELCRS_INT10_LVL 0x04 |
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39 | #define ELCRS_INT9_LVL 0x02 |
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40 | #define ELCRS_INT8_LVL 0x01 |
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41 | #define ELCRM_INT7_LVL 0x80 |
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42 | #define ELCRM_INT6_LVL 0x40 |
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43 | #define ELCRM_INT5_LVL 0x20 |
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44 | #define ELCRM_INT4_LVL 0x10 |
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45 | #define ELCRM_INT3_LVL 0x8 |
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46 | #define ELCRM_INT2_LVL 0x4 |
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47 | #define ELCRM_INT1_LVL 0x2 |
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48 | #define ELCRM_INT0_LVL 0x1 |
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49 | |
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50 | #define BSP_ASM_IRQ_VECTOR_BASE 0x0 |
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51 | /* PIC's command and mask registers */ |
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52 | #define PIC_MASTER_COMMAND_IO_PORT 0x20 /* Master PIC command register */ |
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53 | #define PIC_SLAVE_COMMAND_IO_PORT 0xa0 /* Slave PIC command register */ |
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54 | #define PIC_MASTER_IMR_IO_PORT 0x21 /* Master PIC Interrupt Mask Register */ |
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55 | #define PIC_SLAVE_IMR_IO_PORT 0xa1 /* Slave PIC Interrupt Mask Register */ |
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56 | |
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57 | /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */ |
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58 | #define PIC_EOSI 0x60 /* End of Specific Interrupt (EOSI) */ |
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59 | #define SLAVE_PIC_EOSI 0x62 /* End of Specific Interrupt (EOSI) for cascade */ |
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60 | #define PIC_EOI 0x20 /* Generic End of Interrupt (EOI) */ |
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61 | |
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62 | #ifndef ASM |
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63 | |
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64 | #ifdef __cplusplus |
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65 | extern "C" { |
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66 | #endif |
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67 | |
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68 | /* |
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69 | * Symbolic IRQ names and related definitions |
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70 | */ |
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71 | |
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72 | /* Base vector for our ISA IRQ handlers. */ |
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73 | #define BSP_ISA_IRQ_VECTOR_BASE BSP_ASM_IRQ_VECTOR_BASE |
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74 | /* |
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75 | * ISA IRQ handler related definitions |
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76 | */ |
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77 | #define BSP_ISA_IRQ_NUMBER (16) |
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78 | #define BSP_ISA_IRQ_LOWEST_OFFSET (0) |
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79 | #define BSP_ISA_IRQ_MAX_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET+BSP_ISA_IRQ_NUMBER-1) |
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80 | /* |
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81 | * PCI IRQ handlers related definitions |
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82 | * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE |
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83 | */ |
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84 | #define BSP_PCI_IRQ_NUMBER (16) |
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85 | #define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_ISA_IRQ_NUMBER) |
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86 | #define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET+BSP_PCI_IRQ_NUMBER-1) |
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87 | /* |
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88 | * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt |
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89 | * handler might be connected |
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90 | */ |
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91 | #define BSP_PROCESSOR_IRQ_NUMBER (1) |
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92 | #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1) |
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93 | #define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET+BSP_PROCESSOR_IRQ_NUMBER-1) |
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94 | /* Misc vectors for OPENPIC irqs (IPI, timers) |
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95 | */ |
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96 | #define BSP_MISC_IRQ_NUMBER (8) |
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97 | #define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) |
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98 | #define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET+BSP_MISC_IRQ_NUMBER-1) |
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99 | /* |
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100 | * Summary |
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101 | */ |
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102 | #define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1) |
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103 | #define BSP_LOWEST_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET) |
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104 | #define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET) |
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105 | /* |
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106 | * Some PCI IRQ symbolic name definition |
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107 | */ |
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108 | #define BSP_PCI_IRQ0 (BSP_PCI_IRQ_LOWEST_OFFSET) |
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109 | |
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110 | /* |
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111 | * Some Processor execption handled as RTEMS IRQ symbolic name definition |
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112 | */ |
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113 | #define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) |
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114 | |
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115 | #ifdef __cplusplus |
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116 | } |
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117 | #endif |
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118 | |
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119 | #endif |
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120 | |
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121 | #endif |
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