source: rtems/c/src/lib/libbsp/powerpc/score603e/irq/irq.h @ 31a5ec8

4.9
Last change on this file since 31a5ec8 was 31a5ec8, checked in by Jennifer Averett <Jennifer.Averett@…>, on May 5, 2009 at 4:18:06 PM

2009-05-05 Jennifer Averett <jennifer.averett@…>

  • Makefile.am, README, configure.ac, preinstall.am, PCI_bus/PCI.c, PCI_bus/PCI.h, PCI_bus/flash.c, PCI_bus/universe.c, console/85c30.c, console/85c30.h, console/console.c, console/consolebsp.h, console/tbl85c30.c, include/bsp.h, include/coverhd.h, include/gen2.h, include/irq-config.h, include/tm27.h, irq/FPGA.c, irq/irq.h, irq/irq_init.c, start/start.S, startup/Hwr_init.c, startup/bspstart.c, timer/timer.c, tod/tod.c: Updated and tested with the latest powerpc isr source
  • irq/no_pic.c: New file.
  • irq/irq.c, startup/genpvec.c, startup/setvec.c, startup/vmeintr.c: Removed.
  • Property mode set to 100644
File size: 4.9 KB
Line 
1/* irq.h
2 *
3 *  This include file describe the data structure and the functions implemented
4 *  by RTEMS to write interrupt handlers.
5 *
6 *  This code is heavilly inspired by the public specification of STREAM V2
7 *  that can be found at :
8 *
9 *  <http://www.chorus.com/Documentation/index.html> by following
10 *  the STREAM API Specification Document link.
11 *
12 *  COPYRIGHT (c) 1989-2009.
13 *  On-Line Applications Research Corporation (OAR).
14 *
15 *  The license and distribution terms for this file may be
16 *  found in the file LICENSE in this distribution or at
17 *  http://www.rtems.com/license/LICENSE.
18 *
19 *  $Id$
20 */
21
22#ifndef BSP_POWERPC_IRQ_H
23#define BSP_POWERPC_IRQ_H
24
25#define BSP_SHARED_HANDLER_SUPPORT      1
26#include <rtems/irq.h>
27
28#ifndef ASM
29
30#ifdef __cplusplus
31extern "C" {
32#endif
33
34
35/*
36 * rtems_irq_number Definitions
37 */
38
39/*
40 * ISA IRQ handler related definitions
41 */
42#define BSP_ISA_IRQ_NUMBER              (16)
43#define BSP_ISA_IRQ_LOWEST_OFFSET       (0)
44#define BSP_ISA_IRQ_MAX_OFFSET          (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
45
46/*
47 * PCI IRQ handlers related definitions
48 */
49#define BSP_PCI_IRQ_NUMBER              (16)
50#define BSP_PCI_IRQ_LOWEST_OFFSET       (BSP_ISA_IRQ_NUMBER)
51#define BSP_PCI_IRQ_MAX_OFFSET          (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
52
53/*
54 * PMC IRQ
55 */
56#define BSP_PMC_IRQ_NUMBER              (4)
57#define BSP_PMC_IRQ_LOWEST_OFFSET       (BSP_PCI_IRQ_MAX_OFFSET + 1)
58#define BSP_PMC_IRQ_MAX_OFFSET          (BSP_PMC_IRQ_LOWEST_OFFSET + BSP_PMC_IRQ_NUMBER - 1)
59
60
61/*
62 * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
63 * handler might be connected
64 */
65#define BSP_PROCESSOR_IRQ_NUMBER        (1)
66#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PMC_IRQ_MAX_OFFSET + 1)
67#define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
68
69/* Misc vectors for OPENPIC irqs (IPI, timers)
70 */
71#define BSP_MISC_IRQ_NUMBER             (8)
72#define BSP_MISC_IRQ_LOWEST_OFFSET      (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
73#define BSP_MISC_IRQ_MAX_OFFSET         (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1)
74/*
75 * Summary
76 */
77#define BSP_IRQ_NUMBER                  (BSP_MISC_IRQ_MAX_OFFSET + 1)
78#define BSP_LOWEST_OFFSET               (BSP_ISA_IRQ_LOWEST_OFFSET)
79#define BSP_MAX_OFFSET                  (BSP_MISC_IRQ_MAX_OFFSET)
80
81/*
82 * Some Processor execption handled as RTEMS IRQ symbolic name definition
83 */
84#define BSP_DECREMENTER                 (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
85
86/*
87 * First Score Unique IRQ
88 */
89#define Score_IRQ_First ( BSP_PCI_IRQ_LOWEST_OFFSET )
90
91/*
92 * The Following Are part of a Score603e FPGA.
93 */
94#define SCORE603E_IRQ00   ( Score_IRQ_First +  0 )
95#define SCORE603E_IRQ01   ( Score_IRQ_First +  1 )
96#define SCORE603E_IRQ02   ( Score_IRQ_First +  2 )
97#define SCORE603E_IRQ03   ( Score_IRQ_First +  3 )
98#define SCORE603E_IRQ04   ( Score_IRQ_First +  4 )
99#define SCORE603E_IRQ05   ( Score_IRQ_First +  5 )
100#define SCORE603E_IRQ06   ( Score_IRQ_First +  6 )
101#define SCORE603E_IRQ07   ( Score_IRQ_First +  7 )
102#define SCORE603E_IRQ08   ( Score_IRQ_First +  8 )
103#define SCORE603E_IRQ09   ( Score_IRQ_First +  9 )
104#define SCORE603E_IRQ10   ( Score_IRQ_First + 10 )
105#define SCORE603E_IRQ11   ( Score_IRQ_First + 11 )
106#define SCORE603E_IRQ12   ( Score_IRQ_First + 12 )
107#define SCORE603E_IRQ13   ( Score_IRQ_First + 13 )
108#define SCORE603E_IRQ14   ( Score_IRQ_First + 14 )
109#define SCORE603E_IRQ15   ( Score_IRQ_First + 15 )
110
111#define SCORE603E_TIMER1_IRQ           SCORE603E_IRQ00
112#define SCORE603E_TIMER2_IRQ           SCORE603E_IRQ01
113#define SCORE603E_TIMER3_IRQ           SCORE603E_IRQ02
114#define SCORE603E_85C30_1_IRQ          SCORE603E_IRQ03
115#define SCORE603E_85C30_0_IRQ          SCORE603E_IRQ04
116#define SCORE603E_RTC_IRQ              SCORE603E_IRQ05
117#define SCORE603E_PCI_IRQ_0            SCORE603E_IRQ06
118#define SCORE603E_PCI_IRQ_1            SCORE603E_IRQ07
119#define SCORE603E_PCI_IRQ_2            SCORE603E_IRQ08
120#define SCORE603E_PCI_IRQ_3            SCORE603E_IRQ09
121#define SCORE603E_UNIVERSE_IRQ         SCORE603E_IRQ10
122#define SCORE603E_1553_IRQ             SCORE603E_IRQ11
123#define SCORE603E_MAIL_BOX_IRQ_0       SCORE603E_IRQ12
124#define SCORE603E_MAIL_BOX_IRQ_1       SCORE603E_IRQ13
125#define SCORE603E_MAIL_BOX_IRQ_2       SCORE603E_IRQ14
126#define SCORE603E_MAIL_BOX_IRQ_3       SCORE603E_IRQ15
127
128/*
129 * The Score FPGA maps all interrupts comming from the PMC card to
130 * the FPGA interrupt SCORE603E_PCI_IRQ_0 the PMC status word must be
131 * read to indicate which interrupt was chained to the FPGA.
132 */
133#define SCORE603E_IRQ16   ( Score_IRQ_First + 16 )
134#define SCORE603E_IRQ17   ( Score_IRQ_First + 17 )
135#define SCORE603E_IRQ18   ( Score_IRQ_First + 18 )
136#define SCORE603E_IRQ19   ( Score_IRQ_First + 19 )
137
138/*
139 * IRQ'a read from the PMC card
140 */
141#define SCORE603E_85C30_4_IRQ          SCORE603E_IRQ16    /* SCC 422-1 */
142#define SCORE603E_85C30_2_IRQ          SCORE603E_IRQ17    /* SCC 232-1 */
143#define SCORE603E_85C30_5_IRQ          SCORE603E_IRQ18    /* SCC 422-2 */
144#define SCORE603E_85C30_3_IRQ          SCORE603E_IRQ19    /* SCC 232-2 */
145
146#define MAX_BOARD_IRQS                 SCORE603E_IRQ19
147
148#ifdef __cplusplus
149}
150#endif
151
152#endif
153#endif
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