[2608c9a9] | 1 | /* irq.h |
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| 2 | * |
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| 3 | * This include file describe the data structure and the functions implemented |
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| 4 | * by RTEMS to write interrupt handlers. |
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| 5 | * |
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| 6 | * This code is heavilly inspired by the public specification of STREAM V2 |
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| 7 | * that can be found at : |
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| 8 | * |
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[31a5ec8] | 9 | * <http://www.chorus.com/Documentation/index.html> by following |
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[2608c9a9] | 10 | * the STREAM API Specification Document link. |
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| 11 | * |
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[31a5ec8] | 12 | * COPYRIGHT (c) 1989-2009. |
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| 13 | * On-Line Applications Research Corporation (OAR). |
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| 14 | * |
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[2608c9a9] | 15 | * The license and distribution terms for this file may be |
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[31a5ec8] | 16 | * found in the file LICENSE in this distribution or at |
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[2608c9a9] | 17 | * http://www.rtems.com/license/LICENSE. |
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| 18 | * |
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| 19 | * $Id$ |
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| 20 | */ |
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| 21 | |
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[40e7ae2] | 22 | #ifndef BSP_POWERPC_IRQ_H |
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| 23 | #define BSP_POWERPC_IRQ_H |
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[7068d7ac] | 24 | |
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| 25 | #define BSP_SHARED_HANDLER_SUPPORT 1 |
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| 26 | #include <rtems/irq.h> |
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[2608c9a9] | 27 | |
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| 28 | #ifndef ASM |
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| 29 | |
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| 30 | #ifdef __cplusplus |
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| 31 | extern "C" { |
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| 32 | #endif |
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| 33 | |
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[31a5ec8] | 34 | |
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[2608c9a9] | 35 | /* |
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[40e7ae2] | 36 | * rtems_irq_number Definitions |
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[2608c9a9] | 37 | */ |
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| 38 | |
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[40e7ae2] | 39 | /* |
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| 40 | * ISA IRQ handler related definitions |
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| 41 | */ |
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[7068d7ac] | 42 | #define BSP_ISA_IRQ_NUMBER (16) |
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| 43 | #define BSP_ISA_IRQ_LOWEST_OFFSET (0) |
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[40e7ae2] | 44 | #define BSP_ISA_IRQ_MAX_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1) |
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[31a5ec8] | 45 | |
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[40e7ae2] | 46 | /* |
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| 47 | * PCI IRQ handlers related definitions |
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| 48 | */ |
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[7068d7ac] | 49 | #define BSP_PCI_IRQ_NUMBER (16) |
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| 50 | #define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_ISA_IRQ_NUMBER) |
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[40e7ae2] | 51 | #define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1) |
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[31a5ec8] | 52 | |
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| 53 | /* |
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| 54 | * PMC IRQ |
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| 55 | */ |
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| 56 | #define BSP_PMC_IRQ_NUMBER (4) |
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| 57 | #define BSP_PMC_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1) |
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| 58 | #define BSP_PMC_IRQ_MAX_OFFSET (BSP_PMC_IRQ_LOWEST_OFFSET + BSP_PMC_IRQ_NUMBER - 1) |
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| 59 | |
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| 60 | |
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[40e7ae2] | 61 | /* |
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| 62 | * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt |
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| 63 | * handler might be connected |
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| 64 | */ |
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[7068d7ac] | 65 | #define BSP_PROCESSOR_IRQ_NUMBER (1) |
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[31a5ec8] | 66 | #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PMC_IRQ_MAX_OFFSET + 1) |
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[40e7ae2] | 67 | #define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) |
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[31a5ec8] | 68 | |
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[40e7ae2] | 69 | /* Misc vectors for OPENPIC irqs (IPI, timers) |
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| 70 | */ |
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[7068d7ac] | 71 | #define BSP_MISC_IRQ_NUMBER (8) |
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| 72 | #define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) |
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[40e7ae2] | 73 | #define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1) |
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| 74 | /* |
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| 75 | * Summary |
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| 76 | */ |
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[7068d7ac] | 77 | #define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1) |
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| 78 | #define BSP_LOWEST_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET) |
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[40e7ae2] | 79 | #define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET) |
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[2608c9a9] | 80 | |
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[40e7ae2] | 81 | /* |
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| 82 | * Some Processor execption handled as RTEMS IRQ symbolic name definition |
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| 83 | */ |
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[7068d7ac] | 84 | #define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET) |
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[2608c9a9] | 85 | |
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[40e7ae2] | 86 | /* |
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[31a5ec8] | 87 | * First Score Unique IRQ |
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[40e7ae2] | 88 | */ |
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[31a5ec8] | 89 | #define Score_IRQ_First ( BSP_PCI_IRQ_LOWEST_OFFSET ) |
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[40e7ae2] | 90 | |
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| 91 | /* |
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[31a5ec8] | 92 | * The Following Are part of a Score603e FPGA. |
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| 93 | */ |
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| 94 | #define SCORE603E_IRQ00 ( Score_IRQ_First + 0 ) |
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| 95 | #define SCORE603E_IRQ01 ( Score_IRQ_First + 1 ) |
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| 96 | #define SCORE603E_IRQ02 ( Score_IRQ_First + 2 ) |
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| 97 | #define SCORE603E_IRQ03 ( Score_IRQ_First + 3 ) |
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| 98 | #define SCORE603E_IRQ04 ( Score_IRQ_First + 4 ) |
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| 99 | #define SCORE603E_IRQ05 ( Score_IRQ_First + 5 ) |
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| 100 | #define SCORE603E_IRQ06 ( Score_IRQ_First + 6 ) |
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| 101 | #define SCORE603E_IRQ07 ( Score_IRQ_First + 7 ) |
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| 102 | #define SCORE603E_IRQ08 ( Score_IRQ_First + 8 ) |
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| 103 | #define SCORE603E_IRQ09 ( Score_IRQ_First + 9 ) |
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| 104 | #define SCORE603E_IRQ10 ( Score_IRQ_First + 10 ) |
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| 105 | #define SCORE603E_IRQ11 ( Score_IRQ_First + 11 ) |
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| 106 | #define SCORE603E_IRQ12 ( Score_IRQ_First + 12 ) |
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| 107 | #define SCORE603E_IRQ13 ( Score_IRQ_First + 13 ) |
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| 108 | #define SCORE603E_IRQ14 ( Score_IRQ_First + 14 ) |
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| 109 | #define SCORE603E_IRQ15 ( Score_IRQ_First + 15 ) |
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| 110 | |
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| 111 | #define SCORE603E_TIMER1_IRQ SCORE603E_IRQ00 |
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| 112 | #define SCORE603E_TIMER2_IRQ SCORE603E_IRQ01 |
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| 113 | #define SCORE603E_TIMER3_IRQ SCORE603E_IRQ02 |
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| 114 | #define SCORE603E_85C30_1_IRQ SCORE603E_IRQ03 |
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| 115 | #define SCORE603E_85C30_0_IRQ SCORE603E_IRQ04 |
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| 116 | #define SCORE603E_RTC_IRQ SCORE603E_IRQ05 |
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| 117 | #define SCORE603E_PCI_IRQ_0 SCORE603E_IRQ06 |
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| 118 | #define SCORE603E_PCI_IRQ_1 SCORE603E_IRQ07 |
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| 119 | #define SCORE603E_PCI_IRQ_2 SCORE603E_IRQ08 |
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| 120 | #define SCORE603E_PCI_IRQ_3 SCORE603E_IRQ09 |
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| 121 | #define SCORE603E_UNIVERSE_IRQ SCORE603E_IRQ10 |
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| 122 | #define SCORE603E_1553_IRQ SCORE603E_IRQ11 |
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| 123 | #define SCORE603E_MAIL_BOX_IRQ_0 SCORE603E_IRQ12 |
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| 124 | #define SCORE603E_MAIL_BOX_IRQ_1 SCORE603E_IRQ13 |
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| 125 | #define SCORE603E_MAIL_BOX_IRQ_2 SCORE603E_IRQ14 |
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| 126 | #define SCORE603E_MAIL_BOX_IRQ_3 SCORE603E_IRQ15 |
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[40e7ae2] | 127 | |
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| 128 | /* |
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[31a5ec8] | 129 | * The Score FPGA maps all interrupts comming from the PMC card to |
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| 130 | * the FPGA interrupt SCORE603E_PCI_IRQ_0 the PMC status word must be |
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| 131 | * read to indicate which interrupt was chained to the FPGA. |
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[40e7ae2] | 132 | */ |
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[31a5ec8] | 133 | #define SCORE603E_IRQ16 ( Score_IRQ_First + 16 ) |
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| 134 | #define SCORE603E_IRQ17 ( Score_IRQ_First + 17 ) |
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| 135 | #define SCORE603E_IRQ18 ( Score_IRQ_First + 18 ) |
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| 136 | #define SCORE603E_IRQ19 ( Score_IRQ_First + 19 ) |
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| 137 | |
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[40e7ae2] | 138 | /* |
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[31a5ec8] | 139 | * IRQ'a read from the PMC card |
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[40e7ae2] | 140 | */ |
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[31a5ec8] | 141 | #define SCORE603E_85C30_4_IRQ SCORE603E_IRQ16 /* SCC 422-1 */ |
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| 142 | #define SCORE603E_85C30_2_IRQ SCORE603E_IRQ17 /* SCC 232-1 */ |
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| 143 | #define SCORE603E_85C30_5_IRQ SCORE603E_IRQ18 /* SCC 422-2 */ |
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| 144 | #define SCORE603E_85C30_3_IRQ SCORE603E_IRQ19 /* SCC 232-2 */ |
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[40e7ae2] | 145 | |
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[31a5ec8] | 146 | #define MAX_BOARD_IRQS SCORE603E_IRQ19 |
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[40e7ae2] | 147 | |
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[2608c9a9] | 148 | #ifdef __cplusplus |
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[31a5ec8] | 149 | } |
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[2608c9a9] | 150 | #endif |
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| 151 | |
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| 152 | #endif |
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| 153 | #endif |
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