source: rtems/c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c @ 31a5ec8

4.9
Last change on this file since 31a5ec8 was 31a5ec8, checked in by Jennifer Averett <Jennifer.Averett@…>, on May 5, 2009 at 4:18:06 PM

2009-05-05 Jennifer Averett <jennifer.averett@…>

  • Makefile.am, README, configure.ac, preinstall.am, PCI_bus/PCI.c, PCI_bus/PCI.h, PCI_bus/flash.c, PCI_bus/universe.c, console/85c30.c, console/85c30.h, console/console.c, console/consolebsp.h, console/tbl85c30.c, include/bsp.h, include/coverhd.h, include/gen2.h, include/irq-config.h, include/tm27.h, irq/FPGA.c, irq/irq.h, irq/irq_init.c, start/start.S, startup/Hwr_init.c, startup/bspstart.c, timer/timer.c, tod/tod.c: Updated and tested with the latest powerpc isr source
  • irq/no_pic.c: New file.
  • irq/irq.c, startup/genpvec.c, startup/setvec.c, startup/vmeintr.c: Removed.
  • Property mode set to 100644
File size: 3.3 KB
Line 
1/*  FPGA.c -- Bridge for second and subsequent generations
2 *
3 *  COPYRIGHT (c) 1989-2009.
4 *  On-Line Applications Research Corporation (OAR).
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.rtems.com/license/LICENSE.
9 *
10 *  $Id$
11 */
12
13#include <bsp.h>
14#include <bsp/irq.h>
15#include <string.h>
16#include <fcntl.h>
17#include <assert.h>
18
19#include <rtems/libio.h>
20#include <rtems/libcsupport.h>
21#include <rtems/bspIo.h>
22
23/*
24 *  initialize FPGA
25 */
26void initialize_PCI_bridge (void)
27{
28  /* Note: Accept DINKs setup of the PCI Bridge and don't
29   *       change anything.
30   */
31}
32
33void set_irq_mask(
34  uint16_t         value
35)
36{
37  volatile uint16_t   *loc;
38
39  loc = (uint16_t*)SCORE603E_FPGA_MASK_DATA;
40
41  *loc = value;
42}
43
44uint16_t         get_irq_mask(voi)
45{
46  volatile uint16_t  *loc;
47  uint16_t            value;
48
49  loc =  (uint16_t*)SCORE603E_FPGA_MASK_DATA;
50
51  value = *loc;
52
53  return value;
54}
55
56void mask_irq(
57  uint16_t         irq_idx
58)
59{
60  uint16_t         value;
61  uint32_t         mask_idx = irq_idx;
62
63  value = get_irq_mask();
64
65#if (HAS_PMC_PSC8)
66  switch (irq_idx + Score_IRQ_First ) {
67    case SCORE603E_85C30_4_IRQ:
68    case SCORE603E_85C30_2_IRQ:
69    case SCORE603E_85C30_5_IRQ:
70    case SCORE603E_85C30_3_IRQ:
71      mask_idx = SCORE603E_PCI_IRQ_0 - Score_IRQ_First;
72      break;
73    default:
74      break;
75  }
76#endif
77
78  value |= (0x1 << mask_idx);
79  set_irq_mask( value );
80}
81
82void unmask_irq(
83  uint16_t         irq_idx
84)
85{
86  uint16_t         value;
87  uint32_t         mask_idx = irq_idx;
88
89  value = get_irq_mask();
90
91#if (HAS_PMC_PSC8)
92  switch (irq_idx + Score_IRQ_First ) {
93    case SCORE603E_85C30_4_IRQ:
94    case SCORE603E_85C30_2_IRQ:
95    case SCORE603E_85C30_5_IRQ:
96    case SCORE603E_85C30_3_IRQ:
97      mask_idx = SCORE603E_PCI_IRQ_0 - Score_IRQ_First;
98      break;
99    default:
100      break;
101  }
102#endif
103
104  value &= (~(0x1 << mask_idx));
105  set_irq_mask( value );
106}
107
108void init_irq_data_register(void)
109{
110  uint32_t         index;
111  uint32_t         i;
112
113  set_irq_mask( 0xffff );
114
115  /*
116   * Clear any existing interupts from the vector data register.
117   */
118  for (i=0; i<20; i++) {
119    index =  (*SCORE603E_FPGA_VECT_DATA);
120    if ( (index&0x10) != 0x10 )
121      break;
122  }
123}
124
125uint16_t         read_and_clear_PMC_irq(
126  uint16_t            irq
127)
128{
129  uint16_t   status_word = irq;
130
131  status_word = (*BSP_PMC_STATUS_ADDRESS);
132
133  return status_word;
134}
135
136bool Is_PMC_IRQ(
137  uint32_t           pmc_irq,
138  uint16_t           status_word
139)
140{
141  bool result = false;
142
143  switch(pmc_irq) {
144    case SCORE603E_85C30_4_IRQ:
145      result = Is_PMC_85C30_4_IRQ( status_word ) ? true : false;
146      break;
147    case SCORE603E_85C30_2_IRQ:
148      result = Is_PMC_85C30_2_IRQ( status_word ) ? true : false;
149      break;
150    case SCORE603E_85C30_5_IRQ:
151      result = Is_PMC_85C30_5_IRQ( status_word ) ? true : false;
152      break;
153    case SCORE603E_85C30_3_IRQ:
154      result = Is_PMC_85C30_3_IRQ( status_word ) ? true : false;
155      break;
156    default:
157      assert( 0 );
158      break;
159  }
160
161  return result;
162}
163
164uint16_t         read_and_clear_irq(void)
165{
166  uint16_t            irq;
167
168
169  irq = (*SCORE603E_FPGA_VECT_DATA);
170  Processor_Synchronize();
171  if ((irq & 0xffff0) != 0x10) {
172    printk( "read_and_clear_irq:: ERROR==>no irq data 0x%x\n", irq);
173    return (irq | 0x80);
174  }
175
176  irq &=0xf;
177  irq += Score_IRQ_First;
178  return irq;
179}
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