source: rtems/c/src/lib/libbsp/powerpc/score603e/include/gen2.h @ f05b2ac

4.104.114.84.95
Last change on this file since f05b2ac was f05b2ac, checked in by Ralf Corsepius <ralf.corsepius@…>, on 04/21/04 at 16:01:48

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1/*  Gen2.h
2 *
3 *  This include file contains all Generation 2 board addreses
4 *
5 *  COPYRIGHT (c) 1989-1997.
6 *  On-Line Applications Research Corporation (OAR).
7 *
8 *  The license and distribution terms for this file may in
9 *  the file LICENSE in this distribution or at
10 *  http://www.rtems.com/license/LICENSE.
11 *
12 *  $Id:
13 */
14
15#ifndef __SCORE_GENERATION_2_h
16#define __SCORE_GENERATION_2_h
17
18#ifdef __cplusplus
19extern "C" {
20#endif
21
22#include <rtems.h>
23
24/*
25 * ISA/PCI I/O space.
26 */
27#define SCORE603E_VME_JUMPER_ADDR      0x00e20000
28#define SCORE603E_FLASH_BASE_ADDR      0x04000000
29#define SCORE603E_ISA_PCI_IO_BASE      0x80000000
30#define SCORE603E_TIMER_PORT_C         0xfd000000
31#define SCORE603E_TIMER_INT_ACK        0xfd000000
32#define SCORE603E_TIMER_PORT_B         0xfd000008
33#define SCORE603E_TIMER_PORT_A         0xfd000004
34
35#define SCORE603E_BOARD_CTRL_REG       ((volatile uint8_t*)0xfd00002c)
36#define SCORE603E_BRD_FLASH_DISABLE_MASK     0x40
37
38#define SCORE603E_85C30_CTRL_0         ((volatile uint8_t*)0xfe200020)
39#define SCORE603E_85C30_DATA_0         ((volatile uint8_t*)0xfe200024)
40#define SCORE603E_85C30_CTRL_1         ((volatile uint8_t*)0xfe200028)
41#define SCORE603E_85C30_DATA_1         ((volatile uint8_t*)0xfe20002c)
42#define SCORE603E_85C30_CTRL_2         ((volatile uint8_t*)0xfe200000)
43#define SCORE603E_85C30_DATA_2         ((volatile uint8_t*)0xfe200004)
44#define SCORE603E_85C30_CTRL_3         ((volatile uint8_t*)0xfe200008)
45#define SCORE603E_85C30_DATA_3         ((volatile uint8_t*)0xfe20000c)
46
47/*
48 * PSC8 - PMC Card
49 */
50#define SCORE603E_PCI_CONFIGURATION_BASE   0x80800000
51#define SCORE603E_PMC_BASE                 SCORE603E_PCI_CONFIGURATION_BASE
52#define SCORE603E_PCI_PMC_DEVICE_BASE      0x80808000
53
54#define SCORE603E_PCI_REGISTER_BASE        0xfc000000
55
56#define SCORE603E_PCI_DEVICE_ADDRESS( _offset) \
57         ((volatile uint32_t*)( SCORE603E_PCI_PMC_DEVICE_BASE + _offset ))
58
59#define SCORE603E_PMC_SERIAL_ADDRESS( _offset )    \
60        ((volatile uint8_t*)(SCORE603E_PCI_REGISTER_BASE + _offset))
61
62/*
63 * PMC serial channels - (4-7: 232 and 8-11: 422)
64 */
65#define SCORE603E_85C30_CTRL_4        SCORE603E_PMC_SERIAL_ADDRESS(0x200020)
66#define SCORE603E_85C30_DATA_4        SCORE603E_PMC_SERIAL_ADDRESS(0x200024)
67#define SCORE603E_85C30_CTRL_5        SCORE603E_PMC_SERIAL_ADDRESS(0x200028)
68#define SCORE603E_85C30_DATA_5        SCORE603E_PMC_SERIAL_ADDRESS(0x20002c)
69#define SCORE603E_85C30_CTRL_6        SCORE603E_PMC_SERIAL_ADDRESS(0x200030)
70#define SCORE603E_85C30_DATA_6        SCORE603E_PMC_SERIAL_ADDRESS(0x200034)
71#define SCORE603E_85C30_CTRL_7        SCORE603E_PMC_SERIAL_ADDRESS(0x200038)
72#define SCORE603E_85C30_DATA_7        SCORE603E_PMC_SERIAL_ADDRESS(0x20003c)
73#define SCORE603E_85C30_CTRL_8        SCORE603E_PMC_SERIAL_ADDRESS(0x200000)
74#define SCORE603E_85C30_DATA_8        SCORE603E_PMC_SERIAL_ADDRESS(0x200004)
75#define SCORE603E_85C30_CTRL_9        SCORE603E_PMC_SERIAL_ADDRESS(0x200008)
76#define SCORE603E_85C30_DATA_9        SCORE603E_PMC_SERIAL_ADDRESS(0x20000c)
77#define SCORE603E_85C30_CTRL_10       SCORE603E_PMC_SERIAL_ADDRESS(0x200010)
78#define SCORE603E_85C30_DATA_10       SCORE603E_PMC_SERIAL_ADDRESS(0x200014)
79#define SCORE603E_85C30_CTRL_11       SCORE603E_PMC_SERIAL_ADDRESS(0x200018)
80#define SCORE603E_85C30_DATA_11       SCORE603E_PMC_SERIAL_ADDRESS(0x20001c)
81
82#define SCORE603E_PCI_IO_CFG_ADDR      0x80000cf8
83#define SCORE603E_PCI_IO_CFG_DATA      0x80000cfc
84
85#define SCORE603E_UNIVERSE_BASE        0x80030000
86#define SCORE603E_IO_VME_UNIVERSE_BASE 0x80007000
87#define SCORE603E_PCI_MEM_BASE         0xc0000000
88#define SCORE603E_NVRAM_BASE           0xfd100000
89#define SCORE603E_RTC_ADDRESS          ((volatile unsigned char *)0xfd180000)
90#define SCORE603E_JP1_JP2_PROM_BASE    0xfff00000
91#define SCORE603E_NOT_JP1_2_FLASH_BASE 0xff800000
92
93#if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE)
94#define SCORE603E_VME_A16_OFFSET       0x04000000
95#elif (SCORE603E_USE_DINK)
96#define SCORE603E_VME_A16_OFFSET       0x11000000
97#define SCORE603E_VME_A24_OFFSET       0x10000000
98#define SCORE603E_VME_A24_BASE         (SCORE603E_PCI_MEM_BASE+SCORE603E_VME_A24_OFFSET)
99#else
100#error "SCORE603E gen2.h -- what ROM monitor are you using"
101#endif
102
103#define SCORE603E_VME_A16_BASE         (SCORE603E_PCI_MEM_BASE+SCORE603E_VME_A16_OFFSET)
104
105/*
106 *  Definations for the ICM 1770 RTC chip
107 */
108    /*
109     * These values are programed into a register and must not be changed.
110     */
111#define ICM1770_CRYSTAL_FREQ_32K      0x00
112#define ICM1770_CRYSTAL_FREQ_1M       0x01
113#define ICM1770_CRYSTAL_FREQ_2M       0x02
114#define ICM1770_CRYSTAL_FREQ_4M       0x03
115
116#define SCORE_RTC_FREQUENCY           ICM1770_CRYSTAL_FREQ_32K
117
118/*
119 *  Z85C30 Definations for the 423 interface.
120 */
121#define SCORE603E_85C30_0_CLOCK     14745600  /* 10,000,000 ?10->14.5 */
122#define SCORE603E_85C30_0_CLOCK_X       16
123
124/*
125 *  Z85C30 Definations for the 422 interface.
126 */
127#define SCORE603E_85C30_1_CLOCK     16000000  /* 10,000,000 ?10->14.5 */
128#define SCORE603E_85C30_1_CLOCK_X       16
129
130/*
131 *  Z85C30 Definations for the PMC serial chips
132 */
133#define SCORE603E_85C30_PMC_CLOCK     16000000  /* 10,000,000 ?10->14.5 */
134#define SCORE603E_85C30_PMC_CLOCK_X       16
135
136#define SCORE603E_85C30_2_CLOCK       SCORE603E_85C30_PMC_CLOCK
137#define SCORE603E_85C30_3_CLOCK       SCORE603E_85C30_PMC_CLOCK
138#define SCORE603E_85C30_4_CLOCK       SCORE603E_85C30_PMC_CLOCK
139#define SCORE603E_85C30_5_CLOCK       SCORE603E_85C30_PMC_CLOCK
140#define SCORE603E_85C30_2_CLOCK_X     SCORE603E_85C30_PMC_CLOCK_X
141#define SCORE603E_85C30_3_CLOCK_X     SCORE603E_85C30_PMC_CLOCK_X
142#define SCORE603E_85C30_4_CLOCK_X     SCORE603E_85C30_PMC_CLOCK_X
143#define SCORE603E_85C30_5_CLOCK_X     SCORE603E_85C30_PMC_CLOCK_X
144
145#define SCORE603E_UNIVERSE_CHIP_ID     0x000010E3
146
147/*
148 * FPGA Interupt Address Definations.
149 */
150#define SCORE603E_FPGA_VECT_DATA    ((volatile uint16_t*)0xfd000040)
151#define SCORE603E_FPGA_BIT1_15_0    ((volatile uint16_t*)0xfd000044)
152#define SCORE603E_FPGA_MASK_DATA    ((volatile uint16_t*)0xfd000048)
153#define SCORE603E_FPGA_IRQ_INPUT    ((volatile uint16_t*)0xfd00004c)
154
155/*
156 * The PMC status word is at the PMC base address
157 */
158#define SCORE603E_PMC_STATUS_ADDRESS  (SCORE603E_PMC_SERIAL_ADDRESS (0))
159#define Is_PMC_85C30_4_IRQ( _status ) (_status & 0x80)    /* SCC 422-1 */
160#define Is_PMC_85C30_2_IRQ( _status ) (_status & 0x40)    /* SCC 232-1 */
161#define Is_PMC_85C30_5_IRQ( _status ) (_status & 0x20)    /* SCC 422-2 */
162#define Is_PMC_85C30_3_IRQ( _status ) (_status & 0x08)    /* SCC 232-2 */
163
164#define SCORE603E_PMC_CONTROL_ADDRESS    SCORE603E_PMC_SERIAL_ADDRESS(0x100000)
165#define SCORE603E_PMC_SCC_232_LOOPBACK (_word) (_word|0x20)
166
167#define PMC_SET_232_LOOPBACK(_word)   (_word | 0x02)
168#define PMC_CLEAR_232_LOOPBACK(_word) (_word & 0xfd)
169#define PMC_SET_422_LOOPBACK(_word)   (_word | 0x01)
170#define PMC_CLEAR_422_LOOPBACK(_word) (_word & 0xfe)
171
172/*
173 *  Score603e Interupt Definations.
174 */
175
176/*
177 * First Score Unique IRQ
178 */
179#define Score_IRQ_First ( PPC_IRQ_LAST +  1 )
180
181/*
182 * The Following Are part of a Score603e FPGA.
183 */
184#define SCORE603E_IRQ00   ( Score_IRQ_First +  0 )
185#define SCORE603E_IRQ01   ( Score_IRQ_First +  1 )
186#define SCORE603E_IRQ02   ( Score_IRQ_First +  2 )
187#define SCORE603E_IRQ03   ( Score_IRQ_First +  3 )
188#define SCORE603E_IRQ04   ( Score_IRQ_First +  4 )
189#define SCORE603E_IRQ05   ( Score_IRQ_First +  5 )
190#define SCORE603E_IRQ06   ( Score_IRQ_First +  6 )
191#define SCORE603E_IRQ07   ( Score_IRQ_First +  7 )
192#define SCORE603E_IRQ08   ( Score_IRQ_First +  8 )
193#define SCORE603E_IRQ09   ( Score_IRQ_First +  9 )
194#define SCORE603E_IRQ10   ( Score_IRQ_First + 10 )
195#define SCORE603E_IRQ11   ( Score_IRQ_First + 11 )
196#define SCORE603E_IRQ12   ( Score_IRQ_First + 12 )
197#define SCORE603E_IRQ13   ( Score_IRQ_First + 13 )
198#define SCORE603E_IRQ14   ( Score_IRQ_First + 14 )
199#define SCORE603E_IRQ15   ( Score_IRQ_First + 15 )
200
201#define SCORE603E_TIMER1_IRQ           SCORE603E_IRQ00
202#define SCORE603E_TIMER2_IRQ           SCORE603E_IRQ01
203#define SCORE603E_TIMER3_IRQ           SCORE603E_IRQ02
204#define SCORE603E_85C30_1_IRQ          SCORE603E_IRQ03
205#define SCORE603E_85C30_0_IRQ          SCORE603E_IRQ04
206#define SCORE603E_RTC_IRQ              SCORE603E_IRQ05
207#define SCORE603E_PCI_IRQ_0            SCORE603E_IRQ06
208#define SCORE603E_PCI_IRQ_1            SCORE603E_IRQ07
209#define SCORE603E_PCI_IRQ_2            SCORE603E_IRQ08
210#define SCORE603E_PCI_IRQ_3            SCORE603E_IRQ09
211#define SCORE603E_UNIVERSE_IRQ         SCORE603E_IRQ10
212#define SCORE603E_1553_IRQ             SCORE603E_IRQ11
213#define SCORE603E_MAIL_BOX_IRQ_0       SCORE603E_IRQ12
214#define SCORE603E_MAIL_BOX_IRQ_1       SCORE603E_IRQ13
215#define SCORE603E_MAIL_BOX_IRQ_2       SCORE603E_IRQ14
216#define SCORE603E_MAIL_BOX_IRQ_3       SCORE603E_IRQ15
217
218/*
219 * The Score FPGA maps all interrupts comming from the PMC card to
220 * the FPGA interrupt SCORE603E_PCI_IRQ_0 the PMC status word must be
221 * read to indicate which interrupt was chained to the FPGA.
222 */
223#define SCORE603E_IRQ16   ( Score_IRQ_First + 16 )
224#define SCORE603E_IRQ17   ( Score_IRQ_First + 17 )
225#define SCORE603E_IRQ18   ( Score_IRQ_First + 18 )
226#define SCORE603E_IRQ19   ( Score_IRQ_First + 19 )
227
228/*
229 * IRQ'a read from the PMC card
230 */
231#define SCORE603E_85C30_4_IRQ          SCORE603E_IRQ16    /* SCC 422-1 */
232#define SCORE603E_85C30_2_IRQ          SCORE603E_IRQ17    /* SCC 232-1 */
233#define SCORE603E_85C30_5_IRQ          SCORE603E_IRQ18    /* SCC 422-2 */
234#define SCORE603E_85C30_3_IRQ          SCORE603E_IRQ19    /* SCC 232-2 */
235
236#define MAX_BOARD_IRQS                 SCORE603E_IRQ19
237
238/*
239 *  BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID for the shared timer
240 *  driver.
241 */
242
243#define BSP_TIMER_AVG_OVERHEAD   4  /* It typically takes xx clicks        */
244                                    /*     to start/stop the timer.        */
245#define BSP_TIMER_LEAST_VALID    1  /* Don't trust a value lower than this */
246
247/*
248 *  Convert decrement value to tenths of microsecnds (used by
249 *  shared timer driver).
250 *
251 *    + CPU has a 66.67 Mhz bus,
252 *    + There are 4 bus cycles per click
253 *    + We return value in 1/10 microsecond units.
254 *   Modified following equation to integer equation to remove
255 *   floating point math.
256 *   (int) ((float)(_value) / ((66.67 * 0.1) / 4.0))
257 */
258
259#define BSP_Convert_decrementer( _value ) \
260  (int) (((_value) * 4000) / 6667)
261
262#endif
263
264#ifdef __cplusplus
265}
266#endif
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