source: rtems/c/src/lib/libbsp/powerpc/score603e/include/gen2.h @ 6128a4a

4.104.114.84.95
Last change on this file since 6128a4a was 6128a4a, checked in by Ralf Corsepius <ralf.corsepius@…>, on 04/21/04 at 10:43:04

Remove stray white spaces.
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1/*  Gen2.h
2 *
3 *  This include file contains all Generation 2 board addreses
4 *
5 *  COPYRIGHT (c) 1989-1997.
6 *  On-Line Applications Research Corporation (OAR).
7 *
8 *  The license and distribution terms for this file may in
9 *  the file LICENSE in this distribution or at
10 *  http://www.rtems.com/license/LICENSE.
11 *
12 *  $Id:
13 */
14
15#ifndef __SCORE_GENERATION_2_h
16#define __SCORE_GENERATION_2_h
17
18#ifdef __cplusplus
19extern "C" {
20#endif
21
22#include <rtems.h>
23
24/*
25 * ISA/PCI I/O space.
26 */
27#define SCORE603E_VME_JUMPER_ADDR      0x00e20000
28#define SCORE603E_FLASH_BASE_ADDR      0x04000000
29#define SCORE603E_ISA_PCI_IO_BASE      0x80000000
30#define SCORE603E_TIMER_PORT_C         0xfd000000
31#define SCORE603E_TIMER_INT_ACK        0xfd000000
32#define SCORE603E_TIMER_PORT_B         0xfd000008
33#define SCORE603E_TIMER_PORT_A         0xfd000004
34
35#define SCORE603E_BOARD_CTRL_REG       ((volatile uint8_t*)0xfd00002c)
36#define SCORE603E_BRD_FLASH_DISABLE_MASK     0x40
37
38#define SCORE603E_85C30_CTRL_0         ((volatile uint8_t*)0xfe200020)
39#define SCORE603E_85C30_DATA_0         ((volatile uint8_t*)0xfe200024)
40#define SCORE603E_85C30_CTRL_1         ((volatile uint8_t*)0xfe200028)
41#define SCORE603E_85C30_DATA_1         ((volatile uint8_t*)0xfe20002c)
42#define SCORE603E_85C30_CTRL_2         ((volatile uint8_t*)0xfe200000)
43#define SCORE603E_85C30_DATA_2         ((volatile uint8_t*)0xfe200004)
44#define SCORE603E_85C30_CTRL_3         ((volatile uint8_t*)0xfe200008)
45#define SCORE603E_85C30_DATA_3         ((volatile uint8_t*)0xfe20000c)
46
47/*
48 * PSC8 - PMC Card
49 */
50#define SCORE603E_PCI_CONFIGURATION_BASE   0x80800000
51#define SCORE603E_PMC_BASE                 SCORE603E_PCI_CONFIGURATION_BASE
52#define SCORE603E_PCI_PMC_DEVICE_BASE      0x80808000
53
54#define SCORE603E_PCI_REGISTER_BASE        0xfc000000
55
56#define SCORE603E_PCI_DEVICE_ADDRESS( _offset) \
57         ((volatile uint32_t*)( SCORE603E_PCI_PMC_DEVICE_BASE + _offset ))
58
59
60#define SCORE603E_PMC_SERIAL_ADDRESS( _offset )    \
61        ((volatile uint8_t*)(SCORE603E_PCI_REGISTER_BASE + _offset))
62
63/*
64 * PMC serial channels - (4-7: 232 and 8-11: 422)
65 */
66#define SCORE603E_85C30_CTRL_4        SCORE603E_PMC_SERIAL_ADDRESS(0x200020)
67#define SCORE603E_85C30_DATA_4        SCORE603E_PMC_SERIAL_ADDRESS(0x200024)
68#define SCORE603E_85C30_CTRL_5        SCORE603E_PMC_SERIAL_ADDRESS(0x200028)
69#define SCORE603E_85C30_DATA_5        SCORE603E_PMC_SERIAL_ADDRESS(0x20002c)
70#define SCORE603E_85C30_CTRL_6        SCORE603E_PMC_SERIAL_ADDRESS(0x200030)
71#define SCORE603E_85C30_DATA_6        SCORE603E_PMC_SERIAL_ADDRESS(0x200034)
72#define SCORE603E_85C30_CTRL_7        SCORE603E_PMC_SERIAL_ADDRESS(0x200038)
73#define SCORE603E_85C30_DATA_7        SCORE603E_PMC_SERIAL_ADDRESS(0x20003c)
74#define SCORE603E_85C30_CTRL_8        SCORE603E_PMC_SERIAL_ADDRESS(0x200000)
75#define SCORE603E_85C30_DATA_8        SCORE603E_PMC_SERIAL_ADDRESS(0x200004)
76#define SCORE603E_85C30_CTRL_9        SCORE603E_PMC_SERIAL_ADDRESS(0x200008)
77#define SCORE603E_85C30_DATA_9        SCORE603E_PMC_SERIAL_ADDRESS(0x20000c)
78#define SCORE603E_85C30_CTRL_10       SCORE603E_PMC_SERIAL_ADDRESS(0x200010)
79#define SCORE603E_85C30_DATA_10       SCORE603E_PMC_SERIAL_ADDRESS(0x200014)
80#define SCORE603E_85C30_CTRL_11       SCORE603E_PMC_SERIAL_ADDRESS(0x200018)
81#define SCORE603E_85C30_DATA_11       SCORE603E_PMC_SERIAL_ADDRESS(0x20001c)
82
83#define SCORE603E_PCI_IO_CFG_ADDR      0x80000cf8
84#define SCORE603E_PCI_IO_CFG_DATA      0x80000cfc
85
86#define SCORE603E_UNIVERSE_BASE        0x80030000
87#define SCORE603E_IO_VME_UNIVERSE_BASE 0x80007000
88#define SCORE603E_PCI_MEM_BASE         0xc0000000
89#define SCORE603E_NVRAM_BASE           0xfd100000
90#define SCORE603E_RTC_ADDRESS          ((volatile unsigned char *)0xfd180000)
91#define SCORE603E_JP1_JP2_PROM_BASE    0xfff00000
92#define SCORE603E_NOT_JP1_2_FLASH_BASE 0xff800000
93
94
95#if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE)
96#define SCORE603E_VME_A16_OFFSET       0x04000000
97#elif (SCORE603E_USE_DINK)
98#define SCORE603E_VME_A16_OFFSET       0x11000000
99#define SCORE603E_VME_A24_OFFSET       0x10000000
100#define SCORE603E_VME_A24_BASE         (SCORE603E_PCI_MEM_BASE+SCORE603E_VME_A24_OFFSET)
101#else
102#error "SCORE603E gen2.h -- what ROM monitor are you using"
103#endif
104
105#define SCORE603E_VME_A16_BASE         (SCORE603E_PCI_MEM_BASE+SCORE603E_VME_A16_OFFSET)
106
107/*
108 *  Definations for the ICM 1770 RTC chip
109 */
110    /*
111     * These values are programed into a register and must not be changed.
112     */
113#define ICM1770_CRYSTAL_FREQ_32K      0x00
114#define ICM1770_CRYSTAL_FREQ_1M       0x01
115#define ICM1770_CRYSTAL_FREQ_2M       0x02
116#define ICM1770_CRYSTAL_FREQ_4M       0x03
117
118#define SCORE_RTC_FREQUENCY           ICM1770_CRYSTAL_FREQ_32K
119
120/*
121 *  Z85C30 Definations for the 423 interface.
122 */
123#define SCORE603E_85C30_0_CLOCK     14745600  /* 10,000,000 ?10->14.5 */
124#define SCORE603E_85C30_0_CLOCK_X       16
125
126/*
127 *  Z85C30 Definations for the 422 interface.
128 */
129#define SCORE603E_85C30_1_CLOCK     16000000  /* 10,000,000 ?10->14.5 */
130#define SCORE603E_85C30_1_CLOCK_X       16
131
132/*
133 *  Z85C30 Definations for the PMC serial chips
134 */
135#define SCORE603E_85C30_PMC_CLOCK     16000000  /* 10,000,000 ?10->14.5 */
136#define SCORE603E_85C30_PMC_CLOCK_X       16
137
138#define SCORE603E_85C30_2_CLOCK       SCORE603E_85C30_PMC_CLOCK
139#define SCORE603E_85C30_3_CLOCK       SCORE603E_85C30_PMC_CLOCK
140#define SCORE603E_85C30_4_CLOCK       SCORE603E_85C30_PMC_CLOCK
141#define SCORE603E_85C30_5_CLOCK       SCORE603E_85C30_PMC_CLOCK
142#define SCORE603E_85C30_2_CLOCK_X     SCORE603E_85C30_PMC_CLOCK_X
143#define SCORE603E_85C30_3_CLOCK_X     SCORE603E_85C30_PMC_CLOCK_X
144#define SCORE603E_85C30_4_CLOCK_X     SCORE603E_85C30_PMC_CLOCK_X
145#define SCORE603E_85C30_5_CLOCK_X     SCORE603E_85C30_PMC_CLOCK_X
146
147
148#define SCORE603E_UNIVERSE_CHIP_ID     0x000010E3
149
150/*
151 * FPGA Interupt Address Definations.
152 */
153#define SCORE603E_FPGA_VECT_DATA    ((volatile uint16_t*)0xfd000040)
154#define SCORE603E_FPGA_BIT1_15_0    ((volatile uint16_t*)0xfd000044)
155#define SCORE603E_FPGA_MASK_DATA    ((volatile uint16_t*)0xfd000048)
156#define SCORE603E_FPGA_IRQ_INPUT    ((volatile uint16_t*)0xfd00004c)
157
158/*
159 * The PMC status word is at the PMC base address
160 */
161#define SCORE603E_PMC_STATUS_ADDRESS  (SCORE603E_PMC_SERIAL_ADDRESS (0))
162#define Is_PMC_85C30_4_IRQ( _status ) (_status & 0x80)    /* SCC 422-1 */
163#define Is_PMC_85C30_2_IRQ( _status ) (_status & 0x40)    /* SCC 232-1 */
164#define Is_PMC_85C30_5_IRQ( _status ) (_status & 0x20)    /* SCC 422-2 */
165#define Is_PMC_85C30_3_IRQ( _status ) (_status & 0x08)    /* SCC 232-2 */
166
167#define SCORE603E_PMC_CONTROL_ADDRESS    SCORE603E_PMC_SERIAL_ADDRESS(0x100000)
168#define SCORE603E_PMC_SCC_232_LOOPBACK (_word) (_word|0x20)
169
170#define PMC_SET_232_LOOPBACK(_word)   (_word | 0x02)
171#define PMC_CLEAR_232_LOOPBACK(_word) (_word & 0xfd)
172#define PMC_SET_422_LOOPBACK(_word)   (_word | 0x01)
173#define PMC_CLEAR_422_LOOPBACK(_word) (_word & 0xfe)
174
175
176/*
177 *  Score603e Interupt Definations.
178 */
179
180/*
181 * First Score Unique IRQ
182 */
183#define Score_IRQ_First ( PPC_IRQ_LAST +  1 )
184
185/*
186 * The Following Are part of a Score603e FPGA.
187 */
188#define SCORE603E_IRQ00   ( Score_IRQ_First +  0 )
189#define SCORE603E_IRQ01   ( Score_IRQ_First +  1 )
190#define SCORE603E_IRQ02   ( Score_IRQ_First +  2 )
191#define SCORE603E_IRQ03   ( Score_IRQ_First +  3 )
192#define SCORE603E_IRQ04   ( Score_IRQ_First +  4 )
193#define SCORE603E_IRQ05   ( Score_IRQ_First +  5 )
194#define SCORE603E_IRQ06   ( Score_IRQ_First +  6 )
195#define SCORE603E_IRQ07   ( Score_IRQ_First +  7 )
196#define SCORE603E_IRQ08   ( Score_IRQ_First +  8 )
197#define SCORE603E_IRQ09   ( Score_IRQ_First +  9 )
198#define SCORE603E_IRQ10   ( Score_IRQ_First + 10 )
199#define SCORE603E_IRQ11   ( Score_IRQ_First + 11 )
200#define SCORE603E_IRQ12   ( Score_IRQ_First + 12 )
201#define SCORE603E_IRQ13   ( Score_IRQ_First + 13 )
202#define SCORE603E_IRQ14   ( Score_IRQ_First + 14 )
203#define SCORE603E_IRQ15   ( Score_IRQ_First + 15 )
204
205#define SCORE603E_TIMER1_IRQ           SCORE603E_IRQ00
206#define SCORE603E_TIMER2_IRQ           SCORE603E_IRQ01
207#define SCORE603E_TIMER3_IRQ           SCORE603E_IRQ02
208#define SCORE603E_85C30_1_IRQ          SCORE603E_IRQ03
209#define SCORE603E_85C30_0_IRQ          SCORE603E_IRQ04
210#define SCORE603E_RTC_IRQ              SCORE603E_IRQ05
211#define SCORE603E_PCI_IRQ_0            SCORE603E_IRQ06
212#define SCORE603E_PCI_IRQ_1            SCORE603E_IRQ07
213#define SCORE603E_PCI_IRQ_2            SCORE603E_IRQ08
214#define SCORE603E_PCI_IRQ_3            SCORE603E_IRQ09
215#define SCORE603E_UNIVERSE_IRQ         SCORE603E_IRQ10
216#define SCORE603E_1553_IRQ             SCORE603E_IRQ11
217#define SCORE603E_MAIL_BOX_IRQ_0       SCORE603E_IRQ12
218#define SCORE603E_MAIL_BOX_IRQ_1       SCORE603E_IRQ13
219#define SCORE603E_MAIL_BOX_IRQ_2       SCORE603E_IRQ14
220#define SCORE603E_MAIL_BOX_IRQ_3       SCORE603E_IRQ15
221
222/*
223 * The Score FPGA maps all interrupts comming from the PMC card to
224 * the FPGA interrupt SCORE603E_PCI_IRQ_0 the PMC status word must be
225 * read to indicate which interrupt was chained to the FPGA.
226 */
227#define SCORE603E_IRQ16   ( Score_IRQ_First + 16 )
228#define SCORE603E_IRQ17   ( Score_IRQ_First + 17 )
229#define SCORE603E_IRQ18   ( Score_IRQ_First + 18 )
230#define SCORE603E_IRQ19   ( Score_IRQ_First + 19 )
231
232/*
233 * IRQ'a read from the PMC card
234 */
235#define SCORE603E_85C30_4_IRQ          SCORE603E_IRQ16    /* SCC 422-1 */
236#define SCORE603E_85C30_2_IRQ          SCORE603E_IRQ17    /* SCC 232-1 */
237#define SCORE603E_85C30_5_IRQ          SCORE603E_IRQ18    /* SCC 422-2 */
238#define SCORE603E_85C30_3_IRQ          SCORE603E_IRQ19    /* SCC 232-2 */
239
240#define MAX_BOARD_IRQS                 SCORE603E_IRQ19
241
242
243/*
244 *  BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID for the shared timer
245 *  driver.
246 */
247
248#define BSP_TIMER_AVG_OVERHEAD   4  /* It typically takes xx clicks        */
249                                    /*     to start/stop the timer.        */
250#define BSP_TIMER_LEAST_VALID    1  /* Don't trust a value lower than this */
251
252/*
253 *  Convert decrement value to tenths of microsecnds (used by
254 *  shared timer driver).
255 *
256 *    + CPU has a 66.67 Mhz bus,
257 *    + There are 4 bus cycles per click
258 *    + We return value in 1/10 microsecond units.
259 *   Modified following equation to integer equation to remove
260 *   floating point math.
261 *   (int) ((float)(_value) / ((66.67 * 0.1) / 4.0))
262 */
263
264#define BSP_Convert_decrementer( _value ) \
265  (int) (((_value) * 4000) / 6667)
266
267#endif
268
269#ifdef __cplusplus
270}
271#endif
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