source: rtems/c/src/lib/libbsp/powerpc/score603e/include/gen2.h @ 40e7ae2

4.104.114.9
Last change on this file since 40e7ae2 was 40e7ae2, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 3, 2008 at 8:36:21 PM

2008-09-03 Joel Sherrill <joel.sherrill@…>

  • Makefile.am, README, configure.ac, console/85c30.c, console/console.c, console/consolebsp.h, include/bsp.h, include/gen2.h, irq/FPGA.c, irq/irq.c, irq/irq.h, irq/irq_init.c, start/start.S, startup/bspstart.c, startup/genpvec.c, startup/linkcmds, timer/timer.c, tod/tod.c: Initiate update and testing. Runs hello but does not run ticker yet.
  • Property mode set to 100644
File size: 10.2 KB
Line 
1/*  Gen2.h
2 *
3 *  This include file contains all Generation 2 board addreses
4 *
5 *  COPYRIGHT (c) 1989-1997.
6 *  On-Line Applications Research Corporation (OAR).
7 *
8 *  The license and distribution terms for this file may in
9 *  the file LICENSE in this distribution or at
10 *  http://www.rtems.com/license/LICENSE.
11 *
12 *  $Id:
13 */
14
15#ifndef __SCORE_GENERATION_2_h
16#define __SCORE_GENERATION_2_h
17
18#ifdef __cplusplus
19extern "C" {
20#endif
21
22#include <rtems.h>
23
24/*
25 * ISA/PCI I/O space.
26 */
27#define SCORE603E_VME_JUMPER_ADDR      0x00e20000
28#define BSP_FLASH_BASE                 0x04000000
29#define SCORE603E_ISA_PCI_IO_BASE      0x80000000
30#define SCORE603E_TIMER_PORT_C         0xfd000000
31#define SCORE603E_TIMER_INT_ACK        0xfd000000
32#define SCORE603E_TIMER_PORT_B         0xfd000008
33#define SCORE603E_TIMER_PORT_A         0xfd000004
34
35#define SCORE603E_BOARD_CTRL_REG       ((volatile uint8_t*)0xfd00002c)
36#define SCORE603E_BRD_FLASH_DISABLE_MASK     0x40
37
38#define SCORE603E_85C30_CTRL_0         ((volatile uint8_t*)0xfe200020)
39#define SCORE603E_85C30_DATA_0         ((volatile uint8_t*)0xfe200024)
40#define SCORE603E_85C30_CTRL_1         ((volatile uint8_t*)0xfe200028)
41#define SCORE603E_85C30_DATA_1         ((volatile uint8_t*)0xfe20002c)
42#define SCORE603E_85C30_CTRL_2         ((volatile uint8_t*)0xfe200000)
43#define SCORE603E_85C30_DATA_2         ((volatile uint8_t*)0xfe200004)
44#define SCORE603E_85C30_CTRL_3         ((volatile uint8_t*)0xfe200008)
45#define SCORE603E_85C30_DATA_3         ((volatile uint8_t*)0xfe20000c)
46
47/*
48 * PSC8 - PMC Card
49 */
50/* address of our ram on the PCI bus   */
51#define PCI_DRAM_OFFSET              PREP_PCI_DRAM_OFFSET
52#define BSP_PCI_CONFIGURATION_BASE   0x80800000
53#define BSP_PMC_BASE                 BSP_PCI_CONFIGURATION_BASE
54#define PCI_MEM_BASE_ADJUSTMENT      0
55#define BSP_PCI_PMC_DEVICE_BASE      0x80808000
56#define BSP_PCI_REGISTER_BASE        0xfc000000
57
58#define BSP_PCI_DEVICE_ADDRESS( _offset) \
59         ((volatile uint32_t *)( BSP_PCI_PMC_DEVICE_BASE + _offset ))
60
61
62#define BSP_PMC_SERIAL_ADDRESS( _offset )    \
63        ((volatile uint8_t*)(BSP_PCI_REGISTER_BASE + _offset))
64
65/*
66 * PMC serial channels - (4-7: 232 and 8-11: 422)
67 */
68#define SCORE603E_85C30_CTRL_4        BSP_PMC_SERIAL_ADDRESS(0x00200020)
69#define SCORE603E_85C30_DATA_4        BSP_PMC_SERIAL_ADDRESS(0x00200024)
70#define SCORE603E_85C30_CTRL_5        BSP_PMC_SERIAL_ADDRESS(0x00200028)
71#define SCORE603E_85C30_DATA_5        BSP_PMC_SERIAL_ADDRESS(0x0020002c)
72#define SCORE603E_85C30_CTRL_6        BSP_PMC_SERIAL_ADDRESS(0x00200030)
73#define SCORE603E_85C30_DATA_6        BSP_PMC_SERIAL_ADDRESS(0x00200034)
74#define SCORE603E_85C30_CTRL_7        BSP_PMC_SERIAL_ADDRESS(0x00200038)
75#define SCORE603E_85C30_DATA_7        BSP_PMC_SERIAL_ADDRESS(0x0020003c)
76#define SCORE603E_85C30_CTRL_8        BSP_PMC_SERIAL_ADDRESS(0x00200000)
77#define SCORE603E_85C30_DATA_8        BSP_PMC_SERIAL_ADDRESS(0x00200004)
78#define SCORE603E_85C30_CTRL_9        BSP_PMC_SERIAL_ADDRESS(0x00200008)
79#define SCORE603E_85C30_DATA_9        BSP_PMC_SERIAL_ADDRESS(0x0020000c)
80#define SCORE603E_85C30_CTRL_10       BSP_PMC_SERIAL_ADDRESS(0x00200010)
81#define SCORE603E_85C30_DATA_10       BSP_PMC_SERIAL_ADDRESS(0x00200014)
82#define SCORE603E_85C30_CTRL_11       BSP_PMC_SERIAL_ADDRESS(0x00200018)
83#define SCORE603E_85C30_DATA_11       BSP_PMC_SERIAL_ADDRESS(0x0020001c)
84
85#define _IO_BASE                       PREP_ISA_IO_BASE
86#define SCORE603E_PCI_IO_CFG_ADDR      0x80000cf8
87#define SCORE603E_PCI_IO_CFG_DATA      0x80000cfc
88
89#define SCORE603E_UNIVERSE_BASE        0x80030000
90#define SCORE603E_IO_VME_UNIVERSE_BASE 0x80007000
91#define PCI_MEM_BASE                   0xc0000000
92#define BSP_PCI_MEM_BASE               PCI_MEM_BASE  /* XXX - May want to remove this later */
93#define BSP_NVRAM_BASE           0xfd100000
94#define BSP_RTC_ADDRESS          ((volatile unsigned char *)0xfd180000)
95#define SCORE603E_JP1_JP2_PROM_BASE    0xfff00000
96#define SCORE603E_NOT_JP1_2_FLASH_BASE 0xff800000
97
98#if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE)
99#define SCORE603E_VME_A16_OFFSET       0x04000000
100#elif (SCORE603E_USE_DINK)
101#define SCORE603E_VME_A16_OFFSET       0x11000000
102#define SCORE603E_VME_A24_OFFSET       0x10000000
103#define BSP_VME_A24_BASE               (BSP_PCI_MEM_BASE+SCORE603E_VME_A24_OFFSET)
104#else
105#error "SCORE603E gen2.h -- what ROM monitor are you using"
106#endif
107
108#define BSP_VME_A16_BASE         (BSP_PCI_MEM_BASE+SCORE603E_VME_A16_OFFSET)
109
110/*
111 *  Definations for the ICM 1770 RTC chip
112 */
113    /*
114     * These values are programed into a register and must not be changed.
115     */
116#define ICM1770_CRYSTAL_FREQ_32K      0x00
117#define ICM1770_CRYSTAL_FREQ_1M       0x01
118#define ICM1770_CRYSTAL_FREQ_2M       0x02
119#define ICM1770_CRYSTAL_FREQ_4M       0x03
120
121#define BSP_RTC_FREQUENCY           ICM1770_CRYSTAL_FREQ_32K
122
123/*
124 *  Z85C30 Definations for the 423 interface.
125 */
126#define SCORE603E_85C30_0_CLOCK     14745600  /* 10,000,000 ?10->14.5 */
127#define SCORE603E_85C30_0_CLOCK_X       16
128
129/*
130 *  Z85C30 Definations for the 422 interface.
131 */
132#define SCORE603E_85C30_1_CLOCK     16000000  /* 10,000,000 ?10->14.5 */
133#define SCORE603E_85C30_1_CLOCK_X       16
134
135/*
136 *  Z85C30 Definations for the PMC serial chips
137 */
138#define SCORE603E_85C30_PMC_CLOCK     16000000  /* 10,000,000 ?10->14.5 */
139#define SCORE603E_85C30_PMC_CLOCK_X       16
140
141#define SCORE603E_85C30_2_CLOCK       SCORE603E_85C30_PMC_CLOCK
142#define SCORE603E_85C30_3_CLOCK       SCORE603E_85C30_PMC_CLOCK
143#define SCORE603E_85C30_4_CLOCK       SCORE603E_85C30_PMC_CLOCK
144#define SCORE603E_85C30_5_CLOCK       SCORE603E_85C30_PMC_CLOCK
145#define SCORE603E_85C30_2_CLOCK_X     SCORE603E_85C30_PMC_CLOCK_X
146#define SCORE603E_85C30_3_CLOCK_X     SCORE603E_85C30_PMC_CLOCK_X
147#define SCORE603E_85C30_4_CLOCK_X     SCORE603E_85C30_PMC_CLOCK_X
148#define SCORE603E_85C30_5_CLOCK_X     SCORE603E_85C30_PMC_CLOCK_X
149
150#define SCORE603E_UNIVERSE_CHIP_ID     0x000010E3
151
152/*
153 * FPGA Interupt Address Definations.
154 */
155#define SCORE603E_FPGA_VECT_DATA    ((volatile uint16_t*)0xfd000040)
156#define SCORE603E_FPGA_BIT1_15_0    ((volatile uint16_t*)0xfd000044)
157#define SCORE603E_FPGA_MASK_DATA    ((volatile uint16_t*)0xfd000048)
158#define SCORE603E_FPGA_IRQ_INPUT    ((volatile uint16_t*)0xfd00004c)
159
160/*
161 * The PMC status word is at the PMC base address
162 */
163#define BSP_PMC_STATUS_ADDRESS  (BSP_PMC_SERIAL_ADDRESS (0))
164#define Is_PMC_85C30_4_IRQ( _status ) (_status & 0x80)    /* SCC 422-1 */
165#define Is_PMC_85C30_2_IRQ( _status ) (_status & 0x40)    /* SCC 232-1 */
166#define Is_PMC_85C30_5_IRQ( _status ) (_status & 0x20)    /* SCC 422-2 */
167#define Is_PMC_85C30_3_IRQ( _status ) (_status & 0x08)    /* SCC 232-2 */
168
169#define SCORE603E_PMC_CONTROL_ADDRESS    BSP_PMC_SERIAL_ADDRESS(0x100000)
170#define SCORE603E_PMC_SCC_232_LOOPBACK (_word) (_word|0x20)
171
172#define PMC_SET_232_LOOPBACK(_word)   (_word | 0x02)
173#define PMC_CLEAR_232_LOOPBACK(_word) (_word & 0xfd)
174#define PMC_SET_422_LOOPBACK(_word)   (_word | 0x01)
175#define PMC_CLEAR_422_LOOPBACK(_word) (_word & 0xfe)
176
177/*
178 *  Score603e Interupt Definations.
179 */
180
181/*
182 * First Score Unique IRQ
183 */
184#define Score_IRQ_First ( PPC_IRQ_LAST +  1 )
185
186/*
187 * The Following Are part of a Score603e FPGA.
188 */
189#define SCORE603E_IRQ00   ( Score_IRQ_First +  0 )
190#define SCORE603E_IRQ01   ( Score_IRQ_First +  1 )
191#define SCORE603E_IRQ02   ( Score_IRQ_First +  2 )
192#define SCORE603E_IRQ03   ( Score_IRQ_First +  3 )
193#define SCORE603E_IRQ04   ( Score_IRQ_First +  4 )
194#define SCORE603E_IRQ05   ( Score_IRQ_First +  5 )
195#define SCORE603E_IRQ06   ( Score_IRQ_First +  6 )
196#define SCORE603E_IRQ07   ( Score_IRQ_First +  7 )
197#define SCORE603E_IRQ08   ( Score_IRQ_First +  8 )
198#define SCORE603E_IRQ09   ( Score_IRQ_First +  9 )
199#define SCORE603E_IRQ10   ( Score_IRQ_First + 10 )
200#define SCORE603E_IRQ11   ( Score_IRQ_First + 11 )
201#define SCORE603E_IRQ12   ( Score_IRQ_First + 12 )
202#define SCORE603E_IRQ13   ( Score_IRQ_First + 13 )
203#define SCORE603E_IRQ14   ( Score_IRQ_First + 14 )
204#define SCORE603E_IRQ15   ( Score_IRQ_First + 15 )
205
206#define SCORE603E_TIMER1_IRQ           SCORE603E_IRQ00
207#define SCORE603E_TIMER2_IRQ           SCORE603E_IRQ01
208#define SCORE603E_TIMER3_IRQ           SCORE603E_IRQ02
209#define SCORE603E_85C30_1_IRQ          SCORE603E_IRQ03
210#define SCORE603E_85C30_0_IRQ          SCORE603E_IRQ04
211#define SCORE603E_RTC_IRQ              SCORE603E_IRQ05
212#define SCORE603E_PCI_IRQ_0            SCORE603E_IRQ06
213#define SCORE603E_PCI_IRQ_1            SCORE603E_IRQ07
214#define SCORE603E_PCI_IRQ_2            SCORE603E_IRQ08
215#define SCORE603E_PCI_IRQ_3            SCORE603E_IRQ09
216#define SCORE603E_UNIVERSE_IRQ         SCORE603E_IRQ10
217#define SCORE603E_1553_IRQ             SCORE603E_IRQ11
218#define SCORE603E_MAIL_BOX_IRQ_0       SCORE603E_IRQ12
219#define SCORE603E_MAIL_BOX_IRQ_1       SCORE603E_IRQ13
220#define SCORE603E_MAIL_BOX_IRQ_2       SCORE603E_IRQ14
221#define SCORE603E_MAIL_BOX_IRQ_3       SCORE603E_IRQ15
222
223/*
224 * The Score FPGA maps all interrupts comming from the PMC card to
225 * the FPGA interrupt SCORE603E_PCI_IRQ_0 the PMC status word must be
226 * read to indicate which interrupt was chained to the FPGA.
227 */
228#define SCORE603E_IRQ16   ( Score_IRQ_First + 16 )
229#define SCORE603E_IRQ17   ( Score_IRQ_First + 17 )
230#define SCORE603E_IRQ18   ( Score_IRQ_First + 18 )
231#define SCORE603E_IRQ19   ( Score_IRQ_First + 19 )
232
233/*
234 * IRQ'a read from the PMC card
235 */
236#define SCORE603E_85C30_4_IRQ          SCORE603E_IRQ16    /* SCC 422-1 */
237#define SCORE603E_85C30_2_IRQ          SCORE603E_IRQ17    /* SCC 232-1 */
238#define SCORE603E_85C30_5_IRQ          SCORE603E_IRQ18    /* SCC 422-2 */
239#define SCORE603E_85C30_3_IRQ          SCORE603E_IRQ19    /* SCC 232-2 */
240
241#define MAX_BOARD_IRQS                 SCORE603E_IRQ19
242
243/*
244 *  BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID for the shared timer
245 *  driver.
246 */
247
248#define BSP_TIMER_AVG_OVERHEAD   4  /* It typically takes xx clicks        */
249                                    /*     to start/stop the timer.        */
250#define BSP_TIMER_LEAST_VALID    1  /* Don't trust a value lower than this */
251
252/*
253 *  Convert decrement value to tenths of microsecnds (used by
254 *  shared timer driver).
255 *
256 *    + CPU has a 66.67 Mhz bus,
257 *    + There are 4 bus cycles per click
258 *    + We return value in 1/10 microsecond units.
259 *   Modified following equation to integer equation to remove
260 *   floating point math.
261 *   (int) ((float)(_value) / ((66.67 * 0.1) / 4.0))
262 */
263
264#define BSP_Convert_decrementer( _value ) \
265  (int) (((_value) * 4000) / 6667)
266
267#endif
268
269#ifdef __cplusplus
270}
271#endif
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