[9c448e1] | 1 | /* Gen2.h |
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| 2 | * |
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| 3 | * This include file contains all Generation 2 board addreses |
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| 4 | * |
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| 5 | * COPYRIGHT (c) 1989-1997. |
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| 6 | * On-Line Applications Research Corporation (OAR). |
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| 7 | * |
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| 8 | * The license and distribution terms for this file may in |
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| 9 | * the file LICENSE in this distribution or at |
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[b14e2f2] | 10 | * http://www.rtems.com/license/LICENSE. |
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[9c448e1] | 11 | * |
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[6128a4a] | 12 | * $Id: |
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[9c448e1] | 13 | */ |
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| 14 | |
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| 15 | #ifndef __SCORE_GENERATION_2_h |
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| 16 | #define __SCORE_GENERATION_2_h |
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| 17 | |
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| 18 | #ifdef __cplusplus |
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| 19 | extern "C" { |
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| 20 | #endif |
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| 21 | |
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| 22 | #include <rtems.h> |
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| 23 | |
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| 24 | /* |
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| 25 | * ISA/PCI I/O space. |
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| 26 | */ |
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[6128a4a] | 27 | #define SCORE603E_VME_JUMPER_ADDR 0x00e20000 |
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[f309cda] | 28 | #define BSP_FLASH_BASE 0x04000000 |
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[9c448e1] | 29 | #define SCORE603E_ISA_PCI_IO_BASE 0x80000000 |
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[6128a4a] | 30 | #define SCORE603E_TIMER_PORT_C 0xfd000000 |
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| 31 | #define SCORE603E_TIMER_INT_ACK 0xfd000000 |
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[9c448e1] | 32 | #define SCORE603E_TIMER_PORT_B 0xfd000008 |
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| 33 | #define SCORE603E_TIMER_PORT_A 0xfd000004 |
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| 34 | |
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[dac4208] | 35 | #define SCORE603E_BOARD_CTRL_REG ((volatile uint8_t*)0xfd00002c) |
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[9c448e1] | 36 | #define SCORE603E_BRD_FLASH_DISABLE_MASK 0x40 |
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| 37 | |
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[dac4208] | 38 | #define SCORE603E_85C30_CTRL_0 ((volatile uint8_t*)0xfe200020) |
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| 39 | #define SCORE603E_85C30_DATA_0 ((volatile uint8_t*)0xfe200024) |
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| 40 | #define SCORE603E_85C30_CTRL_1 ((volatile uint8_t*)0xfe200028) |
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| 41 | #define SCORE603E_85C30_DATA_1 ((volatile uint8_t*)0xfe20002c) |
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| 42 | #define SCORE603E_85C30_CTRL_2 ((volatile uint8_t*)0xfe200000) |
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| 43 | #define SCORE603E_85C30_DATA_2 ((volatile uint8_t*)0xfe200004) |
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| 44 | #define SCORE603E_85C30_CTRL_3 ((volatile uint8_t*)0xfe200008) |
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| 45 | #define SCORE603E_85C30_DATA_3 ((volatile uint8_t*)0xfe20000c) |
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[9c448e1] | 46 | |
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| 47 | /* |
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[6128a4a] | 48 | * PSC8 - PMC Card |
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[9c448e1] | 49 | */ |
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[bb41881e] | 50 | /* address of our ram on the PCI bus */ |
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| 51 | #define PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET |
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[f309cda] | 52 | #define BSP_PCI_CONFIGURATION_BASE 0x80800000 |
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| 53 | #define BSP_PMC_BASE BSP_PCI_CONFIGURATION_BASE |
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[bb41881e] | 54 | #define PCI_MEM_BASE_ADJUSTMENT 0 |
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[f309cda] | 55 | #define BSP_PCI_PMC_DEVICE_BASE 0x80808000 |
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| 56 | #define BSP_PCI_REGISTER_BASE 0xfc000000 |
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[9c448e1] | 57 | |
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[f309cda] | 58 | #define BSP_PCI_DEVICE_ADDRESS( _offset) \ |
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[7929893] | 59 | ((volatile uint32_t *)( BSP_PCI_PMC_DEVICE_BASE + _offset )) |
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[6128a4a] | 60 | |
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[f309cda] | 61 | |
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| 62 | #define BSP_PMC_SERIAL_ADDRESS( _offset ) \ |
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[40e7ae2] | 63 | ((volatile uint8_t*)(BSP_PCI_REGISTER_BASE + _offset)) |
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[9c448e1] | 64 | |
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| 65 | /* |
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| 66 | * PMC serial channels - (4-7: 232 and 8-11: 422) |
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| 67 | */ |
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[40e7ae2] | 68 | #define SCORE603E_85C30_CTRL_4 BSP_PMC_SERIAL_ADDRESS(0x00200020) |
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| 69 | #define SCORE603E_85C30_DATA_4 BSP_PMC_SERIAL_ADDRESS(0x00200024) |
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| 70 | #define SCORE603E_85C30_CTRL_5 BSP_PMC_SERIAL_ADDRESS(0x00200028) |
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| 71 | #define SCORE603E_85C30_DATA_5 BSP_PMC_SERIAL_ADDRESS(0x0020002c) |
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| 72 | #define SCORE603E_85C30_CTRL_6 BSP_PMC_SERIAL_ADDRESS(0x00200030) |
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| 73 | #define SCORE603E_85C30_DATA_6 BSP_PMC_SERIAL_ADDRESS(0x00200034) |
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| 74 | #define SCORE603E_85C30_CTRL_7 BSP_PMC_SERIAL_ADDRESS(0x00200038) |
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| 75 | #define SCORE603E_85C30_DATA_7 BSP_PMC_SERIAL_ADDRESS(0x0020003c) |
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| 76 | #define SCORE603E_85C30_CTRL_8 BSP_PMC_SERIAL_ADDRESS(0x00200000) |
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| 77 | #define SCORE603E_85C30_DATA_8 BSP_PMC_SERIAL_ADDRESS(0x00200004) |
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| 78 | #define SCORE603E_85C30_CTRL_9 BSP_PMC_SERIAL_ADDRESS(0x00200008) |
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| 79 | #define SCORE603E_85C30_DATA_9 BSP_PMC_SERIAL_ADDRESS(0x0020000c) |
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| 80 | #define SCORE603E_85C30_CTRL_10 BSP_PMC_SERIAL_ADDRESS(0x00200010) |
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| 81 | #define SCORE603E_85C30_DATA_10 BSP_PMC_SERIAL_ADDRESS(0x00200014) |
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| 82 | #define SCORE603E_85C30_CTRL_11 BSP_PMC_SERIAL_ADDRESS(0x00200018) |
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| 83 | #define SCORE603E_85C30_DATA_11 BSP_PMC_SERIAL_ADDRESS(0x0020001c) |
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[9c448e1] | 84 | |
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[bb41881e] | 85 | #define _IO_BASE PREP_ISA_IO_BASE |
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[9c448e1] | 86 | #define SCORE603E_PCI_IO_CFG_ADDR 0x80000cf8 |
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| 87 | #define SCORE603E_PCI_IO_CFG_DATA 0x80000cfc |
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| 88 | |
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| 89 | #define SCORE603E_UNIVERSE_BASE 0x80030000 |
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| 90 | #define SCORE603E_IO_VME_UNIVERSE_BASE 0x80007000 |
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[bb41881e] | 91 | #define PCI_MEM_BASE 0xc0000000 |
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| 92 | #define BSP_PCI_MEM_BASE PCI_MEM_BASE /* XXX - May want to remove this later */ |
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[f309cda] | 93 | #define BSP_NVRAM_BASE 0xfd100000 |
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| 94 | #define BSP_RTC_ADDRESS ((volatile unsigned char *)0xfd180000) |
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[9c448e1] | 95 | #define SCORE603E_JP1_JP2_PROM_BASE 0xfff00000 |
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| 96 | #define SCORE603E_NOT_JP1_2_FLASH_BASE 0xff800000 |
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| 97 | |
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| 98 | #if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE) |
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| 99 | #define SCORE603E_VME_A16_OFFSET 0x04000000 |
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| 100 | #elif (SCORE603E_USE_DINK) |
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| 101 | #define SCORE603E_VME_A16_OFFSET 0x11000000 |
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| 102 | #define SCORE603E_VME_A24_OFFSET 0x10000000 |
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[f309cda] | 103 | #define BSP_VME_A24_BASE (BSP_PCI_MEM_BASE+SCORE603E_VME_A24_OFFSET) |
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[9c448e1] | 104 | #else |
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| 105 | #error "SCORE603E gen2.h -- what ROM monitor are you using" |
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| 106 | #endif |
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| 107 | |
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[f309cda] | 108 | #define BSP_VME_A16_BASE (BSP_PCI_MEM_BASE+SCORE603E_VME_A16_OFFSET) |
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[9c448e1] | 109 | |
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| 110 | /* |
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| 111 | * Definations for the ICM 1770 RTC chip |
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[6128a4a] | 112 | */ |
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[9c448e1] | 113 | /* |
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| 114 | * These values are programed into a register and must not be changed. |
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| 115 | */ |
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| 116 | #define ICM1770_CRYSTAL_FREQ_32K 0x00 |
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| 117 | #define ICM1770_CRYSTAL_FREQ_1M 0x01 |
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| 118 | #define ICM1770_CRYSTAL_FREQ_2M 0x02 |
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| 119 | #define ICM1770_CRYSTAL_FREQ_4M 0x03 |
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| 120 | |
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[f309cda] | 121 | #define BSP_RTC_FREQUENCY ICM1770_CRYSTAL_FREQ_32K |
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[9c448e1] | 122 | |
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| 123 | /* |
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| 124 | * Z85C30 Definations for the 423 interface. |
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| 125 | */ |
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| 126 | #define SCORE603E_85C30_0_CLOCK 14745600 /* 10,000,000 ?10->14.5 */ |
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[6128a4a] | 127 | #define SCORE603E_85C30_0_CLOCK_X 16 |
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[9c448e1] | 128 | |
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| 129 | /* |
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| 130 | * Z85C30 Definations for the 422 interface. |
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| 131 | */ |
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| 132 | #define SCORE603E_85C30_1_CLOCK 16000000 /* 10,000,000 ?10->14.5 */ |
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[6128a4a] | 133 | #define SCORE603E_85C30_1_CLOCK_X 16 |
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[9c448e1] | 134 | |
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| 135 | /* |
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| 136 | * Z85C30 Definations for the PMC serial chips |
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| 137 | */ |
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| 138 | #define SCORE603E_85C30_PMC_CLOCK 16000000 /* 10,000,000 ?10->14.5 */ |
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[6128a4a] | 139 | #define SCORE603E_85C30_PMC_CLOCK_X 16 |
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[9c448e1] | 140 | |
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| 141 | #define SCORE603E_85C30_2_CLOCK SCORE603E_85C30_PMC_CLOCK |
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| 142 | #define SCORE603E_85C30_3_CLOCK SCORE603E_85C30_PMC_CLOCK |
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| 143 | #define SCORE603E_85C30_4_CLOCK SCORE603E_85C30_PMC_CLOCK |
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| 144 | #define SCORE603E_85C30_5_CLOCK SCORE603E_85C30_PMC_CLOCK |
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| 145 | #define SCORE603E_85C30_2_CLOCK_X SCORE603E_85C30_PMC_CLOCK_X |
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| 146 | #define SCORE603E_85C30_3_CLOCK_X SCORE603E_85C30_PMC_CLOCK_X |
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| 147 | #define SCORE603E_85C30_4_CLOCK_X SCORE603E_85C30_PMC_CLOCK_X |
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| 148 | #define SCORE603E_85C30_5_CLOCK_X SCORE603E_85C30_PMC_CLOCK_X |
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| 149 | |
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| 150 | #define SCORE603E_UNIVERSE_CHIP_ID 0x000010E3 |
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| 151 | |
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| 152 | /* |
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| 153 | * FPGA Interupt Address Definations. |
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| 154 | */ |
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[dac4208] | 155 | #define SCORE603E_FPGA_VECT_DATA ((volatile uint16_t*)0xfd000040) |
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| 156 | #define SCORE603E_FPGA_BIT1_15_0 ((volatile uint16_t*)0xfd000044) |
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| 157 | #define SCORE603E_FPGA_MASK_DATA ((volatile uint16_t*)0xfd000048) |
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| 158 | #define SCORE603E_FPGA_IRQ_INPUT ((volatile uint16_t*)0xfd00004c) |
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[9c448e1] | 159 | |
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| 160 | /* |
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[6128a4a] | 161 | * The PMC status word is at the PMC base address |
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[9c448e1] | 162 | */ |
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[f309cda] | 163 | #define BSP_PMC_STATUS_ADDRESS (BSP_PMC_SERIAL_ADDRESS (0)) |
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[9c448e1] | 164 | #define Is_PMC_85C30_4_IRQ( _status ) (_status & 0x80) /* SCC 422-1 */ |
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| 165 | #define Is_PMC_85C30_2_IRQ( _status ) (_status & 0x40) /* SCC 232-1 */ |
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| 166 | #define Is_PMC_85C30_5_IRQ( _status ) (_status & 0x20) /* SCC 422-2 */ |
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| 167 | #define Is_PMC_85C30_3_IRQ( _status ) (_status & 0x08) /* SCC 232-2 */ |
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| 168 | |
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[f309cda] | 169 | #define SCORE603E_PMC_CONTROL_ADDRESS BSP_PMC_SERIAL_ADDRESS(0x100000) |
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[9c448e1] | 170 | #define SCORE603E_PMC_SCC_232_LOOPBACK (_word) (_word|0x20) |
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| 171 | |
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[6128a4a] | 172 | #define PMC_SET_232_LOOPBACK(_word) (_word | 0x02) |
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| 173 | #define PMC_CLEAR_232_LOOPBACK(_word) (_word & 0xfd) |
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| 174 | #define PMC_SET_422_LOOPBACK(_word) (_word | 0x01) |
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| 175 | #define PMC_CLEAR_422_LOOPBACK(_word) (_word & 0xfe) |
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| 176 | |
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[9c448e1] | 177 | /* |
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| 178 | * Score603e Interupt Definations. |
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| 179 | */ |
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| 180 | |
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[6128a4a] | 181 | /* |
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[9c448e1] | 182 | * First Score Unique IRQ |
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| 183 | */ |
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| 184 | #define Score_IRQ_First ( PPC_IRQ_LAST + 1 ) |
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| 185 | |
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| 186 | /* |
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| 187 | * The Following Are part of a Score603e FPGA. |
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| 188 | */ |
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| 189 | #define SCORE603E_IRQ00 ( Score_IRQ_First + 0 ) |
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| 190 | #define SCORE603E_IRQ01 ( Score_IRQ_First + 1 ) |
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| 191 | #define SCORE603E_IRQ02 ( Score_IRQ_First + 2 ) |
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| 192 | #define SCORE603E_IRQ03 ( Score_IRQ_First + 3 ) |
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| 193 | #define SCORE603E_IRQ04 ( Score_IRQ_First + 4 ) |
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| 194 | #define SCORE603E_IRQ05 ( Score_IRQ_First + 5 ) |
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| 195 | #define SCORE603E_IRQ06 ( Score_IRQ_First + 6 ) |
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| 196 | #define SCORE603E_IRQ07 ( Score_IRQ_First + 7 ) |
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| 197 | #define SCORE603E_IRQ08 ( Score_IRQ_First + 8 ) |
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| 198 | #define SCORE603E_IRQ09 ( Score_IRQ_First + 9 ) |
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| 199 | #define SCORE603E_IRQ10 ( Score_IRQ_First + 10 ) |
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| 200 | #define SCORE603E_IRQ11 ( Score_IRQ_First + 11 ) |
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| 201 | #define SCORE603E_IRQ12 ( Score_IRQ_First + 12 ) |
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| 202 | #define SCORE603E_IRQ13 ( Score_IRQ_First + 13 ) |
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| 203 | #define SCORE603E_IRQ14 ( Score_IRQ_First + 14 ) |
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| 204 | #define SCORE603E_IRQ15 ( Score_IRQ_First + 15 ) |
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| 205 | |
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[6128a4a] | 206 | #define SCORE603E_TIMER1_IRQ SCORE603E_IRQ00 |
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| 207 | #define SCORE603E_TIMER2_IRQ SCORE603E_IRQ01 |
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| 208 | #define SCORE603E_TIMER3_IRQ SCORE603E_IRQ02 |
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| 209 | #define SCORE603E_85C30_1_IRQ SCORE603E_IRQ03 |
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| 210 | #define SCORE603E_85C30_0_IRQ SCORE603E_IRQ04 |
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| 211 | #define SCORE603E_RTC_IRQ SCORE603E_IRQ05 |
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| 212 | #define SCORE603E_PCI_IRQ_0 SCORE603E_IRQ06 |
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| 213 | #define SCORE603E_PCI_IRQ_1 SCORE603E_IRQ07 |
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| 214 | #define SCORE603E_PCI_IRQ_2 SCORE603E_IRQ08 |
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| 215 | #define SCORE603E_PCI_IRQ_3 SCORE603E_IRQ09 |
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| 216 | #define SCORE603E_UNIVERSE_IRQ SCORE603E_IRQ10 |
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| 217 | #define SCORE603E_1553_IRQ SCORE603E_IRQ11 |
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| 218 | #define SCORE603E_MAIL_BOX_IRQ_0 SCORE603E_IRQ12 |
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| 219 | #define SCORE603E_MAIL_BOX_IRQ_1 SCORE603E_IRQ13 |
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| 220 | #define SCORE603E_MAIL_BOX_IRQ_2 SCORE603E_IRQ14 |
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| 221 | #define SCORE603E_MAIL_BOX_IRQ_3 SCORE603E_IRQ15 |
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| 222 | |
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| 223 | /* |
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| 224 | * The Score FPGA maps all interrupts comming from the PMC card to |
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[9c448e1] | 225 | * the FPGA interrupt SCORE603E_PCI_IRQ_0 the PMC status word must be |
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| 226 | * read to indicate which interrupt was chained to the FPGA. |
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| 227 | */ |
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| 228 | #define SCORE603E_IRQ16 ( Score_IRQ_First + 16 ) |
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| 229 | #define SCORE603E_IRQ17 ( Score_IRQ_First + 17 ) |
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| 230 | #define SCORE603E_IRQ18 ( Score_IRQ_First + 18 ) |
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| 231 | #define SCORE603E_IRQ19 ( Score_IRQ_First + 19 ) |
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| 232 | |
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| 233 | /* |
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| 234 | * IRQ'a read from the PMC card |
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| 235 | */ |
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| 236 | #define SCORE603E_85C30_4_IRQ SCORE603E_IRQ16 /* SCC 422-1 */ |
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| 237 | #define SCORE603E_85C30_2_IRQ SCORE603E_IRQ17 /* SCC 232-1 */ |
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| 238 | #define SCORE603E_85C30_5_IRQ SCORE603E_IRQ18 /* SCC 422-2 */ |
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| 239 | #define SCORE603E_85C30_3_IRQ SCORE603E_IRQ19 /* SCC 232-2 */ |
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| 240 | |
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| 241 | #define MAX_BOARD_IRQS SCORE603E_IRQ19 |
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| 242 | |
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| 243 | /* |
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| 244 | * BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID for the shared timer |
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| 245 | * driver. |
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| 246 | */ |
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| 247 | |
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| 248 | #define BSP_TIMER_AVG_OVERHEAD 4 /* It typically takes xx clicks */ |
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| 249 | /* to start/stop the timer. */ |
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| 250 | #define BSP_TIMER_LEAST_VALID 1 /* Don't trust a value lower than this */ |
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| 251 | |
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| 252 | /* |
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[6128a4a] | 253 | * Convert decrement value to tenths of microsecnds (used by |
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[9c448e1] | 254 | * shared timer driver). |
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| 255 | * |
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| 256 | * + CPU has a 66.67 Mhz bus, |
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| 257 | * + There are 4 bus cycles per click |
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| 258 | * + We return value in 1/10 microsecond units. |
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| 259 | * Modified following equation to integer equation to remove |
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| 260 | * floating point math. |
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| 261 | * (int) ((float)(_value) / ((66.67 * 0.1) / 4.0)) |
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| 262 | */ |
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| 263 | |
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| 264 | #define BSP_Convert_decrementer( _value ) \ |
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| 265 | (int) (((_value) * 4000) / 6667) |
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| 266 | |
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| 267 | #endif |
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| 268 | |
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| 269 | #ifdef __cplusplus |
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| 270 | } |
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| 271 | #endif |
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