1 | /* |
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2 | * This include file contains all board IO definitions. |
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3 | */ |
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4 | |
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5 | /* |
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6 | * COPYRIGHT (c) 1989-2014. |
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7 | * On-Line Applications Research Corporation (OAR). |
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8 | * |
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9 | * The license and distribution terms for this file may be |
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10 | * found in the file LICENSE in this distribution or at |
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11 | * http://www.rtems.org/license/LICENSE. |
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12 | */ |
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13 | |
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14 | #ifndef _BSP_H |
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15 | #define _BSP_H |
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16 | |
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17 | #define BSP_ZERO_WORKSPACE_AUTOMATICALLY TRUE |
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18 | |
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19 | #include <bspopts.h> |
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20 | #include <bsp/default-initial-extension.h> |
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21 | #include <rtems.h> |
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22 | #include <rtems/console.h> |
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23 | #include <libcpu/io.h> |
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24 | #include <rtems/clockdrv.h> |
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25 | #include <bsp/vectors.h> |
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26 | |
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27 | #ifdef ASM |
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28 | /* Definition of where to store registers in alignment handler */ |
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29 | #define ALIGN_REGS 0x0140 |
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30 | |
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31 | #else |
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32 | #include <rtems.h> |
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33 | #include <rtems/console.h> |
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34 | #include <rtems/clockdrv.h> |
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35 | #include <rtems/iosupp.h> |
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36 | |
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37 | /* |
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38 | * We no longer support the first generation board. |
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39 | */ |
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40 | |
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41 | #include <gen2.h> |
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42 | #include <bsp/irq.h> |
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43 | |
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44 | #ifdef __cplusplus |
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45 | extern "C" { |
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46 | #endif |
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47 | |
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48 | /* |
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49 | * The following macro calculates the Baud constant. For the Z8530 chip. |
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50 | * |
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51 | * Note: baud constant = ((clock frequency / Clock_X) / (2 * Baud Rate)) - 2 |
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52 | * for the Score603e ((10,000,000 / 16) / (2 * Baud Rate)) - 2 |
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53 | */ |
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54 | #define _Score603e_Z8530_Baud( _frequency, _clock_by, _baud_rate ) \ |
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55 | ( (_frequency /( _clock_by * 2 * _baud_rate)) - 2) |
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56 | |
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57 | #define Score603e_Z8530_Chip1_Baud( _value ) \ |
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58 | _Score603e_Z8530_Baud( SCORE603E_85C30_1_CLOCK, \ |
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59 | SCORE603E_85C30_1_CLOCK_X, _value ) |
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60 | |
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61 | #define Score603e_Z8530_Chip0_Baud( _value ) \ |
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62 | _Score603e_Z8530_Baud( SCORE603E_85C30_0_CLOCK, \ |
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63 | SCORE603E_85C30_0_CLOCK_X, _value ) |
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64 | |
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65 | #define Initialize_Board_ctrl_register() \ |
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66 | *SCORE603E_BOARD_CTRL_REG = (*SCORE603E_BOARD_CTRL_REG | \ |
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67 | SCORE603E_BRD_FLASH_DISABLE_MASK) |
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68 | |
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69 | #define Processor_Synchronize() \ |
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70 | __asm__ volatile(" eieio ") |
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71 | |
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72 | |
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73 | /* Constants */ |
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74 | |
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75 | /* |
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76 | * Device Driver Table Entries |
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77 | */ |
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78 | |
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79 | /* |
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80 | * NOTE: Use the standard Console driver entry |
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81 | */ |
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82 | |
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83 | /* |
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84 | * NOTE: Use the standard Clock driver entry |
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85 | */ |
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86 | |
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87 | /* |
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88 | * Information placed in the linkcmds file. |
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89 | */ |
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90 | |
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91 | extern int RAM_START; |
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92 | extern int RAM_END; |
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93 | extern int RAM_SIZE; |
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94 | |
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95 | extern int PROM_START; |
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96 | extern int PROM_END; |
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97 | extern int PROM_SIZE; |
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98 | |
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99 | extern int CLOCK_SPEED; |
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100 | extern int CPU_PPC_CLICKS_PER_MS; |
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101 | |
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102 | extern int end; /* last address in the program */ |
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103 | |
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104 | /* |
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105 | * Total RAM available |
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106 | */ |
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107 | extern int end; /* last address in the program */ |
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108 | extern int RAM_END; |
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109 | extern uint32_t BSP_mem_size; |
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110 | |
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111 | |
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112 | /* |
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113 | * How many libio files we want |
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114 | */ |
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115 | |
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116 | #define BSP_LIBIO_MAX_FDS 20 |
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117 | |
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118 | /* functions */ |
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119 | |
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120 | /* |
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121 | * |
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122 | */ |
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123 | rtems_isr_entry set_EE_vector( |
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124 | rtems_isr_entry handler, /* isr routine */ |
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125 | rtems_vector_number vector /* vector number */ |
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126 | ); |
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127 | void initialize_external_exception_vector(void); |
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128 | |
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129 | /* |
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130 | * Hwr_init.c |
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131 | */ |
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132 | void init_PCI(void); |
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133 | void init_RTC(void); |
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134 | void instruction_cache_enable(void); |
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135 | void data_cache_enable(void); |
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136 | |
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137 | void initialize_PCI_bridge(void); |
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138 | uint16_t read_and_clear_irq(void); |
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139 | void set_irq_mask(uint16_t value); |
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140 | uint16_t get_irq_mask(void); |
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141 | |
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142 | /* |
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143 | * universe.c |
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144 | */ |
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145 | void initialize_universe(void); |
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146 | void set_irq_mask(uint16_t value); |
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147 | uint16_t get_irq_mask(void); |
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148 | void unmask_irq(uint16_t irq_idx); |
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149 | void mask_irq(uint16_t irq_idx); |
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150 | void init_irq_data_register(void); |
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151 | uint16_t read_and_clear_PMC_irq(uint16_t irq); |
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152 | bool Is_PMC_IRQ( uint32_t pmc_irq, uint16_t status_word); |
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153 | uint16_t read_and_clear_irq(void); |
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154 | void set_vme_base_address(uint32_t base_address); |
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155 | uint32_t get_vme_slave_size(void); |
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156 | void set_vme_slave_size (uint32_t size); |
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157 | |
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158 | /* |
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159 | * FPGA.c |
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160 | */ |
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161 | void initialize_PCI_bridge(void); |
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162 | void init_irq_data_register(void); |
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163 | uint32_t Read_pci_device_register(uint32_t address); |
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164 | void Write_pci_device_register(uint32_t address, uint32_t data); |
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165 | |
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166 | /* flash.c */ |
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167 | unsigned int SCORE603e_FLASH_Disable(uint32_t unused); |
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168 | unsigned int SCORE603e_FLASH_verify_enable(void); |
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169 | unsigned int SCORE603e_FLASH_Enable_writes(uint32_t area); |
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170 | |
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171 | /* |
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172 | * PCI.c |
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173 | */ |
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174 | uint32_t PCI_bus_read(volatile uint32_t *_addr); |
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175 | void PCI_bus_write(volatile uint32_t *_addr, uint32_t _data); |
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176 | |
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177 | #define BSP_FLASH_ENABLE_WRITES( _area) SCORE603e_FLASH_Enable_writes( _area ) |
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178 | #define BSP_FLASH_DISABLE_WRITES(_area) SCORE603e_FLASH_Disable( _area ) |
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179 | |
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180 | #define Convert_Endian_32( _data ) \ |
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181 | ( ((_data&0x000000ff)<<24) | ((_data&0x0000ff00)<<8) | \ |
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182 | ((_data&0x00ff0000)>>8) | ((_data&0xff000000)>>24) ) |
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183 | |
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184 | #define Convert_Endian_16( _data ) \ |
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185 | ( ((_data&0x00ff)<<8) | ((_data&0xff00)>>8) ) |
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186 | |
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187 | /* |
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188 | * Interfaces to required Clock Driver support methods |
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189 | */ |
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190 | int BSP_disconnect_clock_handler(void); |
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191 | int BSP_connect_clock_handler(void); |
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192 | |
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193 | #ifdef __cplusplus |
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194 | } |
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195 | #endif |
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196 | |
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197 | #endif /* ASM */ |
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198 | |
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199 | #endif |
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