source: rtems/c/src/lib/libbsp/powerpc/score603e/include/bsp.h @ 42b6dd2a

4.104.115
Last change on this file since 42b6dd2a was 42b6dd2a, checked in by Jennifer Averett <Jennifer.Averett@…>, on 05/05/09 at 16:24:04

2009-05-05 Jennifer Averett <jennifer.averett@…>

  • Makefile.am, configure.ac, preinstall.am, PCI_bus/PCI.c, PCI_bus/PCI.h, PCI_bus/flash.c, PCI_bus/universe.c, console/85c30.c, console/85c30.h, console/console.c, console/consolebsp.h, console/tbl85c30.c, include/bsp.h, include/gen2.h, include/irq-config.h, include/tm27.h, irq/FPGA.c, irq/irq.h, irq/irq_init.c, start/start.S, startup/Hwr_init.c, startup/bspstart.c, startup/linkcmds, timer/timer.c, tod/tod.c, vme/VMEConfig.h: Updated and tested with latest interrupt source. Modified with latest memory allocation, but this needs testing.
  • irq/no_pic.c: New file.
  • Property mode set to 100644
File size: 4.5 KB
Line 
1/*  bsp.h
2 *
3 *  This include file contains all board IO definitions.
4 *
5 *  COPYRIGHT (c) 1989-2009.
6 *  On-Line Applications Research Corporation (OAR).
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.rtems.com/license/LICENSE.
11 *
12 *  $Id$
13 */
14
15#ifndef _BSP_H
16#define _BSP_H
17
18#ifdef __cplusplus
19extern "C" {
20#endif
21
22#define BSP_ZERO_WORKSPACE_AUTOMATICALLY TRUE
23
24#include <bspopts.h>
25#include <rtems.h>
26#include <rtems/console.h>
27#include <libcpu/io.h>
28#include <rtems/clockdrv.h>
29#include <bsp/vectors.h>
30
31/*
32 *  confdefs.h overrides for this BSP:
33 *   - termios serial ports (defaults to 1)
34 *   - Interrupt stack space is not minimum if defined.
35 */
36
37#if (HAS_PMC_PSC8)
38#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS (4 + 4)
39#else
40#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS (4)
41#endif
42
43#ifdef ASM
44/* Definition of where to store registers in alignment handler */
45#define ALIGN_REGS 0x0140
46
47#else
48#include <rtems.h>
49#include <rtems/console.h>
50#include <rtems/clockdrv.h>
51#include <rtems/iosupp.h>
52
53/*
54 *  We no longer support the first generation board.
55 */
56
57#include <gen2.h>
58#include <bsp/irq.h>
59
60/*
61 * The following macro calculates the Baud constant. For the Z8530 chip.
62 *
63 * Note: baud constant = ((clock frequency / Clock_X) / (2 * Baud Rate)) - 2
64 *       for the Score603e ((10,000,000 / 16) / (2 * Baud Rate)) - 2
65 */
66#define _Score603e_Z8530_Baud( _frequency, _clock_by, _baud_rate  )   \
67  ( (_frequency /( _clock_by * 2 * _baud_rate))  - 2)
68
69#define Score603e_Z8530_Chip1_Baud( _value ) \
70  _Score603e_Z8530_Baud( SCORE603E_85C30_1_CLOCK, \
71     SCORE603E_85C30_1_CLOCK_X, _value )
72
73#define Score603e_Z8530_Chip0_Baud( _value ) \
74  _Score603e_Z8530_Baud( SCORE603E_85C30_0_CLOCK, \
75     SCORE603E_85C30_0_CLOCK_X, _value )
76
77#define Initialize_Board_ctrl_register()                         \
78  *SCORE603E_BOARD_CTRL_REG = (*SCORE603E_BOARD_CTRL_REG |       \
79                               SCORE603E_BRD_FLASH_DISABLE_MASK)
80
81#define Processor_Synchronize() \
82  asm volatile(" eieio ")
83
84
85/* Constants */
86
87/*
88 *  Device Driver Table Entries
89 */
90
91/*
92 * NOTE: Use the standard Console driver entry
93 */
94
95/*
96 * NOTE: Use the standard Clock driver entry
97 */
98
99/*
100 *  Information placed in the linkcmds file.
101 */
102
103extern int   RAM_START;
104extern int   RAM_END;
105extern int   RAM_SIZE;
106
107extern int   PROM_START;
108extern int   PROM_END;
109extern int   PROM_SIZE;
110
111extern int   CLOCK_SPEED;
112extern int   CPU_PPC_CLICKS_PER_MS;
113
114extern int   end;        /* last address in the program */
115
116/*
117 * Total RAM available
118 */
119extern int        end;        /* last address in the program */
120extern int        RAM_END;
121extern uint32_t   BSP_mem_size;
122
123
124/*
125 * How many libio files we want
126 */
127
128#define BSP_LIBIO_MAX_FDS       20
129
130/* functions */
131
132/*
133 *
134 */
135rtems_isr_entry  set_EE_vector(
136  rtems_isr_entry     handler,                  /* isr routine        */
137  rtems_vector_number vector                    /* vector number      */
138);
139void initialize_external_exception_vector ();
140
141/*
142 * console.c
143 */
144void BSP_fatal_return( void );
145
146/*
147 * Hwr_init.c
148 */
149void init_PCI();
150void instruction_cache_enable ();
151void data_cache_enable ();
152
153void initialize_PCI_bridge ();
154uint16_t         read_and_clear_irq ();
155void set_irq_mask(
156  uint16_t         value
157);
158uint16_t         get_irq_mask();
159
160/*
161 * universe.c
162 */
163void initialize_universe();
164
165void set_irq_mask(
166  uint16_t         value
167);
168
169uint16_t         get_irq_mask();
170
171void unmask_irq(
172  uint16_t         irq_idx
173);
174
175void mask_irq(
176  uint16_t         irq_idx
177);
178
179void init_irq_data_register();
180
181uint16_t         read_and_clear_PMC_irq(
182  uint16_t            irq
183);
184
185bool Is_PMC_IRQ(
186  uint32_t           pmc_irq,
187  uint16_t           status_word
188);
189
190uint16_t         read_and_clear_irq();
191
192/*
193 * FPGA.c
194 */
195void initialize_PCI_bridge ();
196
197/* flash.c */
198
199unsigned int SCORE603e_FLASH_Disable(
200  uint32_t                       unused
201);
202unsigned int SCORE603e_FLASH_verify_enable();
203unsigned int SCORE603e_FLASH_Enable_writes(
204  uint32_t                       area        /* Unused  */
205);
206
207#define BSP_FLASH_ENABLE_WRITES( _area) SCORE603e_FLASH_Enable_writes( _area )
208#define BSP_FLASH_DISABLE_WRITES(_area) SCORE603e_FLASH_Disable( _area )
209
210#define Convert_Endian_32( _data ) \
211  ( ((_data&0x000000ff)<<24) | ((_data&0x0000ff00)<<8) |  \
212    ((_data&0x00ff0000)>>8)  | ((_data&0xff000000)>>24) )
213
214#define Convert_Endian_16( _data ) \
215  ( ((_data&0x00ff)<<8) | ((_data&0xff00)>>8) )
216
217#endif /* ASM */
218
219#ifdef __cplusplus
220}
221#endif
222
223#endif
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